Three-dimensional stacked high-density packaging structure based on multi-core particle local interconnection bridge
By using a three-dimensional stacked high-density packaging structure with multi-core local interconnect bridges, the high cost and thermal expansion coefficient mismatch issues of high-density interconnect packaging are solved, achieving high-performance, low-cost chip interconnects and improving computing performance and reliability.
Patent Information
- Application Number
- CN202520141151.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-01-21
AI Technical Summary
In existing technologies, high-density interconnect packaging suffers from high cost, complex processes, and thermal expansion coefficient mismatch, which limits chip performance improvement and reliability.
A three-dimensional stacked high-density packaging structure with multi-core local interconnect bridges is adopted. High-density interconnection between cores is achieved by using interconnect bridges made of materials such as silicon or glass. Bonding quality is improved by solder balls and flux, and organic materials are used to reduce thermal expansion coefficient mismatch.
It improves interconnect density and data transmission smoothness, enhances computing performance and energy efficiency, reduces package size, and improves thermal expansion coefficient mismatch.
Smart Images
Figure CN223912864U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to, especially in a kind of three-dimensional stacking high-density packaging structure based on multi-core particle local interconnection bridge. BACKGROUND
[0002] With the development of advanced process slowing down, the improvement of chip performance gradually slows down, and the traditional Moore's law also faces the risk of failure. With the integrated circuit technology gradually advancing to 3nm or even 2nm node, the design and development cost of a single system chip (SoC) has broken through 1 billion US dollars, and the manufacturing of large chip is difficult, with low yield, leading to gradually declining economic benefits. Under this background, Chiplet technology emerged as the times require, by disassembling the system chip into multiple small-size, cross-process node high-yield chiplets, and realizing IP reuse, thereby effectively reducing chip area and production cost, while integrating multiple functional modules into a single chip through advanced packaging technology to improve its overall performance and functionality.
[0003] High-density interconnection between chiplets is the core of high-performance packaging. Currently, mainstream 2.5D and 3D packaging technologies rely on high-density wiring silicon interposers. These silicon interposers are manufactured through wafer process, capable of achieving line width and spacing less than 2μm, thereby significantly improving the bandwidth and interconnection performance between chiplets, and thus improving the overall performance of the package. However, silicon interposers based on wafer process have high manufacturing difficulty, and require the use of high aspect ratio through silicon vias and complex redistribution layers (RDL), thus requiring high process requirements, and only a few advanced wafer manufacturers have the related manufacturing capabilities, while the high development cost also limits its promotion in practical applications.
[0004] To overcome the cost and process challenges of large-size silicon interposers, Intel proposed the EMIB (Embedded Multi-die Interconnect Bridge) technology. By embedding small-size silicon bridges into the substrate to achieve 2.5D packaging, this technology effectively solves some packaging problems. However, EMIB technology also faces some challenges. First, the silicon bridge still needs to use wafer manufacturing process, with a long production cycle, and as the number of chiplets increases, the number of silicon bridges also increases, leading to rising process complexity and cost. Second, the coefficient of thermal expansion (CTE) of silicon is 2.4ppm / ℃, while the CTE of common FCBGA packaging substrate is 14.2ppm / ℃, there is a significant mismatch in thermal expansion coefficient between the two. When too many silicon bridges are embedded on the substrate, asymmetric stress and strain may occur on both sides of the substrate, leading to adhesion failure, circuit cracking, and other problems between the substrate and the silicon bridge, thereby affecting the overall reliability of the package.
[0005] Therefore, it is urgent to develop a 3D packaging technology with lower cost, smaller coefficient of thermal expansion mismatch and higher reliability to adapt to the increasingly complex packaging requirements in the future. Utility model content
[0006] The utility model discloses to the following technical background exists the shortage, provide a 3D packaging scheme of high interconnection density, small package size, high reliability.
[0007] In order to achieve the above object, the utility model provides a kind of three-dimensional stacking high-density packaging structure based on multi-core particle local interconnection bridge, at least including substrate, first chip layer, second chip layer and interconnection bridge, the substrate is provided with a plurality of solder balls, the plurality of core particles of the first chip layer are bonded and packaged with the substrate by the solder ball, the second chip layer is arranged above the first chip layer, the interconnection bridge is arranged between the second chip layer and the first chip layer, the core particle of the second chip layer is bonded and packaged with corresponding core particle of the first chip layer by the solder ball, while forming high-density interconnection by the interconnection bridge, the line width / line spacing of the interconnection bridge is <10 μm / μm.
[0008] Further, the material of the interconnection bridge is silicon or glass.
[0009] Further, the material of the interconnection bridge is organic material.
[0010] Further, the upper surface and the lower surface of the interconnection bridge are provided with a plurality of solder joints.
[0011] Further, the number of core particles of the first chip layer and the second chip layer is one or two.
[0012] Further, the number of core particles of the first chip layer and the second chip layer is three or more.
[0013] Further, the three-dimensional stacking high-density packaging structure further comprises a third chip layer, the third chip layer is arranged above the second chip layer, the second chip layer and the first chip layer are high-density interconnected by the first interconnection bridge, and the third chip layer and the second chip layer are high-density interconnected by the second interconnection bridge.
[0014] The above scheme of the utility model has the following beneficial effects:
[0015] The three-dimensional stacked high-density packaging structure based on the multi-core particle local interconnection bridge improves the interconnection density, improves the smoothness of data flow in the device (system), and improves the performance.
[0016] Other advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 Figure 1 is a two-layer chip layer three-dimensional stacked high-density packaging structure schematic diagram of the present application;
[0018] Figure 2 Figure 2 is a three-layer chip layer three-dimensional stacked high-density packaging structure schematic diagram of the present application;
[0019] Figure 3 Figure 3 is a process flow diagram of case 1 of the present application.
[0020] BRIEF DESCRIPTION OF DRAWINGS
[0021] 1 - substrate; 2 - first chip layer; 3 - second chip layer; 4 - interconnection bridge; 5 - solder ball; 6 - third chip layer; 7 - plastic sealing material; DETAILED DESCRIPTION
[0022] In order to make the technical problems, technical schemes and advantages of the present application clearer, the following will be described in detail in conjunction with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the present application. In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0023] In the description of the utility model, it is necessary to explain, the term "center", "upper", "lower", "left", "right", "vertical", "horizontal", "internal", "external" and so on indicate the orientation or position relation based on the orientation or position relation shown in the drawing, only for the convenience of describing the utility model and simplifying the description, and not indicate or imply that the device or element indicated must have a particular orientation, a particular orientation and operation, therefore, it cannot be understood as the limitation of the utility model. In addition, the term "first", "second", "third" is only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0024] In the description of the utility model, it is necessary to explain, unless otherwise explicitly provided and limited, the term "installation", "connection", "connection" should be broad understanding, for example, it can be locking connection, or detachable connection, or integrally connected, it can be mechanical connection, or electrical connection, it can be directly connected, or indirectly connected through intermediate medium, it can be the communication inside two elements. For ordinary skilled in the art, the specific meaning of the above-mentioned terms in the utility model can be understood according to the specific circumstances.
[0025] As Figure 1 The embodiment of the utility model provides a kind of three-dimensional stacked high-density packaging structure based on multi-core particle local interconnection bridge, including substrate 1, first chip layer 2, second chip layer 3 and interconnection bridge 4.Wherein, substrate 1 is provided with a plurality of solder balls 5. The plurality of core particles of first chip layer 2 are bonded and packaged with substrate 1 by solder ball 5, to complete the communication connection with substrate 1. Second chip layer 3 is packaged above first chip layer 2, and the core particle of second chip layer 3 is bonded with the corresponding core particle of first chip layer 2 by solder ball 5 to form conventional bond on one hand, and high-density interconnection is formed by interconnection bridge 4 between another, based on the setting of interconnection bridge 4, data flow in device (system) is more smooth, and performance is greatly improved.
[0026] In the embodiment, the material of the interconnection bridge 4 can be silicon, glass or an organic material (such as polyimide, ABF, etc.). The interconnection bridge 4 can be formed by using the existing substrate 1 manufacturing process (such as subtractive method, additive method, semi-additive method, ETS, etc.) to form multiple layers of conductive lines on the interconnection bridge 4, with a line width / line spacing < 10 μm / μm. Since the manufacturing process of the substrate 1 is already very mature, compared with the silicon adapter plate, the process difficulty of the interconnection bridge 4 is smaller and the processing cost is lower. The upper surface and the lower surface of the interconnection bridge 4 are provided with multiple soldering points, which are used to interconnect with the first chip layer 2 below and the second chip layer 3 above, thereby realizing vertical high-density interconnection between the first chip layer 2 and the second chip layer 3. In the multi-chip package (MCP) or system on chip (SoC), the interconnection bridge 4 provides a communication channel between multiple dies, ensuring seamless data transmission between dies and improving collaborative working ability. In this way, the device (system) can flexibly match multiple chips to improve computing performance and energy efficiency.
[0027] It should be noted that when the die and the interconnection bridge 4 are bonded and packaged, it is better to uniformly spray a layer of flux on the corresponding surface of the die, which plays a role in soldering during the packaging process of the interconnection bridge 4, thereby improving the quality of the bonding and packaging between the die and the interconnection bridge 4 and ensuring the smoothness of data flow between the upper and lower layers.
[0028] In the embodiment, the first chip layer 2 and the second chip layer 3 shown each include two dies, and the high-density interconnection between the two dies of the first chip layer 2 and the second chip layer 3 is realized by using one interconnection bridge 4. However, the embodiment is not limited thereto, and when the first chip layer 2 and the second chip layer 3 each include more dies, the high-density interconnection between the more dies of the first chip layer 2 and the second chip layer 3 can also be realized by using an interconnection bridge 4 with a corresponding size.
[0029] Meanwhile, as shown in Figure 2 , the setting of the interconnection bridge 4 can also realize three-dimensional stacked packaging of more chip layers. For example, when a third chip layer 6 needs to be packaged, a layer of flux is uniformly sprayed on the upper surface of the second chip layer 3 after the packaging of the second chip layer 3 is completed, another interconnection bridge 4 is installed, and then the third chip layer 6 is stacked so that the dies of the third chip layer 6 and the second chip layer 3 are bonded and packaged with the interconnection bridge 4.
[0030] It is worth mentioning that in the embodiment, the size of the interconnection bridge 4 can be designed to be smaller compared with the adapter plate, so that the overall size of the three-dimensional stacked packaging structure can be reduced, and the influence of the mismatch of the thermal expansion coefficient is smaller. In particular, when the interconnection bridge 4 is made of ABF or other organic materials, the thermal expansion coefficient of the interconnection bridge 4 can be consistent with that of the substrate 1, so that the problem of mismatch of the thermal expansion coefficient can be almost completely avoided.
[0031] The following further illustrates the present solution through specific cases. In case 1, a three-dimensional stacked structure with two chip layers is packaged, as shown in FIG. 1, including the following steps: Figure 3
[0032] S1, the first chip layer 2 is mounted, and after the processes of flip chip mounting, high-temperature reflow, cleaning, drying, bottom filling glue, and solidification, the reliable connection between the substrate 1 and the first chip layer 2 is completed;
[0033] S2, the interconnection bridge 4 is packaged, and the interconnection bridge 4 is bonded and packaged with the first chip layer 2 by uniformly spraying a layer of flux on the upper surface of the first chip layer 2 through equipment;
[0034] S3, the second chip layer 3 is stacked, and after the processes of flip chip mounting, high-temperature reflow, cleaning, drying, bottom filling glue, and solidification, the second chip layer 3 is reliably connected with the first chip layer 2 through the interconnection bridge 4 and the solder ball 5;
[0035] S4, a special mold after optimization design is used to complete the plastic packaging of the chip around once by using a high-precision vacuum plastic packaging machine. Before plastic packaging, plasma cleaning is used to reduce surface tension, increase the flow performance of the plastic packaging material 7, and reduce plastic packaging voids. During the plastic packaging process, the temperature, pressure, and time are strictly controlled to ensure that the plastic packaging material 7 completes the complete filling of the bottom through the flow guide hole of the substrate 1. After plastic packaging is completed, the moisture in the plastic packaging material 7 is removed through a high-temperature oven.
[0036] After the above key process flow, the three-dimensional stacked packaging of the two chip layers is completed, and the packaging structure as shown in FIG. 2 is obtained. Figure 1
[0037] In case 2, a structure with three chip layers is packaged, including the following steps:
[0038] S1, the first chip layer 2 is mounted, and after the processes of flip chip mounting, high-temperature reflow, cleaning, drying, bottom filling glue, and solidification, the reliable connection between the substrate 1 and the first chip layer 2 is completed;
[0039] S2, the first interconnection bridge 4 is packaged, and the first interconnection bridge 4 is bonded and packaged with the first chip layer 2 by uniformly spraying a layer of flux on the upper surface of the first chip layer 2 through equipment;
[0040] S3, the second chip layer 3 is stacked, and after the processes of flip chip mounting, high-temperature reflow, cleaning, drying, bottom filling glue, and solidification, the second chip layer 3 is reliably connected with the first chip layer 2 through the interconnection bridge 4 and the solder ball 5;
[0041] S4, the second interconnection bridge 4 is packaged, and the second interconnection bridge 4 is bonded and packaged with the second chip layer 3 by uniformly spraying a layer of flux on the upper surface of the second chip layer 3 through equipment;
[0042] S5, after the third chip layer 6 is flip-chip mounted, high-temperature reflow, cleaning, drying, underfill glue, curing and other processes, the third chip layer 6 is reliably connected to the second chip layer 3 and the first chip layer 2 through the interconnection bridge 4 and the solder ball 5;
[0043] S6, through the special mold after optimization design, using high-precision vacuum packaging machine, one-time completion of the chip around the plastic package. Among them, the surface tension is reduced by using plasma cleaning before plastic packaging, the flow performance of the plastic material 7 is increased and the plastic cavity is reduced; strictly control the temperature, pressure and time during the plastic packaging process to ensure that the plastic material 7 completes the complete filling of the bottom through the guide hole of the substrate 1; after the plastic packaging is completed, the moisture in the plastic material 7 is removed through the high-temperature oven.
[0044] Through the above key process flow, the three-dimensional stacked packaging of the three chip layers is completed, and the high-density packaging structure shown in the figure is obtained. Figure 2
[0045] In summary, the three-dimensional stacked high-density packaging structure based on the multi-core local interconnection bridge provided by the embodiment effectively improves the interconnection density by interconnecting the core particles of different layers through the interconnection bridge 4, improves the smoothness of data flow within the device (system), thereby improving the performance, seamless data transmission between chips, and improves the collaborative work capability, so that the device (system) can flexibly match multiple chips to improve the computing performance and energy efficiency ratio; In addition, the three-dimensional stacking and high-density packaging structure of the interconnection bridge 4 significantly reduces the packaging size, and the thermal expansion coefficient mismatch problem can be improved compared with the prior art.
[0046] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combination of the technical features does not exist Contradiction, it should be considered as the scope of the description.
[0047] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A multi-chip-particle local interconnect bridge based three-dimensional stacked high-density package structure, characterized by, At least comprising a substrate, a first chip layer, a second chip layer and an interconnection bridge, a plurality of solder balls are arranged on the substrate, a plurality of core particles of the first chip layer are bonded and packaged with the substrate through the solder balls, the second chip layer is arranged above the first chip layer, the interconnection bridge is arranged between the second chip layer and the first chip layer, the core particles of the second chip layer and the corresponding core particles of the first chip layer are bonded and packaged through the solder balls, and meanwhile high-density interconnection is formed through the interconnection bridge, the line width / space of the interconnection bridge is <10μm / μm.
2. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The material of the interconnection bridge is silicon or glass.
3. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The material of the interconnection bridge is an organic material.
4. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The upper surface and the lower surface of the interconnection bridge are each provided with a plurality of solder points.
5. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The number of core particles of the first chip layer and the second chip layer is one or two.
6. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The number of core particles of the first chip layer and the second chip layer is more than three.
7. The multi-die local interconnect bridge based three-dimensional stacked high-density package structure of claim 1, wherein, The three-dimensional stacked high-density packaging structure further comprises a third chip layer, the third chip layer is arranged above the second chip layer, the second chip layer and the first chip layer are high-density interconnected through a first interconnection bridge, and the third chip layer and the second chip layer are high-density interconnected through a second interconnection bridge.