Drain electrode leading-out terminal structure suitable for MOSFET CSP packaging

Abstract

The utility model relates to the technical field of semiconductor chips, in particular to a drain electrode leading-out end structure suitable for MOSFET CSP packaging, which comprises a chip body, and the chip body at least comprises a metal layer, an epitaxial layer and a passivation layer which are continuously arranged from bottom to top in the vertical direction. The metal layer is arranged on the epitaxial layer, the metal layer is arranged on the epitaxial layer, the metal layer is arranged on the epitaxial layer, the metal layer is divided into an MOSFET body area located at the center position and a drain electrode external connection area arranged around the MOSFET body area on the horizontal plane projection, and the metal layer is characterized in that the metal layer is electrically connected with a drain electrode leading-out end on the MOSFET body area, and two vertically-through and annular separation grooves are formed in the epitaxial layer at the drain electrode external connection area; a plurality of through holes which are uniformly distributed are formed in the epitaxial layer between the two separation grooves in an up-down penetrating manner; according to the utility model, the metal layer is firstly electrically connected with the drain electrode leading-out end on the MOSFET body area, and then the position of the external pin is arranged at the front position of the chip body through the polycrystal and the metal strip, thereby facilitating the external connection of a circuit, and reducing the size and area of the chip body at the same time.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor chip, concretely is a drain lead-out end structure suitable for MOSFET CSP package. BACKGROUND

[0002] Metal-oxide-semiconductor field-effect transistor (MOSFET for short) is a kind of semiconductor used in digital and analog circuits, and also a kind of useful power device.As a kind of original compact transistor, MOSFET is suitable for a wide range of electrical applications;

[0003] CSP (Chip Scale Package) package is the meaning of chip level package;CSP package is the latest generation of memory chip packaging technology, and its technical performance has new promotion;CSP package can make the ratio of chip area and packaging area more than 1:1.Extended layer 14, it is quite close to the ideal situation of 1:1, compared with BGA package, CSP package can increase storage capacity by three times in the same space;

[0004] In the general MOSFET package design, the drain is connected through the back copper plate, and then the copper plate is extended at the edge position and connected, which leads to a protruding power connection end on the side of the chip, thereby increasing the size of the chip.

[0005] Therefore, a drain lead-out end structure suitable for MOSFET CSP package is needed to reduce the size of the chip. UTILITY MODEL CONTENTS

[0006] In view of the deficiencies in the prior art, the purpose of the utility model is to provide a drain lead-out end structure suitable for MOSFET CSP package, which is directly connected to the chip body front surface by the structure of the metal layer on the chip side position of the MOSFET body area, thereby reducing the size of the chip body and increasing the packaging effect.

[0007] The technical scheme of the above technical objective is achieved by the following technical scheme: the drain lead-out end structure suitable for MOSFET CSP packaging comprises a chip body, the chip body at least comprises a metal layer, an epitaxial layer and a passivation layer which are continuously arranged from bottom to top in the vertical direction, and a MOSFET body area located at the center position and a drain external connection area arranged around the MOSFET body area are divided on the horizontal plane projection, the metal layer is electrically connected with the drain lead-out end on the MOSFET body area, two upper and lower penetrating and annularly arranged separation grooves are arranged on the epitaxial layer at the position of the drain external connection area, a plurality of uniformly distributed penetrating holes are arranged in the epitaxial layer between the two separation grooves, a high-density oxidation insulator is filled and arranged in the separation groove, a polycrystal is filled and arranged in the penetrating hole, an insulating block is arranged on the high-density oxidation insulator at the position between the passivation layer and the epitaxial layer, a metal strip is fixedly connected to the polycrystal at the position between the passivation layer and the epitaxial layer, and a region on the passivation layer leaks out part of the metal strip and uses an external connection pin.

[0008] By adopting the above technical scheme, the polycrystal and the metal strip are used, on the one hand, the drain lead-out end on the MOSFET body area can be electrically connected to the edge position of the front surface of the chip body, preventing the metal layer from needing to expand outwardly by one node and increasing the size of the chip, thereby increasing the packaging effect, and on the other hand, the drain lead-out end on the MOSFET body area can be away from the gate lead-out end on the MOSFET body area, facilitating external circuit connection; meanwhile, the high-density oxidation insulator and the insulating block are used to insulate the metal strip from the gate lead-out end on the MOSFET body area to prevent parasitic effects, thereby ensuring the stability of the chip operation.

[0009] The utility model further sets up: the passivation layer leaks out part of the metal strip area in the length, width direction of the polycrystal number all greater than the polycrystal number of the width direction between the remaining two separation grooves.

[0010] By adopting the above technical scheme, by setting the number and area of the polycrystal at different positions, there are a plurality of polycrystals below the pin position of the metal strip when the pin is connected, thereby ensuring the circuit connection effect, reducing current and voltage loss, and increasing the area of the pin position, facilitating power connection.

[0011] The utility model further sets up: the metal strip is located between the most distant ends of the two insulating blocks and extends upward.

[0012] By adopting the technical scheme, the metal strip is located between the insulating block and the high-density oxide insulator, the insulating block and the high-density oxide insulator further increase the insulation effect on the metal strip and the polycrystal, the occurrence of the parasitic effect is reduced, meanwhile, the upward extension of the metal strip increases the thickness of the electrical connection between the metal strip and the pin and makes the metal strip leak out, thereby facilitating the external circuit.

[0013] The utility model further sets up: the width of insulating block cross section area is greater than the width of high-density oxide insulator cross section area, and the insulating block covers the high-density oxide insulator on the horizontal projection.

[0014] By adopting the technical scheme, on one hand, the insulating block covers the high-density oxide insulator on the horizontal projection, and the insulating block and the high-density oxide insulator upper end surface abut, which can ensure the position electrical isolation effect between the high-density oxide insulator and the insulating block, and on the other hand, the cross section area of the insulating block is greater than that of the high-density oxide insulator, so that when the metal strip is processed, even if the metal strip extends in the horizontal direction, the metal strip can be separated from the MOSFET body area by the insulating block, the metal strip is prevented from directly contacting the MOSFET body area due to the excessive horizontal extension of the metal strip, the electrical isolation effect is further increased, the parasitic effect is reduced, and the stability of the chip operation is increased.

[0015] The utility model further sets up: the polycrystal is made of N-type substance doped polycrystal.

[0016] By adopting the technical scheme, the N-type substance doping can adjust the purity of the polycrystal and reduce the resistance of the polycrystal, the purity of the polycrystal and the concentration of the N-type substance are adjusted according to the material of the metal strip, so as to reduce the contact resistance between the polycrystal and the metal strip, reduce the energy loss, increase the stability of the chip operation, prevent the resistance from being too large to generate heat, and improve the product quality.

[0017] In summary, the utility model has the following beneficial effects:

[0018] First, the metal layer is electrically connected with the drain lead-out end on the MOSFET body area, and then the polycrystal and the metal strip are used to set the position of the external pin on the front surface of the chip body, which facilitates the external circuit, reduces the size of the chip body, separates the circuit between the polycrystal, the metal strip and the MOSFET body area by the high-density oxide insulator and the insulating block, prevents the parasitic effect, ensures that the front lead-out does not affect the current of the chip itself, increases the precision of the chip operation, and improves the use effect. DRAWINGS

[0019] Figure 1 The utility model is a structural schematic diagram;

[0020] Figure 2 This is a cross-sectional view of the present invention.

[0021] Figure 3 for Figure 2 A magnified view of a portion of point A in the middle;

[0022] Figure 4 for Figure 2 A magnified view of a portion of point B in the middle;

[0023] Figure 5 This is a schematic diagram of the epitaxial layer in this utility model.

[0024] In the picture:

[0025] 11. MOSFET body region; 12. Drain external region; 13. Metal layer; 14. Epitaxial layer; 15. Passivation layer; 16. Metal strip; 17. High-density oxide insulator; 18. Polycrystalline; 19. Insulating block; 21. Separator groove; 22. Through hole. Detailed Implementation

[0026] The present invention will now be described in detail with reference to the accompanying drawings of the embodiments thereof.

[0027] Example:

[0028] This is a drain lead structure suitable for MOSFET CSP packages, such as Figures 1 to 5 As shown, the chip includes a chip body, which includes at least a metal layer 13, an epitaxial layer 14, and a passivation layer 15 continuously disposed vertically from bottom to top. The chip body is divided on a horizontal plane by a MOSFET body region 11 located at the center and a drain external region 12 surrounding the MOSFET body region 11. The metal layer 13 is electrically connected to the drain lead on the MOSFET body region 11. Two vertically penetrating and annularly arranged partition grooves 21 are formed on the epitaxial layer 14 at the drain external region 12. A plurality of evenly distributed through-holes are disposed vertically on the epitaxial layer 14 between the two partition grooves 21. The perforation 22 and the partition groove 21 are filled with high-density oxide insulator 17. The perforation 22 is filled with polycrystalline silicon 18. An insulating block 19 is provided at the upper end of the high-density oxide insulator 17 and between the passivation layer 15 and the epitaxial layer 14. A metal strip 16 is fixedly connected at the upper end of the polycrystalline silicon 18 and between the passivation layer 15 and the epitaxial layer 14. There is a region on the passivation layer 15 that exposes part of the metal strip 16 for external pins. The number of polycrystalline silicon 18 in the length and width directions of the region on the passivation layer 15 that exposes part of the metal strip 16 is greater than the number of polycrystalline silicon 18 in the width direction between the other two partition grooves 21.

[0029] like Figures 2 to 3As shown, the metal strip 16 is located between the two insulating blocks 19 farthest apart and extends upward, the width of the cross-sectional area of the insulating block 19 is greater than the width of the cross-sectional area of the high-density oxide insulator 17, and the insulating block 19 covers the high-density oxide insulator 17 in the horizontal projection, and the polycrystal 18 is N-type substance doped polycrystal.

[0030] In the normal MOSFET structure production process, when the hole processing on the epitaxial layer 14 is performed, an additional photoetching layer is used to complete the processing of the separation groove 21, and then an additional photoetching layer is added to fill the high-density oxide insulator 17 into the separation groove 21, and the remaining steps are all changed in the normal MOSFET production process. The price of this structure can be completed by only adding two layers of photoetching layers, greatly reducing the production cost.

[0031] On this basis, the polycrystal 18 is electrically connected with the metal layer 13, and the metal layer 13 is electrically connected with the drain, so that the electrical connection between the polycrystal 18 and the drain is completed, and the structure of the metal strip 16 being electrically connected with the polycrystal 18 and the metal strip 16 being partially exposed on the front surface of the chip body is set, and then the lead-out end of the drain is set on the front surface of the chip body away from the gate lead-out end, and is electrically connected with the external circuit. On the one hand, the drain lead-out end can be set on the front surface without the need to extend the copper sheet from the side of the metal layer 13, which reduces the size area of the chip, increases the disassembly effect, and the pin can be directly led out on the chip, which increases the convenience of the external wire; on the other hand, the drain lead-out end and the gate lead-out end are separated and externally connected, which prevents the mixed chip from being electrically connected with the drain and the gate, further increases the convenience of the external wire, and also prevents the current from escaping and causing the chip to run incorrectly.

[0032] The high-density oxide insulator 17 is used to separate the polycrystal 18 from various circuits on the MOSFET body region 11, so as to prevent the parasitic effect (the parasitic effect refers to the capacitance, inductance or resistance which is not originally designed in the place, but is caused by some factors such as structure, PCB wiring, pin lead, via quality, distance between pad and ground, distance between pad and power plane, and distance between pad and printed line, material difference, device package, package pin and printed line, especially in high-speed circuits. In practical application, those small faults which are caused by the parasitic effect, are difficult to find out, and are annoying and unknown) from being generated, and the stability of the chip operation is further increased. The wider insulating block 19 is used to separate the metal strip 16, and the metal strip 16 is carried by the width of the insulating block 19 during processing, so as to further reduce the parasitic effect between the metal strip 16 and other circuits on the chip. The upward extension of the metal strip 16 can facilitate the metal strip 16 to leak out and have a certain thickness, so as to facilitate the external connection of the pin of the metal strip 16 and the connection of the electricity. The passivation layer 15 is further used to protect various structures and electronic components on the chip, so as to realize the long-term and stable operation and use of the chip.

[0033] The preferred embodiments of the present application have been described above, but the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical solutions falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the technical field, some improvements and decorations without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. A drain lead-out structure suitable for a MOSFET CSP package, comprising a chip body, the chip body comprising at least a metal layer (13), an epitaxial layer (14), and a passivation layer (15) arranged successively from bottom to top in a vertical direction, and divided in a horizontal projection into a MOSFET body region (11) located at a center position and a drain external region (12) arranged around the MOSFET body region (11), characterized in that: The metal layer (13) is electrically connected with the drain lead-out end on the MOSFET body area (11), the extension layer (14) at the position of the drain external connection area (12) is provided with two upper and lower penetrating and annularly arranged separation grooves (21), the extension layer (14) between the two separation grooves (21) is provided with a plurality of uniformly distributed penetrating holes (22) penetrating from top to bottom, the separation groove (21) is filled with a high-density oxide insulator (17), the penetrating hole (22) is filled with a polycrystal (18), the high-density oxide insulator (17) is provided with an insulating block (19) at the position between the upper end and the extension layer (14) and the passivation layer (15); The upper end of the polycrystal (18) and the position between the passivation layer (15) and the extension layer (14) are fixedly connected with a metal strip (16), and there is an area on the passivation layer (15) to leak out part of the metal strip (16) with an external connection pin.

2. A drain lead structure suitable for a MOSFET CSP package according to claim 1, wherein: The number of polycrystals (18) in the length and width directions of the area where part of the metal strip (16) leaks out on the passivation layer (15) is greater than the number of polycrystals (18) in the width direction between the other two separation grooves (21).

3. A drain lead structure suitable for a MOSFET CSP package according to claim 2, wherein: The metal strip (16) is located between the positions where the two insulating blocks (19) are farthest apart and extends upward.

4. A drain lead structure for a MOSFET CSP package according to claim 3, wherein: The width of the cross-sectional area of the insulating block (19) is greater than the width of the cross-sectional area of the high-density oxide insulator (17), and the insulating block (19) covers the high-density oxide insulator (17) in the horizontal projection.

5. The drain lead structure for a MOSFET CSP package of claim 1, wherein: The polycrystal (18) is a polycrystal doped with N-type substances.

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