Adjustable voltage clamping circuit
By using an adjustable voltage clamping circuit, the clamping voltage reference is set using Zener diode D4 and the transistor feedback control is used, which solves the problems of flexibility and high power consumption of the voltage clamping circuit, and achieves effective protection of the vehicle ECU and cost reduction.
Patent Information
- Application Number
- CN202422433870.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2034-10-09
AI Technical Summary
Existing voltage clamping circuits are insufficient in terms of adjustment flexibility and adaptability, and cannot meet the voltage clamping requirements of vehicle ECUs in different application scenarios. They also have high power consumption and current issues, which affect the lifespan and cost of the equipment.
An adjustable voltage clamping circuit is adopted, which uses a feedback control loop composed of PMOSFET, Zener diode and transistor. The clamping voltage reference is set by Zener diode D4. Combined with the connection method of resistor and transistor, the output voltage can be flexibly adjusted and protected.
In the pulse-5b test of the vehicle ECU, it effectively protects the ECU from overvoltage damage, reduces unnecessary power consumption and current, meets Class A functional requirements, and reduces costs.
Smart Images
Figure CN223926808U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit design, and in particular to a pulse voltage clamping circuit. Background Technology
[0002] In recent years, as customers' demands for ECUs to withstand 5-bit waveforms have become increasingly widespread and their requirements have continuously risen, while cost control has become increasingly stringent. Specifically: firstly, when performing pulse-5bit waveform tests, automotive ECUs must meet Class A standards, ensuring all functions remain normal; secondly, during pulse-5bit waveform experiments, transient currents must be less than 5-bit to reduce damage to the vehicle's alternator and wiring harness. However, existing technologies using commonly used analog audio signal detection circuits have the following drawbacks:
[0003] 1. Existing voltage clamping circuits lack flexibility in adjusting the clamping voltage, making it difficult to meet specific voltage clamping requirements in different applications.
[0004] 2. Existing technologies may not be well adapted to the automotive ISO76375b waveform, resulting in an inability to provide effective clamping protection in certain application scenarios.
[0005] 3. Existing voltage clamping circuits generate high current and power consumption during operation, which not only increases the operating cost of the circuit, but may also adversely affect the battery life of devices such as vehicle ECUs. Utility Model Content
[0006] The purpose of this invention is to solve the above-mentioned problems by proposing an on-board ISO76375b waveform voltage clamping circuit.
[0007] To achieve the above objectives, the following technical solution was adopted:
[0008] An adjustable voltage clamping circuit includes a PMOSFET X1, Zener diodes D1, D3, D4, resistors R2, R3, R1, and transistors Q1 and Q2. PMOSFET X1 controls the output voltage. Zener diode D2 is connected between the gate (G) and source (S) terminals of X1 and is connected to ground via R2. Transistor Q2 is connected between the gate (G) and source (S) terminals of X1. The base of transistor Q2 is connected to the collector of transistor Q1 via resistor R1. Zener diode D1 is connected to the emitter and base of transistor Q1. The base of transistor Q1 is connected to the drain (D) terminal of X1 via resistor R3. The emitter of transistor Q1 is connected to Zener diode D4, the other end of which is connected between resistor R2 and ground. Zener diode D3 is connected to the emitter and base of transistor Q1. The circuit includes the following functions:
[0009] F1: Functions include circuit conduction and protection under normal conditions, and the effect of input voltage Vin on the circuit; the circuit conduction and protection under normal conditions are as follows: under normal conditions, resistor R2 is connected between the gate (G) of PMOSFET X1 and ground, forming a stable voltage divider circuit. Due to the characteristics of X1, when the gate-source voltage VGS is less than 0, X1 is in the conducting state. Therefore, R2 ensures that VGS remains negative during normal operation. D2 is a Zener diode with a Zener voltage between 15 and 16V. When the gate-source voltage of X1 exceeds the Zener voltage of D2, D2 quickly conducts, clamping the voltage at the Zener value.
[0010] F2: The effect of the input voltage Vin on the circuit includes low input voltage Vin and high input voltage Vin. The low input voltage Vin occurs when the input voltage Vin is less than the reverse conduction voltage of the Zener diode D4. In this case, D4 is in the reverse cutoff state, and no current flows through D4. Therefore, no current flows into the base of the transistor Q1, causing Q1 to also be in the cutoff state. This also causes the transistor Q2 to be in the cutoff state. At this time, the drain and source terminals of X1 remain in the conducting state. The resistors R1 and R3 and the Zener diodes D1 and D3 are respectively connected to Q1.
[0011] F3: The high input voltage Vin condition occurs when the input voltage Vin is greater than the reverse conduction voltage of D4. In this case, the Zener diode D4 begins reverse conduction, generating a voltage Vd7 equal to the reverse conduction voltage of D4. After D4 conducts, it provides sufficient current to the base of transistor Q1, causing Q1 to enter an amplification state. This, in turn, controls transistor Q2 to enter a conducting state. The conducting state of Q2 adjusts the output voltage Vout, using Vd7 as the clamping voltage for Vout. To meet the Class A functional requirements of the pulse5b experiment, D4 is replaced to reduce the output voltage Vout, preventing damage to the ECU module due to overvoltage.
[0012] Preferably, in function F1, the resistor R2 is connected between the gate (G) of X1 and ground, and the diode D2 is a Zener diode with a voltage regulation value between 15 and 16V. D2 is connected in parallel between the gate (G) and source (S) of X1.
[0013] Preferably, by changing the resistance value of the resistor R2, the voltage at the gate (G) of X1 is adjusted, thereby changing the magnitude of the gate-source voltage VGS, making VGS less than 0, and thus controlling the conduction state of X1.
[0014] Preferably, in function F2, when transistors Q1 and Q2 are in the off state and the gate voltage of X1 is controlled by the voltage divider of resistor R2, the DS stage of X1 remains in the on state when the gate-source voltage VGS of X1 is less than 0.
[0015] Preferably, in function F2, the resistor R3 is connected to the base of the transistor Q1, the resistor R1 is connected to the base of the transistor Q2, the Zener diode D1 is connected to the base and emitter of Q2, and the Zener diode D3 is connected to the base and emitter of Q1.
[0016] Preferably, in function F3, the Zener diode D4 conducts to provide sufficient current to the transistor Q1, and Q1 enters the amplification state. After the current at the collector of Q1 is amplified, it affects the base voltage of the transistor Q2, thereby controlling the conduction state of Q2.
[0017] Preferably, in function F3, the conduction state of the transistor Q2 affects the voltage drop VCE between the collector and emitter, and the collector of Q2 is indirectly connected to the output voltage Vout. Therefore, the change in VCE of Q2 will affect the output voltage Vout.
[0018] Preferably, in function F3, when the input voltage Vin exceeds the reverse conduction voltage of the Zener diode D4, D4 will enter the reverse breakdown state, and the current inside D4 will increase sharply. However, the reverse conduction voltage across the Zener diode remains unchanged, and when D4 is reverse conducting, a clamping voltage of magnitude Vd7 will be generated.
[0019] Compared with existing technologies, the beneficial effects of this invention are as follows: A Zener diode D4 is introduced into the circuit, and its reverse conduction voltage is used as the reference for the clamping voltage. By replacing the Zener diode D4, the clamping voltage can be adjusted. In the pulse-5b experiment, when the generator disconnects and load is dumped, the input voltage Vin rises rapidly. At this time, the clamping effect of the Zener diode D4 ensures that the output voltage Vout does not rise abnormally, thus meeting the Class A functional requirements of the experiment. Under normal conditions, the circuit is connected between the gate (G) of PMOSFET X1 and ground through resistor R2, forming a stable voltage divider circuit to ensure that X1 remains in the conducting state when the gate-source voltage VGS is less than 0. This design reduces unnecessary power consumption and operating current. Attached Figure Description
[0020] Figure 1 This is a circuit diagram of the adjustable voltage clamping circuit of Embodiment 1 of this utility model;
[0021] Figure 2 This is a schematic diagram of the current and power consumption of the adjustable voltage clamping circuit in Embodiment 1 of this utility model; Detailed Implementation
[0022] The adjustable voltage clamping circuit of this utility model will be described in detail below with reference to the accompanying drawings.
[0023] The core working principle of the adjustable voltage clamping circuit of this utility model is to set the clamping voltage reference through the Zener diode D4 and use the feedback control loop composed of transistors Q1 and Q2 to drive the PMOSFET transistor X1, thereby providing power protection for the vehicle ECU, so that it can meet the normal driving requirements and pass the ISO 7637-2Pulse 5b load dump test.
[0024] like Figure 1 The adjustable voltage clamping circuit shown includes a PMOSFET X1, Zener diodes D1, D3, D4, resistors R2, R3, R1, and transistors Q1 and Q2. PMOSFET X1 controls the output voltage. Zener diode D2 is connected between the gate (G) and source (S) terminals of X1 and is connected to ground via R2. Transistor Q2 is connected between the gate (G) and source (S) terminals of X1. The base of transistor Q2 is connected to the collector of transistor Q1 via resistor R1. Zener diode D1 is connected to the emitter and base of transistor Q1. The base of transistor Q1 is connected to the drain (D) terminal of X1 via resistor R3. The emitter of transistor Q1 is connected to Zener diode D4, the other end of which is connected between R2 and ground. Zener diode D3 is connected to the emitter and base of transistor Q1. Functions include circuit conduction and protection under normal conditions, and the effect of input voltage Vin on the circuit.
[0025] F1: Circuit conduction and protection under normal conditions: Under normal conditions, resistor R2 is connected between the gate (G) of PMOSFET X1 and ground, forming a stable voltage divider circuit. Due to the characteristics of X1, when the gate-source voltage VGS is less than 0, X1 is in the conducting state. Therefore, R2 ensures that VGS remains negative during normal operation. D2 is a Zener diode with a Zener voltage between 15 and 16V. When the gate-source voltage exceeds the Zener voltage of D2, D2 quickly conducts, clamping the voltage at the Zener value, thereby protecting X1.
[0026] Preferably, in function F1, resistor R2 is connected between the gate (G) of X1 and ground, forming a stable voltage divider network. D2 is a Zener diode with a Zener voltage between 15 and 16V. D2 is connected in parallel between the gate (G) and source (S) of X1 to prevent the voltage between the gate and source terminals from rising abnormally due to external interference or circuit faults, which could potentially damage X1. Once the voltage between the gate and source terminals attempts to exceed the Zener voltage of D2, D2 will quickly conduct, clamping the voltage to its Zener value and protecting X1 from damage.
[0027] Preferably, by changing the resistance value of resistor R2, the voltage at the gate (G) is adjusted, thereby changing the magnitude of the gate-source voltage VGS, making VGS voltage less than 0, and thus controlling the conduction state of X1. R2 ensures that VGS remains negative during normal operation, thereby enabling X1 to stably conduct current.
[0028] The effect of the input voltage Vin on the circuit includes the case of low input voltage Vin and the case of high input voltage Vin.
[0029] F2: The low input voltage Vin condition is when the input voltage Vin is less than the reverse conduction voltage of the Zener diode D4. D4 is in the reverse cutoff state, and no current flows through the diode D4. Therefore, no current flows into the base of the transistor Q1, causing Q1 to also be in the cutoff state. This also causes Q2 to be in the cutoff state. At this time, the drain and source terminals of X1 remain in the conducting state. Resistors R1 and R3 and Zener diodes D1 and D3 are connected to Q1 respectively.
[0030] Preferably, in function F2, transistors Q1 and Q2 are in the off state because there is not enough current flowing through their bases, and when the gate-source voltage VGS of X1 is less than 0, the DS stage of X1 remains in the on state, while Q1 and Q2 are all in the off state, thus keeping the DS stage of X1 in the on state unchanged.
[0031] Preferably, in function F2, resistor R3 is connected to the base of transistor Q1, resistor R1 is connected to the base of transistor Q2, Zener diode D1 is connected to the base and emitter of Q2, and Zener diode D3 is connected to the base and emitter of Q1. R3 and R1 act as current-limiting resistors to limit the current at the base of transistors Q1 and Q2, preventing excessive current from damaging Q1 and Q2. D1 and D3 act as protective Zener diodes to prevent reverse breakdown between the emitter and base of Q1 and Q2.
[0032] F3: The high input voltage Vin condition occurs when the input voltage Vin is greater than the reverse conduction voltage of D4. D4 then begins to conduct in reverse, generating a voltage Vd7. The magnitude of Vd7 is equal to the reverse conduction voltage of D4. After D4 conducts, it provides sufficient current to the base of Q1, causing Q1 to enter the amplification state. This, in turn, controls Q2 to enter the conduction state. The conduction state of Q2 can adjust the output voltage Vout, using Vd7 as the clamping voltage for the output voltage Vout. To meet the Class A functional requirements of the pulse5b experiment, D4 is replaced to reduce the output voltage Vout, preventing the ECU module from being damaged by overvoltage.
[0033] Preferably, in function F3, the Zener diode D4 conducts to provide sufficient current to the transistor Q1, and Q1 enters the amplification state. After the current at the collector of Q1 is amplified, it affects the base voltage of the transistor Q2, thereby controlling the conduction state of Q2. When the input voltage Vin is high, the reverse conduction of D4 can provide current to Q1, causing it to enter the amplification state, and driving Q2 to enter the conduction state.
[0034] Preferably, in function F3, the conduction state of the transistor Q2 affects the voltage drop VCE between the collector and emitter, and the collector of Q2 is indirectly connected to the output voltage Vout. Therefore, the change in VCE of Q2 will affect the output voltage Vout.
[0035] Preferably, in function F3, when the input voltage Vin exceeds the reverse conduction voltage of the Zener diode D4, D4 will enter a reverse breakdown state, and the current inside D4 will increase sharply. However, the reverse conduction voltage across the Zener diode remains unchanged. Furthermore, when D4 is reverse conducting, a clamping voltage of magnitude Vd7 will be generated. Therefore, replacing D4 can adjust the clamping voltage, thereby adjusting the output voltage Vout. The clamping voltage level of the output voltage Vout can be flexibly adjusted so that the circuit can meet the Class A functional requirements of the pulse5b experiment.
[0036] Under normal conditions, resistor R2 is connected between the gate (G) of PMOSFET X1 and ground, forming a stable voltage divider circuit. Due to the characteristics of X1, when the gate-source voltage VGS is less than 0, X1 is in the conducting state. D2 is connected in parallel between the gate (G) and source (S) of X1. Once the gate-source voltage attempts to exceed the regulated voltage of D2, D2 will quickly turn on, clamping the voltage to its regulated value and protecting X1 from damage.
[0037] When the input voltage Vin is lower than the reverse conduction voltage of Zener diode D4, D4 is in reverse cutoff state and no current flows through diode D4. Therefore, no current flows into the base of transistor Q1, causing Q1 to also be in cutoff state. This also causes Q2 to be in cutoff state. When the gate voltage of X1 is controlled by the voltage divider of resistor R2, when the gate-source voltage VGS of X1 is less than 0, the drain-source stage of X1 remains in conduction state, and Q1 and Q2 are all in cutoff state, thus keeping the drain-source stage of X1 in conduction state unchanged.
[0038] When the input voltage Vin is higher than the reverse conduction voltage of Zener diode D4, D4 begins to conduct in reverse, generating a voltage Vd7, the magnitude of which is equal to the reverse conduction voltage of Zener diode D4. After Zener diode D4 conducts, it provides sufficient current to the base of Q1, and Q1 enters the amplification state, thereby controlling Q2 to enter the conduction state. The conduction state of Q2 can adjust the output voltage Vout, using Vd7 as the clamping voltage of the output voltage Vout.
[0039] Since the input voltage Vin exceeds the reverse conduction voltage of the Zener diode D4, the current inside D4 will increase sharply. The reverse conduction voltage across D4 remains unchanged, and when D4 is reverse-conducting, a clamping voltage of magnitude Vd7 will be generated. Vd7 is directly determined by the Zener voltage value of D4. Therefore, by replacing D4 with different Zener voltage values, the clamping voltage point can be changed to meet the Class A functional requirements of the pulse5b experiment.
[0040] In this embodiment, the input of the "adjustable voltage clamping circuit" is connected to the battery power input. When the generator disconnects and a load is dumped (i.e., during the Pulse-5b experiment), the input voltage Vin rises rapidly to 87V. Once the output voltage Vout rises to the reverse conduction voltage of the Zener diode D4, D4 will conduct. At this time, Q1 enters the amplification state, and Q1 controls Q2 to drive the MOSFET X1 to also enter the amplification state, thereby controlling the output voltage Vout and clamping it around Vd7.
[0041] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of this application. Those skilled in the art may find other optimizations and additional functions in this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. An adjustable voltage clamp circuit, characterized by: The circuit comprises PMOSFET X1, voltage stabilizing tube D1, D3, D3, D4, resistors R2, R3, R1 and transistors Q1, Q2; wherein PMOSFET X1 is used to control output voltage, the voltage stabilizing tube D2 is connected between the G stage and the S stage of X1 and connected to the ground through R2; the transistor Q2 is connected between the G stage and the S stage of X1, the base of the transistor Q2 is connected with the collector of the transistor Q1 through the resistor R1, wherein the voltage stabilizing tube D1 is connected with the emitter and the base of the transistor Q1; the base of the transistor Q1 is connected with the D stage of X1 through the resistor R3, the emitter of the transistor Q1 is connected with the voltage stabilizing tube D4, the other end of the voltage stabilizing tube D4 is connected between the resistor R2 and the ground, the voltage stabilizing tube D3 is connected with the emitter and the base of the transistor Q1; The circuit comprises the following functions: F1: the functions include circuit conduction and protection in normal state, and the influence of input voltage Vin on the circuit; the circuit conduction and protection in normal state is that the resistor R2 is connected between the G stage and the ground of the PMOSFET X1 to form a stable voltage dividing circuit, due to the characteristics of the X1, when the gate-source voltage VGS is less than 0, the X1 is in the conduction state, therefore the R2 ensures that the VGS keeps negative value in normal work, the D2 is a voltage stabilizing tube with a stable voltage value between 15-16V, when the GS voltage of the X1 exceeds the stable voltage value of the D2, the D2 rapidly conducts to clamp the voltage on the stable voltage value; F2: the influence of the input voltage Vin on the circuit includes low input voltage Vin condition and high input voltage Vin condition; the low input voltage Vin condition is that when the input voltage Vin is less than the reverse conduction voltage of the voltage stabilizing tube D4, the D4 is in the reverse cut-off state, no current passes through the D4, therefore no current flows into the base of the transistor Q1, which leads to that the Q1 is also in the cut-off state, which also leads to that the transistor Q2 is also in the cut-off state, at this time, the DS (drain and source) of the X1 keeps the conduction state, the resistors R1, R3 and the voltage stabilizing tubes D1, D3 are connected with the Q1 respectively; F3: the high input voltage Vin condition is that when the input voltage Vin is greater than the reverse conduction voltage of the D4, the voltage stabilizing tube D4 starts to conduct reversely, a voltage Vd7 is generated, the size of the Vd7 is equal to the reverse conduction voltage of the D4, after the D4 conducts, enough current is provided for the base of the transistor Q1, the Q1 enters the amplification state, thereby controlling the transistor Q2 to enter the conduction state, the conduction state of the Q2 can adjust the output voltage Vout, taking the Vd7 as the clamping voltage of the output voltage Vout, in order to meet the A class functional requirements of pulse5b experiment, the D4 is replaced to reduce the output voltage Vout.
2. The adjustable voltage clamp circuit of claim 1, wherein: In function F1, the resistor R2 is connected between the voltage stabilizer D2 and the ground, and the voltage stabilizer D2 is a voltage stabilizer with a stable voltage between 15V and 16V.
3. The adjustable voltage clamp circuit of claim 2, wherein: By changing the resistance of the resistor R2, the voltage of the G terminal of X1 is adjusted, thereby changing the size of the gate-source voltage VGS, making the VGS voltage less than 0, and then controlling the conduction state of X1.
4. The adjustable voltage clamp circuit of claim 1, wherein: In function F2, the triode Q1 and the triode Q2 are in the off state, and when the gate-source voltage VGS of X1 is less than 0, the DS terminal of X1 remains in the conduction state under the condition that the voltage of the G terminal of X1 is controlled by the voltage division of the resistor R2.
5. The adjustable voltage clamp circuit of claim 1, wherein: In function F2, the resistor R3 is connected to the base of the triode Q1, the resistor R1 is connected to the base of the triode Q2, the voltage stabilizer D1 is connected to the base and emitter of Q2, and the voltage stabilizer D3 is connected to the base and emitter of Q1.
6. The adjustable voltage clamp circuit of claim 1, wherein: In function F3, the voltage stabilizer D4 provides sufficient current for the triode Q1, and the Q1 enters the amplification state. The current amplified by the collector of the Q1 affects the base voltage of the triode Q2, thereby controlling the conduction state of the Q2.
7. The adjustable voltage clamp circuit of claim 6, wherein: In function F3, the conduction state of the triode Q2 affects the voltage drop VCE between the collector and the emitter, and the collector of the Q2 is indirectly connected to the output voltage Vout, so the change of VCE of the Q2 will affect the output voltage Vout.
8. The adjustable voltage clamp circuit of claim 1, wherein: In function F3, when the input voltage Vin exceeds the reverse conduction voltage of the voltage stabilizer D4, D4 will enter the reverse breakdown state, and the current inside D4 will increase sharply, but the reverse conduction voltage between the two ends of the voltage stabilizer remains unchanged. When D4 is in the reverse conduction state, a clamping voltage with a size of Vd7 is generated.