Multi-bus architecture distributed IO system
By combining a multi-bus architecture with SPI and RS485 buses, the distributed I/O system achieves high real-time performance and stability, solving the communication bottleneck and insufficiency problems in existing technologies, and improving the system's reliability and flexibility.
Patent Information
- Application Number
- CN202520504884.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2035-03-21
AI Technical Summary
The existing CAN and RS485 single-bus architecture cannot meet the high real-time requirements of industrial applications in distributed I/O systems, and its stability is insufficient, resulting in communication bottlenecks and failure risks.
Adopting a multi-bus architecture, combining SPI and RS485 buses, a master-slave architecture is designed. Utilizing the SPI and RS485 interfaces of the ARM processor, high-speed data interaction and management are achieved. Through four independent SPI data communication buses and RS485 management buses, asynchronous communication of 127 nodes is supported, enabling automatic board identification and automatic node address allocation.
It improves the real-time performance and stability of the system, simplifies the application layer design, reduces the risk of human configuration errors, enhances the system's cost-effectiveness and reliability, and meets the testing requirements of harsh environments such as high temperature and EMC.
Smart Images
Figure CN223926898U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the embedded technology in the floor application technology field of distributed IO system, more specifically relates to a kind of multi-bus architecture distributed IO system. BACKGROUND
[0002] With the continuous application of domestic PLC in industrial field, the application of distributed IO system is more and more widely. The PLC technology applied in some fields is mainly SIEMENS and BECKHOFF, which expands the distributed IO system through coupling form. There are various implementation ways for the most core data communication bus of distributed IO system. Among them, CAN and RS485 single bus architecture are mostly used. However, there is a certain bottleneck in the rate of CAN bus and RS485 bus, which cannot meet the needs of application scenarios with high real-time requirements. At the same time, in the field of high real-time industrial applications, the stability of single bus also faces more severe challenges. Therefore, there is an urgent market demand for distributed IO communication technology that meets the requirements of real-time, stability and reliability. Multi-bus architecture distributed IO system architecture meets the special requirements of industrial applications from the aspects of communication rate, system stability and reliability. SUMMARY
[0003] The utility model overcomes the insufficient in the prior art, and provides a kind of multi-bus architecture distributed IO system.
[0004] The purpose of the utility model is achieved by the following technical scheme.
[0005] A kind of multi-bus architecture distributed IO system, coupler control board is connected with control board and each interface board by management control bus, control board is connected with each interface board by communication data bus, each interface board is coupled and connected to control board by communication terminal and preceding interface board.
[0006] Coupler control board, control board and each interface board are all equipped with 2 hardware IO interfaces, and coupler control board, control board and each interface board are sequentially connected by hardware IO interface.
[0007] Management control bus includes connecting line RS485A and connecting line RS485B, and RS485 terminal matching resistance is fixedly arranged at the position of both ends of management control bus.
[0008] The management control bus comprises four independent SPI data communication buses: an SPI1 data communication bus, an SPI2 data communication bus, an SPI3 data communication bus and an SPI4 data communication bus, and is connected with the first interface board, the second interface board, the third interface board and the fourth interface board of the interface board through the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus respectively.
[0009] The structure of each interface board is the same, the communication terminals of the interface board comprise a first communication terminal, a second communication terminal, a third communication terminal, a fourth communication terminal, a communication terminal A, a communication terminal B, a communication terminal C and a communication terminal D, the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the interface board are connected with the communication terminal A, the communication terminal B, the communication terminal C and the communication terminal D of the previous interface board through a communication data bus, and the second communication terminal, the third communication terminal and the fourth communication terminal of the same interface board are connected with the communication terminal A, the communication terminal B and the communication terminal C respectively.
[0010] The communication terminals arranged on the control board are connected with the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the first interface board through the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus respectively.
[0011] The communication data bus adopts a four-wire SPI.
[0012] The utility model discloses a kind of interface board and control board, the utility model discloses a kind of communication bus and management bus, the utility model discloses a kind of communication terminal and communication terminal, the utility model discloses a kind of communication data bus, the utility model discloses a kind of interface board, the utility model discloses a kind of control board, the utility model discloses a kind of communication bus, the utility model discloses a kind of management bus.
[0013] Communication bus and management bus are designed and realized using master-slave architecture, which can simplify the design difficulty and complexity of application layer to the greatest extent. RCBUS synchronous communication based on SPI interface realizes real-time data interaction function; RMBUS asynchronous communication based on 485 realizes interface function configuration and management function. At the same time, data resources are shared in the coupler control board for synchronous communication and asynchronous communication, to realize the stability and reliability of the communication bus. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 is the overall framework of the utility model;
[0015] Figure 2 is a data communication bus architecture block diagram;
[0016] Figure 3 is an RCBUS data line connection block diagram;
[0017] Figure 4 is an RMBUS node address implementation block diagram;
[0018] In the figure: 1, coupler control board, 2, control board; 3, first interface board; 4, second interface board; 5, third interface board; 6, fourth interface board; 7, terminal matching resistance; 8, management control bus; 9, communication data bus. DETAILED DESCRIPTION
[0019] The technical scheme of the utility model will be further explained below through specific embodiments.
[0020] EMBODIMENT
[0021] A multi-bus architecture distributed IO system, the coupler control board 1 is connected with the control board 2 and each interface board through the management control bus 8, the control board 2 is connected with each interface board through the communication data bus 9, and each interface board is coupled and connected to the control board 2 through the communication terminal and the preceding interface board.
[0022] The coupler control board 1, the control board 2 and each interface board are all provided with two hardware IO interfaces, and the coupler control board 1, the control board 2 and each interface board are sequentially connected through the hardware IO interfaces.
[0023] The management control bus 8 includes the connection line RS485A and the connection line RS485B, and the RS485 terminal matching resistance 7 is fixedly arranged at the positions of both ends of the management control bus 8.
[0024] The management control bus 8 includes four independent SPI data communication buses: SPI1 data communication bus, SPI2 data communication bus, SPI3 data communication bus and SPI4 data communication bus, and the first interface board 3, the second interface board 4, the third interface board 3 and the fourth interface board 6 of the interface board are connected through the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus respectively.
[0025] The structure of each interface board is same, the communication terminals of the interface board include first communication terminal, second communication terminal, third communication terminal, fourth communication terminal, communication terminal A, communication terminal B, communication terminal C and communication terminal D, the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the interface board are connected with the communication terminal A, the communication terminal B, the communication terminal C and the communication terminal D of the previous interface board through the communication data bus 9, and the second communication terminal, the third communication terminal and the fourth communication terminal of the same interface board are connected with the communication terminal A, the communication terminal B and the communication terminal C respectively.
[0026] The communication terminals arranged on the control board 2 are connected with the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the first interface board 3 through the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus respectively.
[0027] The communication data bus 9 adopts 4-wire SPI.
[0028] The working principle of the utility model is as follows, in the embodiment, the communication data bus 9 is realized by standard 4-wire SPI (SPI_NSS, SPI_SCK, SPI_MOSI, SPI_MISO). In the implementation process, according to the SPI interface quantity of the processor, 4-way independent SPI data communication bus is adopted in the embodiment, and the communication protocol uses UXP universal transport layer protocol (Universial Transport Layer Protocol).
[0029] The control board 2 is connected with each interface board through independent SPI, wherein the first interface board 3 is connected with the control board 2 through the SPI1 data communication bus, the second interface board 4 is connected with the control board through the SPI2 data communication bus, the third interface board 5 is connected with the control board 2 through the SPI3 data communication bus, and the fourth interface board 6 is connected with the control board through the SPI4 data communication bus; the interface board is coupled and connected to the control board 2 through the communication terminal and the previous interface board, so that the fixed SPI interface of the interface board is realized and cascaded.
[0030] As shown in Figure 2 The SPI connection communication port of the second interface board 4 is the first communication terminal, that is, the interface board block 1 in the figure, after the first communication terminal of the second interface board 4 is connected to the communication terminal A of the first interface board 3, it is connected to the second communication terminal through the internal connection of the first interface board 3, and then communicates with the 2nd SPI port of the control board 2, and the rest of the interface board SPI channel connection mode is sequentially connected to the corresponding port according to the above connection method, and the specific structure is shown in the figure.
[0031] Among them, asFigure 3 As shown, each group of communication data bus 9 consists of chip select, clock and data lines, in line with the standard 4 SPI communication protocol requirements. At the same time, the chip select enables the data line, which can further increase the flexibility of the system, and is convenient for expansion applications. The control board 2 can also communicate with the interface board in real time through synchronous communication, master the data and working status of the interface board, and is convenient for maintenance and management.
[0032] Further, as shown, Figure 4 The management control bus 8, namely RMBUS management bus, adopts RS485, and the bus node supports 127, meeting the needs of most application scenarios. The management control bus 8 includes two connection lines, namely RS485A and RS485B, namely the A line and the B line in the figure. The coupler control board 1 realizes asynchronous communication of the management bus 8 with the interface board through RS485 to manage data of each board card, and at the same time can provide technical support for data backup and data monitoring as the communication data bus 9, increasing the stability of the system.
[0033] Among them, the RS485 terminal matching resistor 7 is fixedly arranged at both ends of the management control bus 8, which is realized on the backplane bus of the system, which can reduce the terminal resistance and the code dialing configuration of the intermediate control board and the interface board, which can not only reduce the risk of communication failure caused by improper configuration of the operator, but also save materials and reduce the material cost of the system, and improve the performance-price ratio of the product.
[0034] Preferably, the management control bus 8 belongs to the communication within the system, and the distance is generally short, which can reduce the use of isolation devices, improve the bus communication rate, and further improve the comprehensive performance of the product. The actual measurement of the management bus data rate is 10 Mbps, which meets the harsh test environment of high and low temperature and EMC.
[0035] Further, in the actual application of the communication data bus 9 and the management control bus 8, the realization of the automatic adaptation of the node address is the technical guarantee of the flexibility of the whole system. The automatic node adaptation mainly reflects in two aspects of automatic identification of the board card and automatic cascading of the board card.
[0036] The automatic identification of the data communication bus board card is realized by hardware cooperating with software. Each group of communication data bus 9, namely RCBUS, is connected through an independent SPI data bus, and the control board 2 can communicate with the interface board through SPI. Since there are many types of interface boards (such as DI, DO, AI, etc.), the control board 2 and the interface board need to adapt different parameter data according to the type of the interface board to ensure the accuracy of the communication. After the RCBUS communication is established, according to the content of the communication data message, such as the type of the interface board and the data length of the interface board, the control board 2 adapts different parameter data to the interface board, and at the same time, the interface board software identifies through the hardware ID interface (code dialing switch) in the system power-on initialization stage. At the same time, different numbers of ID addresses can be designed according to the complexity of the system and the type of the interface board.
[0037] The automatic cascade implementation of data communication is realized by reserving additional RCBUS connecting lines in the interface board, and four groups of SPI connecting lines are reserved in the communication terminal of the interface board, and the first group of SPI is actually used for communication connection, the reserved RCBUS connecting lines are short-circuited through the second communication terminal and the communication terminal A, the third communication terminal and the communication terminal B, and the fourth communication terminal and the communication terminal C, so that the automatic cascade communication of the SPI communication data lines of the subsequent interface boards is realized.
[0038] As shown in Figure 4 The communication data bus 9 is designed by means of RS485 bus, and only the automatic identification of node address is involved, and the automatic cascade problem is not involved. The automatic identification of node address is realized by software and hardware matching. Two hardware IO interfaces are designed in the control board 2 and the interface board, one of which is used for level input and one of which is used for level output. The RMBUS management bus transmits data and commands through RS485, and the hardware IO assists in allocating node ID address for each board card, so that each node on the bus has a unique node ID.
[0039] The coupler control board 1 has a default node ID of 1, and the remaining board cards are all 0XFF by default. After the system is powered on and works, the coupler control board 1 controls the IO output to be high level, and the control board 2 or the interface board acquires the IO input pin level state through interruption or polling. When the high level is detected, the control board 2 or the interface board communicates with the coupler control board 1, receives the node ID:1 allocated by the coupler control board 1, and then uses the node ID 1 to communicate with the coupler control board 1, and at the same time, the IO output is set to high level. The coupler control board 1 communicates with the second control board 2 or the interface board again, and allocates ID:2 for the second control board 2 or the interface board. In this way, the node ID of the last board card is allocated, and at the same time, the Timeout time is set to judge whether there is no node to be allocated with ID address, so that the allocation of all node IDs of the system is completed. The automatic recognition and node address automatic allocation process is realized. When the system is powered off or an abnormality occurs, the node re-allocates the node ID according to the above-mentioned logic to realize the automatic recognition process, and manual configuration or manual dialing is not needed, so that the uncertainty caused by manual operation is avoided, and the safety and stability of the system are improved.
[0040] The embodiments of the utility model are described in detail above, but the content described can only be the preferred embodiments of the utility model, and cannot be considered as limiting the implementation range of the utility model. Any equivalent change and improvement made within the application range of the utility model should still belong to the patent coverage range of the utility model.
Claims
1. A multi-bus architecture distributed IO system, characterized by: The coupler control board is connected with the control board and the interface boards through the management control bus, the control board is connected with the interface boards through the communication data bus, and the interface boards are coupled to the control board through the communication terminals of the preceding interface boards.
2. The multi-bus architecture distributed IO system according to claim 1, characterized in that: Two hardware IO interfaces are arranged on the coupler control board, the control board and the interface boards, and the coupler control board, the control board and the interface boards are connected in sequence through the hardware IO interfaces.
3. The multi-bus architecture distributed IO system according to claim 1, wherein: The management control bus comprises a connection line RS485A and a connection line RS485B, and RS485 terminal matching resistors are fixedly arranged at positions on both ends of the management control bus.
4. The multi-bus architecture distributed IO system according to claim 1, wherein: The management control bus comprises four independent SPI data communication buses, namely, an SPI1 data communication bus, an SPI2 data communication bus, an SPI3 data communication bus and an SPI4 data communication bus, and the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus are connected with the first interface board, the second interface board, the third interface board and the fourth interface board of the interface boards respectively.
5. The multi-bus architecture distributed IO system according to claim 4, wherein: The structures of the interface boards are the same, the communication terminals of the interface boards comprise a first communication terminal, a second communication terminal, a third communication terminal, a fourth communication terminal, a communication terminal A, a communication terminal B, a communication terminal C and a communication terminal D, the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the interface board are connected with the communication terminal A, the communication terminal B, the communication terminal C and the communication terminal D of the preceding interface board through the communication data bus, and the second communication terminal, the third communication terminal and the fourth communication terminal of the same interface board are connected with the communication terminal A, the communication terminal B and the communication terminal C respectively.
6. The multi-bus architecture distributed IO system according to claim 5, wherein: The communication terminals arranged on the control board are connected with the first communication terminal, the second communication terminal, the third communication terminal and the fourth communication terminal of the first interface board through the SPI1 data communication bus, the SPI2 data communication bus, the SPI3 data communication bus and the SPI4 data communication bus respectively.
7. The multi-bus architecture distributed IO system according to claim 1, wherein: The communication data bus adopts a 4-wire SPI.