Pixel

Abstract

The utility model relates to a pixel. In various embodiments, a pixel is provided. The pixel may include a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, where the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a transfer region of the substrate; and a first planar gate and a second planar gate disposed on the substrate, where the first planar gate and the second planar gate are configured to direct the one or more charge carriers from the transfer region to the first sensing node or the second sensing node.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate generally to light detection, and more specifically to light detection pixels. BACKGROUND

[0002] Light detection pixels are used in a variety of technologies, such as in three-dimensional (3D) and two-dimensional (2D) imaging systems. New developments in technologies that use light detection pixels require the pixels to have improved performance. The Applicant has recognized a number of technical challenges and difficulties associated with light detection pixels. Through the efforts, ingenuity, and innovation applied, the Applicant has solved problems associated with light detection pixels by developing solutions implemented in the present disclosure, which will be described in detail below. SUMMARY

[0003] Various embodiments described herein relate to systems, devices, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes a substrate configured to generate one or more carriers in response to an incident light beam, a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a transfer region of the substrate, and a first planar gate and a second planar gate disposed on the substrate, wherein the first planar gate and the second planar gate are configured to direct the one or more carriers from the transfer region to a first sensing node or a second sensing node.

[0004] In various embodiments, the pixel includes a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first vertical gate control signal, a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second vertical gate control signal, a first planar gate input electrically coupled to the first planar gate and configured to receive a first planar gate control signal, and a second planar gate input electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first planar vertical gate and the second planar vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

[0005] In various embodiments, the first vertical gate and the second vertical gate are configured to be activated using the first vertical gate control signal and the second vertical gate control signal, and, when activated, direct the one or more carriers to the transfer region; the first planar gate is configured to be activated using the first planar gate control signal, and, when activated, direct the one or more carriers to the first sense node; and the second planar gate is configured to be activated using the second planar gate control signal, and, when activated, direct the one or more carriers to the second sense node.

[0006] In various embodiments, the first vertical gate and the second vertical gate are configured to be activated concurrently; the first planar gate is configured to be activated when the second planar gate is deactivated; and the second planar gate is configured to be activated when the first planar gate is deactivated. In various embodiments, the first vertical gate control signal and the second vertical gate control signal are DC voltages, and the first planar gate control signal and the second planar gate control signal comprise periodic waveforms and are complementary to each other.

[0007] In various embodiments, the pixel includes: a third vertical gate disposed inside the substrate; a fourth vertical gate disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the transfer region; a third vertical gate input electrically coupled to the third vertical gate and configured to receive a DC third gate control signal; a fourth vertical gate input electrically coupled to the fourth vertical gate and configured to receive a DC fourth vertical gate control signal; a third planar gate disposed on the substrate and configured to direct the one or more carriers to a third sense node when the third planar gate is activated; a fourth planar gate disposed on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sense node when the fourth planar gate is activated; a third planar gate input electrically coupled to the third planar gate and configured to receive a third planar gate control signal; and a fourth planar gate input electrically coupled to the fourth planar gate and configured to receive a fourth planar gate control signal, wherein the first planar gate control signal, the second planar gate control signal, the third planar gate control signal, and the fourth planar gate control signal comprise periodic waveforms and are spaced apart from each other by a 90º phase shift.

[0008] In various embodiments, the pixel includes: a first deep isolation trench on a first side of the substrate; and a second deep isolation trench on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

[0009] In various embodiments, the first planar gate and the second planar gate are configured to be activated alternately using a first planar gate control signal and a second planar gate control signal, wherein at a given time, the first planar gate control signal is the complement of the second planar gate control signal; the first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal; and the pixel is configured to determine the indirect time of flight (iToF).

[0010] In various embodiments, the first vertical gate and the second vertical gate are configured to be deactivated simultaneously, and the first planar gate and the second planar gate are configured to be deactivated simultaneously for a first time period; the first vertical gate and the second vertical gate are configured to be activated, and the first planar gate or the second planar gate is configured to be activated for a second time period; and the pixel is configured to provide two-dimensional imaging.

[0011] In various embodiments, a pixel is provided. The pixel may include: a substrate configured to generate one or more charge carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed within the substrate, wherein the first and second vertical gates are configured to guide the one or more charge carriers toward the first and second vertical gates; a first planar gate input electrically coupled to the first planar gate and configured to receive a first planar gate control signal; and a second planar gate input electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first and second planar gates are configured to guide the one or more charge carriers to a first capacitor or a second capacitor using the first and second gate control signals.

[0012] In various embodiments, a first planar gate is configured to be activated using a first gate control signal and, when activated, directs one or more charge carriers to a first capacitor; and a second planar gate is configured to be activated using a second planar gate control signal and, when activated, directs one or more charge carriers to a second capacitor, wherein the first planar gate and the second planar gate, as well as the first vertical gate and the second vertical gate, are deployed near the same surface of the substrate.

[0013] In various embodiments, when the second planar gate is activated, the first planar gate is deactivated; when the first planar gate is activated, the second planar gate is deactivated; and the first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

[0014] Various embodiments of this disclosure provide a method. The method may include: deploying a first vertical gate and a second vertical gate within a substrate, wherein the first and second vertical gates are configured to direct one or more charge carriers to a transfer region of the substrate, wherein the one or more charge carriers are generated within the substrate in response to an incident light beam; and deploying a first planar gate and a second planar gate on the substrate, wherein the first and second planar gates are configured to direct the one or more charge carriers from the transfer region to a first sensing node or a second sensing node.

[0015] The method may include: configuring a first vertical gate input to receive a first vertical gate control signal, wherein the first vertical gate input is electrically coupled to a first vertical gate; configuring a second vertical gate input to receive a second vertical gate control signal, wherein the second vertical gate input is electrically coupled to a second vertical gate; configuring a first planar gate input to receive a first planar gate control signal, wherein the first planar gate input is electrically coupled to a first planar gate; configuring a second planar gate input to receive a second planar gate control signal, wherein the second planar gate input is electrically coupled to a second planar gate, wherein the first planar gate and the second planar gate are configured to use the first planar gate control signal and the second planar gate control signal to guide the one or more carriers to a first sensing node or a second sensing node.

[0016] In various embodiments, the method includes: configuring a first vertical gate and a second vertical gate to be activated using a first vertical gate control signal and a second vertical gate control signal, wherein when the first vertical gate and the second vertical gate are activated, the first vertical gate and the second vertical gate direct the one or more carriers to a transfer region; configuring a first planar gate to be activated using a first planar gate control signal, and directing the one or more carriers to a first sensing node when the first planar gate is activated; and configuring a second planar gate to be activated using a second planar gate control signal, and directing the one or more carriers to a second sensing node when the second planar gate is activated.

[0017] In various embodiments, the method includes: configuring a first planar gate to be deactivated when a second planar gate is activated; and configuring the second planar gate to be deactivated when the first planar gate is activated. In various embodiments, the method includes: deploying a first deep insulating trench on a first side of a substrate; and deploying a second deep insulating trench on a second side of the substrate, wherein the first and second deep insulating trenches are configured to create a pinning potential at the substrate to deplete the substrate.

[0018] In various embodiments, the method includes: activating a first vertical gate using a first vertical gate control signal, wherein the first vertical gate control signal is a DC voltage; and activating a second vertical gate using a second vertical gate control signal, wherein the second vertical gate control signal is a DC voltage.

[0019] In various embodiments, the method includes: electrically coupling a first sensing node to a first supplementary capacitor; electrically coupling a second sensing node to a second supplementary capacitor; and configuring the first and second supplementary capacitors to determine an indirect time-of-flight or two-dimensional density image using a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor.

[0020] In various embodiments, the method includes: deploying a third vertical gate inside a substrate; deploying a fourth vertical gate inside the substrate, wherein the first, second, third, and fourth vertical gates are configured to direct the one or more carriers to a transfer region of the substrate; deploying a third planar gate on the substrate, wherein the third planar gate is configured to direct the one or more carriers to a third sensing node when the third planar gate is activated; deploying a fourth planar gate on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated; electrically coupling an input terminal of the third planar gate to the third planar gate to receive a third planar gate control signal; and electrically coupling an input terminal of the fourth planar gate to the fourth planar gate to receive a fourth planar gate control signal, wherein the first, second, third, and fourth planar gate control signals comprise periodic waveforms and are spaced apart from each other by a 90° phase shift.

[0021] The above description of the invention is merely an overview of some exemplary embodiments to provide a basic understanding of some aspects of this disclosure. Therefore, it should be understood that the above embodiments are merely examples and should not be construed as limiting the scope or spirit of this disclosure in any way. It should also be understood that the scope of this disclosure covers many potential embodiments in addition to those summarized herein, some of which will be further described below. Attached Figure Description

[0022] Some exemplary embodiments of this disclosure have been described in general terms above. Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0023] Figure 1 This is a schematic diagram of the iToF determination system.

[0024] Figure 2 This is a schematic diagram of the pixels shown.

[0025] Figure 3A This is a schematic diagram illustrating pixels according to various embodiments of the present disclosure.

[0026] Figure 3B This is a schematic diagram illustrating pixels according to various embodiments of the present disclosure.

[0027] Figure 3C This is a schematic diagram illustrating pixels according to various embodiments of the present disclosure.

[0028] Figure 4 This is a schematic diagram illustrating the operation of pixels according to various embodiments of the present disclosure.

[0029] Figure 5 This is a schematic diagram illustrating pixels according to various embodiments of the present disclosure.

[0030] Figure 6 This is a flowchart illustrating a method according to various embodiments of the present disclosure.

[0031] Figure 7 This is a flowchart illustrating a method according to various embodiments of the present disclosure.

[0032] Figure 8 An example computing device according to one or more embodiments of the present disclosure is illustrated. Detailed Implementation

[0033] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the present disclosure. In fact, various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to enable the present disclosure to meet applicable legal requirements. The same reference numerals always denote the same elements.

[0034] The phrases “in one embodiment,” “according to one embodiment,” “in some embodiments,” “in multiple embodiments,” etc., generally indicate that a particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of this disclosure and may be included in more than one embodiment of this disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0035] The terms “example” or “exemplary” are used herein to mean “used as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0036] If a component or feature is described in the specification as "may," "can," "possibly," "should," "will," "preferably," "likely," "usually," "optionally," "for example," "often," or "maybe" (or other similar language) as being included or having that feature, then that particular component or feature does not need to be included or have that feature. In some embodiments, such a component or feature may be optionally included or may be excluded.

[0037] The terms “electrical coupling,” “communication with,” “electronic communication with,” or “connection” in this disclosure mean that two or more elements or components are connected by wired and / or wireless means such that signals, voltages / currents, data, and / or information can be sent to and / or received from these elements or components.

[0038] Various embodiments of this disclosure relate to improved systems, apparatuses, products, and methods for light detection, for example, by using improved light detection systems. In various embodiments, the light detection system can be used in 3D imaging, for example, using indirect time-of-flight (iToF) measurements.

[0039] In 3D imaging, the distance to an object can be determined. One method for measuring the distance to an object is time-of-flight (ToF) measurement. In a ToF system, the time it takes for a light beam to travel from the emitter to the object and back to the detector is measured. Using the speed of light and the time of propagation, the distance to the object can be measured.

[0040] In an indirect time-of-flight (iToF) system, the distance to an object is indirectly measured by using the phase shift of the received beam relative to the emitted beam.

[0041] Now for reference Figure 1 A schematic diagram of an indirect time-of-flight (iToF) measurement system 100 is provided. The iToF measurement system 100 includes a transmitter 102 configured to emit a light beam 104 having, for example, a sine wave 106. In this example, the emitted light beam 104 may be an intensity-modulated continuous wave. The emitted light beam can be reflected from an object 108. The reflected light beam 110 is detected by a pixel 112. In various embodiments, pixel 112 is a light-detecting pixel.

[0042] In order to determine the phase shift between the reflected beam and the emitted beam, pixel 112 can reconstruct its sine wave after detecting the reflected beam 110.

[0043] To reconstruct the sine wave, pixel 112 samples the detected beam. When the beam is received by pixel 112, the pixel generates electron carriers (e) and holes (h). The carriers are sampled using switches S1 and S2 and guided to the corresponding sensing nodes SN1 or SN2 for detection.

[0044] The charge carriers detected at sensing nodes SN1 and SN2 charge the corresponding capacitors. For example, sensing node SN1 charges the first capacitor 122, and sensing node SN2 charges the second capacitor 124. Controller 114 can compare the charge stored at the capacitors to reconstruct the phase value of the reflected beam.

[0045] Sensing nodes SN1 and SN2 can be floating nodes, and the voltage of the sensing nodes may need to be reset after each detection cycle to prepare for another charge acquisition and measurement. Switches 116 and 118 can use a reset signal to reset the voltage to V. DC .

[0046] In some examples, the emitted light beam can be in the near-infrared (NIR) wavelength range of 800 nm–1100 nm, for example, 940 nm. In other examples, the emitted light beam can be in the short-wave infrared (SWIR) wavelength range of 1100 nm–3000 nm. Therefore, suitable materials in pixel 112 can be used to detect light beams in the corresponding wavelength range. For example, silicon has good absorption in the NIR wavelength range and can be used in pixel 112 for use in iToF and other imaging systems. Other materials (such as Ge and InGaAs) can be used in the SWIR wavelength range.

[0047] Now for reference Figure 2 The diagram illustrates a pixel 200 according to various embodiments already in use. The pixel 200 may include a substrate 202. In various embodiments, the substrate 202 is a silicon substrate. The pixel 200 includes a PN junction 208 located at the center of the pixel between a first planar gate 204 and a second planar gate 206. The PN junction 208 may be created, for example, by an N-well 210. The N-well 210 may be an N-implantation region approximately located at the center of the pixel 200.

[0048] When a light beam is incident on substrate 202, charge carriers are generated in substrate 202. PN junction 208 creates an electrostatic potential gradient that transfers charge carriers to the top of the pixel. By switching between activation of the first planar gate 204 and the second planar gate 206, charge is driven to either the first sensing node 212 or the second sensing node 214. The first and second planar nodes can use an AC signal V. AC Activated.

[0049] The first and second sensing nodes can be electrically coupled to the N+ region of the semiconductor. The N+ region can have a high concentration of N-type impurity dopant. In this example, the N+ region can reduce the contact resistance with the sensing node. For example, the N+ region can be N-type fuse diffusion made of arsenic or phosphorus dopant.

[0050] Now for reference Figure 3A The present disclosure provides schematic diagrams of a pixel 300 according to various embodiments thereof. In various embodiments, the pixel 300 includes a substrate 302. The substrate 302 may be configured to generate one or more charge carriers in response to an incident light beam (e.g., a reflected light beam 110). In various embodiments, the pixel 300 includes a transparent layer 322 at a surface of the substrate 302, at which the substrate is configured to absorb the incident light beam. The transparent layer 322 may include any of an anti-reflective layer, a lens, a microlens array, etc.

[0051] In various embodiments, pixel 300 includes a first vertical gate 334 and a second vertical gate 336 disposed within substrate 302. The first and second vertical gates may be configured to direct one or more charge carriers generated in response to an incident light beam to a higher region of the substrate, such as integration zone 308. In various embodiments, the higher region may refer to a region remote from the surface of the substrate receiving the incident light beam. In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers to a transfer region 309 of the substrate. Transfer region 309 may be higher than integration zone 308.

[0052] In various embodiments, pixel 300 includes a first planar gate 304 and a second planar gate 306. In various embodiments, the first planar gate 304 and the second planar gate 306 are disposed on substrate 302. The first planar gate 304 and the second planar gate 306 can be fabricated by depositing a layer of silicon oxide and a conductive material (such as doped polysilicon or metals such as Al, W, Ag).

[0053] In example embodiments, the substrate height can be between 5 and 12 micrometers when operating in the NIR wavelength range. In example embodiments, the depths of the first vertical gate 334 and the second vertical gate 336 can be between 0.3 and 2 micrometers, for example, 1 micrometer. In example embodiments, if a material different from silicon with higher absorption is used, the substrate height can be even smaller. In various embodiments, the height of the vertical gates is typically between about 5% and 30% of the substrate height.

[0054] In various embodiments, the first and second vertical gates and the first and second planar gates are used for the efficient transfer of charge carriers from the substrate 302 to the first sensing node 310 and the second sensing node 312.

[0055] In various embodiments, pixel 300 includes a first vertical gate input 344 electrically coupled to a first vertical gate and configured to receive a first vertical gate signal. Pixel 300 may include a second vertical gate output 346 electrically coupled to a second vertical gate and configured to receive a second vertical gate signal. In various embodiments, the first and second vertical gates are configured to be activated using first and second vertical gate signals, and to direct one or more charge carriers to a transfer region when activated. In various embodiments, the first and second vertical gates may be activated concurrently. The first and second vertical gate control signals are DC voltages. In various embodiments, the same DC voltage may be applied to all vertical gates.

[0056] In various embodiments, a first planar gate control signal applied to a first planar gate input 314 and a second planar gate control signal applied to a second planar gate input 316 are used to activate the first planar gate 304 and the second planar gate 306. In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers to the first sensing node 310 or the second sensing node 312 using the first and second planar gate control signals.

[0057] For example, by activating the vertical gate, one or more charge carriers can be directed to the transfer region 309. In various embodiments, a potential in region 309 can also be generated due to an appropriate doping profile of the substrate and the potential applied to the deep insulating trenches 324 and 326, as further described below. By alternately activating the first and second planar gates, a potential is created in the substrate 302, and the one or more charge carriers are directed from the transfer region 309 to the corresponding sensing node. For example, when the first planar gate 304 is activated, charge carriers are directed toward the first planar gate and directed to the first sensing node. When the second planar gate 306 is activated, charge carriers are directed toward the second planar gate and directed to the second sensing node.

[0058] In example embodiments, pixel 300 directs charge carriers to the corresponding sensing node without requiring a PN junction created via deep N-well injection (e.g., as described with respect to pixel 200). By eliminating the need for an N-well, various embodiments provide reduced process variations in pixel fabrication while improving the efficiency of charge carrier transfer to the sensing node. Reducing process variations in pixel fabrication can reduce mismatches and / or inconsistencies between individual pixels in a pixel array or matrix.

[0059] In various embodiments, when the second planar gate is activated, the first planar gate is deactivated, and when the first planar gate is activated, the second planar gate is deactivated. The planar gates can be activated using, for example, periodic signals generated by a voltage and / or current source 320. The voltage source 320 can generate a first planar gate control signal and a second planar gate control signal. The first and second planar gate control signals can have periodic waveforms and can be complementary to each other. For example, at a given time, the first planar gate control signal applied to the input of the first planar gate can have a high value, while the second planar gate control signal applied to the input of the second planar gate will have a low value.

[0060] In the example embodiment, compared to pixel 200, pixel 300 provides a more homogeneous electrostatic potential in the substrate, having a gradient toward the vertical gate and then toward the corresponding sensing node when the corresponding planar gate is activated.

[0061] In various embodiments, the first and second sensing nodes are floating junctions, and the signals they generate will vary as charge carriers are directed to each sensing node. This may be because each sensing node has an inherent capacitance, and the charge on the inherent capacitance and its corresponding voltage can change as charge carriers are transferred to the corresponding sensing node. In various embodiments, the inherent capacitance of each sensing node is supplemented, for example, by using a supplementary capacitance that can be provided by an external capacitor. In various embodiments, when pixel 300 is used as an iToF pixel, the charge accumulated on each sensing node and / or the supplementary capacitor electrically coupled in parallel with the sensing node is measured for iToF determination, such as by reference, for example. Figure 1 As described.

[0062] In various embodiments, the pixel alternates between charge collection at the first and second sensing nodes by switching between activations of the planar gate. By doing so over a period of time, the controller 114 can integrate the first charge collection at the first sensing node and the second charge collection at the second sensing node. Using the integrated value, a reconstruction of the phase shift suffered when the light beam is reflected from the object and received by the pixel is determined.

[0063] In various embodiments, by faster alternation between charge collection at different sensing nodes, pixel 300 can provide a more accurate measurement of the phase shift of the reflected signal for iToF determination. In example embodiments, for instance, compared to pixel 200, pixel 300 enables the planar gate to be activated and deactivated at a higher frequency, thus allowing for faster alternation between charge collection at the first and second sensing nodes to achieve more accurate iToF measurements.

[0064] In various embodiments, a higher drive potential is created in the substrate volume and charge carriers are directed to the transfer region by etching a deep vertical gate in the pixel 300 within the substrate. Therefore, charge carriers are subsequently directed to the sensing node more efficiently with lower amplitude requirements for the planar gate control signal.

[0065] In various embodiments, pixel 300 includes a first deep insulating trench 324 and a second deep insulating trench 326. The deep insulating trenches may extend to the same depth as the substrate. In various embodiments, the substrate may be completely surrounded by a plurality of deep insulating trenches.

[0066] In various embodiments, the first deep insulating trench 324 and the second deep insulating trench 326 create a pinning potential at the substrate to deplete the substrate. In various embodiments, a DC voltage signal can be applied to the deep insulating trenches to create the pinning potential. For example, a DC bias voltage can be applied to the first deep insulating trench 324, and a DC bias voltage can be applied to the second deep insulating trench 326.

[0067] In the example embodiment, using vertical gates and deep insulating trenches, a uniform electrostatic field can be generated from bottom to top in the substrate to guide charge carriers to the transfer region, and then planar gates are used to guide the charge carriers in the correct direction to the corresponding sensing node near the top, depending on which planar gate is activated.

[0068] In various embodiments, a lateral gradient of the electrostatic field is created by deep insulating trenches to deplete the substrate, and a vertical gradient of the electrostatic field is created by a vertical gate that extends upwards to the sensing node corresponding to the vertical gate activated at a given time.

[0069] In various embodiments, the deep insulating trench and vertical gate are fabricated using dielectric pads (e.g., SiO2 or HK materials, HfO2, Al2O3, etc.) and then filled with a conductive material (e.g., doped polycrystalline silicon or metals such as Al, W, Ag, etc.). In various embodiments, the substrate is made of silicon, Ge, or InGaAs, as previously described.

[0070] In various embodiments, different arrangements for vertical gates and planar gates can be possible. Reference now. Figure 3A The diagram provides a top-view illustration of the arrangement of various components of a pixel 300 according to various embodiments of the present disclosure. In the embodiments, the first and second vertical gates, the first and second planar gates, the first and second sensing nodes, and their corresponding N+ regions can be approximately arranged on a straight line 352. Figure 3BThis is a schematic diagram illustrating another arrangement of pixels 350 according to various embodiments of the present disclosure. For example, first and second vertical gates may be approximately arranged on a first straight line 354, while first and second planar gates, first and second sensing nodes, and their corresponding N+ regions may be approximately arranged on a second straight line 356. The first and second lines may be approximately perpendicular to each other.

[0071] Now for reference Figure 4 The illustration provides schematic diagrams showing examples of the operation of pixel 300 according to various embodiments of the present disclosure in three-dimensional (3D) imaging or iToF measurement and in two-dimensional (2D) imaging. Figure 4 As shown, line 402 is a schematic diagram of the electrostatic potential level in pixel 300 according to various embodiments.

[0072] In various embodiments, pixel 300 can operate in 3D imaging or iToF mode. When in iToF mode, the first and second vertical gates of the pixel are configured to be activated to guide carriers to the transfer region. In various embodiments, the first and second planar gates of the pixel can be configured to be activated alternately using a first planar gate control signal and a second planar gate control signal. In various embodiments, at a given time, the first planar control signal is complementary to the second planar control signal.

[0073] In various embodiments, when the first planar gate is deactivated, it creates a low gate that acts as a transfer region of the substrate (e.g., Figure 3A The potential barrier between the carriers in the transfer region 309 and the first sensing node. In iToF mode, when the first planar gate is deactivated, the second planar gate can be activated, such as, for example... Figure 4 As shown in the diagram, when the second planar gate is activated, it creates a high gate, which acts as a potential gradient to guide charge carriers to the second sensing node. By alternately activating and deactivating the first and / or second planar gates, when operating in iToF mode, pixel 300 alternately guides charge to the corresponding first or second sensing node.

[0074] In the example embodiment, by not using the PN junction or N-well in the integration region, the activation and / or deactivation of the first and second planar gates in pixel 300 can be performed at a higher frequency and with a lower amplitude. Therefore, measurement accuracy can be increased and pixel power consumption can be reduced.

[0075] In various embodiments, pixel 300 can operate in 2D imaging, for example, using light intensity acquisition. When operating in 2D imaging, the first vertical gate and the two planar gates can be configured to be simultaneously deactivated for a first time period, which may be referred to as the integration time. During the integration time, charge carriers generated in response to the incident light beam can accumulate in the integration region of the substrate. In various embodiments, the barrier created during the integration time can be a stronger barrier than the barrier created during iToF mode to allow for greater charge accumulation for 2D imaging.

[0076] In various embodiments, then for a second time period, the first and second vertical gates and / or the first planar gate or the second planar gate may be activated; this second time period may be referred to as the readout time. During the readout time, an intensity signal for a pixel is generated, which may represent a 2D image pixel. In various embodiments, the vertical gates are activated and deactivated using first and second vertical gate control signals, and the planar gates are activated and deactivated using first and second planar gate control signals.

[0077] During the readout time, either the first or second vertical charge carrier can be activated. When the vertical gate is activated, it creates a high gate, which acts as a potential gradient to guide the integrated charge carriers to the corresponding sensing node for readout of the captured 2D image in the pixel.

[0078] In the example embodiment, greater carrier integration can be achieved in the integration region by not using a PN junction or N-well. Using a vertically embedded gate deep within the pixel allows for a gate with low bias, creating a significantly low gate barrier, thereby allowing a significantly large number of carriers to be stored in the pixel's bulk.

[0079] Therefore, in the example embodiment, the pixel can operate in 3D or 2D imaging mode by simply changing the bias conditions of the vertical and planar gates using vertical and planar gate control signals.

[0080] Now for reference Figure 5 The present invention provides a top-view schematic diagram of a pixel 500 according to various embodiments of the present disclosure. In various embodiments, the pixel 500 includes a first vertical gate 524, a second vertical gate 526, a third vertical gate 528, and a fourth vertical gate 530 disposed within a substrate 502. In various embodiments, the vertical gates are embedded in the substrate 502. The vertical gates may be deep trenches disposed within the substrate 502. In various embodiments, the vertical gates are configured to guide charge carriers to a transfer region of the substrate 502.

[0081] In various embodiments, the cross-section of the vertical gate can have various shapes. For example, one or more vertical gates can have an L-shaped cross-section. The L-shaped cross-section can provide a strong and / or homogeneous electrostatic field in the substrate to guide charge carriers to the transfer region. In various embodiments, the cross-section of the vertical gate can have any other geometry, such as square, rectangular, trapezoidal, circular, elliptical, and / or any combination thereof.

[0082] In various embodiments, pixel 500 includes a first planar gate 504, a second planar gate 506, a third planar gate 508, and a fourth planar gate 510 disposed on substrate 502. In various embodiments, the first, second, third, and fourth planar gates are configured to direct one or more carriers from a transfer region to a first sensing node 514, a second sensing node 516, a third sensing node 518, or a fourth sensing node 520. In various embodiments, each planar gate is configured to transfer carriers to a corresponding sensing node. For example, the first planar gate may be configured to direct carriers to the first sensing node, the second planar gate may be configured to direct carriers to the second sensing node, the third planar gate may be configured to direct carriers to the third sensing node, and the fourth planar gate may be configured to direct carriers to the fourth sensing node. In various embodiments, the first planar gate may be disposed near the first sensing node, the second planar gate may be disposed near the second sensing node, the third planar gate may be disposed near the third sensing node, and the fourth planar gate may be disposed near the fourth sensing node. In various embodiments, each sensing node may be deployed on and / or electrically coupled to the corresponding N+ region.

[0083] In various embodiments, the vertical gate, planar gate, and sensing node can be arranged in various ways on the substrate 502. For example, the vertical gate and planar gate (or sensing node) can be generally arranged on a square shape 540. In other examples, the vertical gate and planar gate (or sensing node) can be arranged on various other shapes, such as circular, elliptical, rectangular, etc. In the example embodiments, by arranging the vertical gate and planar gate (or sensing node) as described herein, the carrier transfer efficiency from the substrate to the corresponding sensing node is increased.

[0084] In various embodiments, the planar gates can have various cross-sectional shapes. For example, at least one or all of the first, second, third, or fourth planar gates can have various cross-sectional shapes surrounding the corresponding sensing node and can completely or partially surround the corresponding sensing node. In various embodiments, at least one or all of the planar gates can partially surround the sensing node, for example by having a C-shaped, F-shaped, or h-shaped cross-section. In various embodiments, at least one or all of the planar gates can completely surround the corresponding sensing node, for example by having a circular (e.g., O) or b-shaped cross-section surrounding the corresponding sensing node. In various embodiments, when more than one planar gate corresponds to a sensing node, the planar gates completely or partially surrounding the sensing node can be concentric or off-center relative to each other.

[0085] In various embodiments, each vertical gate is electrically coupled to a vertical gate input and configured to receive a vertical gate control signal. The vertical gate control signal may be a DC voltage.

[0086] In various embodiments, each planar gate is electrically coupled to a planar gate input and configured to receive a corresponding planar gate control signal. Each planar gate control signal may include a periodic waveform to periodically enable and disable the corresponding planar gate. In various embodiments, when using four planar gates and corresponding four sensing nodes, the planar gate control signals may be offset from each other by 90º. In example embodiments, this provides a finer-grained transfer of charge carriers to the corresponding sensing node. Thus, pixel 500 may, for example, provide 4-tap sampling per cycle of the incident reflected beam to achieve more accurate iToF determination.

[0087] In various embodiments, a pixel may include more than four vertical, planar, and / or sensing nodes, and may be arranged in various forms, such as in a manner similar to that described above. When using more sensing nodes, sampling with higher taps per cycle can be performed in the iToF determination.

[0088] In various embodiments, a pixel may include two or more planar gates for each sensing node. For example, two or more planar gates corresponding to a sensing node may be deployed near that sensing node and guide carriers from the transfer region to the corresponding sensing node. For example, when the first and / or second planar gates are activated using a first and / or second planar gate control signal, carriers are guided to the first sensing node. And, for example, when the third and / or fourth planar gates are activated using a third and / or fourth planar gate control signal, carriers are guided to the second sensing node. In various embodiments, all vertical gates may be activated to guide carriers to the transfer region.

[0089] In various embodiments, pixel 500 may include one or more deep insulating trenches located on each side of the substrate. The deep insulating trenches may be configured to create a pinning potential at the substrate to deplete the substrate.

[0090] In the example embodiments, the vertical gate provided herein can have a higher driving capability across the entire volume of the pixel substrate than the planar gate. This reduces the amplitude requirement of the signal applied to the planar gate, since the vertical gate first directs carriers to a transfer region closer to the planar gate. Therefore, a small voltage for the planar gate control signal is sufficient to provide carrier transfer to the corresponding sensing node. Thus, by requiring a lower amplitude for the planar gate control signal, pixel efficiency can be increased.

[0091] In example embodiments, the use of vertical gates and their higher drive capability allows for an increase in substrate volume without degrading pixel frequency performance. For example, due to the uniform and strong electric field gradient generated by the vertical gate and the resulting strong driving force on charge carriers, using a vertical gate increases the quantum efficiency (QE) of the pixel by increasing the thickness of the substrate silicon volume without degrading performance. In example embodiments, QE can represent the ratio of total charge carriers measured by the pixel's sensing node to the total incident photons on the pixel. In example embodiments, the use of vertical gates and planar gates as described herein can also maintain high demodulation contrast (DMC) in the pixel. DMC can indicate an estimate of the rate at which the pixel collects and / or detects photons at its operating frequency.

[0092] Now for reference Figure 6 The present disclosure provides schematic diagrams of a method 600 according to various embodiments thereof. In various embodiments, method 600 can be used to manufacture and / or prepare light-detecting pixels, such as pixel 300 as described above.

[0093] In various embodiments, in step 602, method 600 deploys a first vertical gate and a second vertical gate within a substrate (e.g., substrate 302). In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers generated in the substrate to a transfer region of the substrate. The one or more charge carriers may be generated within the substrate in response to an incident light beam.

[0094] In various embodiments, in step 604, method 600 deploys a first planar gate and a second planar gate on the substrate. The first and second planar gates can be configured to direct one or more charge carriers from the transfer region to a first sensing node or a second sensing node.

[0095] In various embodiments, in step 606, method 600 configures a first vertical gate input to receive a first vertical gate control signal. The first vertical gate input may be electrically coupled to a first vertical gate. In various embodiments, in step 608, method 600 configures a second vertical gate input to receive a second vertical gate control signal. The second vertical gate input may be electrically coupled to a second vertical gate. In various embodiments, the first and second vertical gate control signals may be DC voltages.

[0096] In various embodiments, in step 610, method 600 configures a first planar gate input to receive a first planar gate control signal. The first planar gate input may be electrically coupled to a first planar gate. In various embodiments, in step 612, method 600 may configure a second planar gate input to receive a second planar gate control signal. The second planar gate input may be electrically coupled to a second planar gate. In various embodiments, the first and second planar gates are configured to direct one or more charge carriers to a first sensing node or a second sensing node using the first and second planar gate control signals.

[0097] In various embodiments, the first and second planar gates are configured to direct one or more charge carriers to a first capacitor or a second capacitor using first and second planar gate control signals. In example embodiments, the first and second sensing nodes have inherent capacitance and are first and second capacitors. In various embodiments, the capacitance of the first and second sensing nodes is supplemented by supplementary capacitors; for example, capacitor 122 may be a first supplementary capacitor electrically coupled to the first sensing node, and capacitor 124 may be a second supplementary capacitor electrically coupled to the second sensing node, such as... Figure 1 As shown in the example embodiment. In this example, the supplementary capacitor may be an external capacitor.

[0098] Now for reference Figure 7 The present disclosure provides schematic diagrams of a method 700 according to various embodiments thereof. In various embodiments, method 700 can be used to manufacture and / or prepare light-detecting pixels, such as pixel 300 as described above.

[0099] In various embodiments, in step 702, method 700 configures the first and second vertical gates to be activated using first and second vertical gate control signals. When the first and second vertical gates are activated, they can direct one or more charge carriers to the transfer region. In various embodiments, in step 704, method 700 configures the first planar gate to be activated using a first planar gate control signal, and when the first planar gate is activated, directs one or more charge carriers to the first sensing node.

[0100] In various embodiments, in step 706, method 700 uses a second planar gate control signal to configure the second planar gate to be activated, and when the second planar gate is activated, directs one or more carriers to the second sensing node.

[0101] In various embodiments, in step 708, method 700 configures the first planar gate to be deactivated when the second planar gate is activated. In various embodiments, in step 710, method 700 configures the second planar gate to be deactivated when the first planar gate is activated.

[0102] In various embodiments, one method may deploy a first deep insulating trench on a first side of a substrate and a second deep insulating trench on a second side of the substrate. The first and second deep insulating trenches may be configured to create a pinning potential at the substrate to deplete the substrate.

[0103] In various embodiments, a method may use a first vertical gate control signal to activate a first vertical gate. In various embodiments, the method may use a second vertical gate control signal to activate a second vertical gate. The first and second vertical gate control signals may be DC voltages.

[0104] In various embodiments, one method may electrically couple a first sensing node to a first supplementary capacitor and a second sensing node to a second supplementary capacitor. In various embodiments, the method uses a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor to determine an indirect time-of-flight or two-dimensional density image.

[0105] In various embodiments, one method may deploy a third vertical gate within the substrate. Another method may deploy a fourth vertical gate within the substrate. The first, second, third, and fourth vertical gates may be configured to direct one or more charge carriers to a transfer region of the substrate.

[0106] In various embodiments, one method may deploy a third planar gate on a substrate, wherein the third planar gate is configured to direct one or more charge carriers to a third sensing node when the third planar gate is activated. Another method may deploy a fourth planar gate on the substrate, wherein the fourth planar gate is configured to direct one or more charge carriers to a fourth sensing node when the fourth planar gate is activated.

[0107] In various embodiments, one method may electrically couple a third plane gate input to a third plane gate to receive a third plane gate control signal. Another method may electrically couple a fourth plane gate input to a fourth plane gate to receive a fourth plane gate control signal. In various embodiments, the first, second, third, and fourth plane gate signals may include periodic waveforms and be phase-shifted relative to each other by 90°.

[0108] It should be readily recognized that, in addition to the methods explicitly described herein, various additional and alternative methods may be used to configure embodiments of the systems, apparatus and methods described herein.

[0109] Figure 8 An example light detection system 800 according to one or more embodiments of the present disclosure is illustrated.

[0110] The optical detection system 800 may include a computing device 810 and / or one or more optical detection pixels 820 communicatively coupled to the computing device 810 using one or more wired and / or wireless communication technologies. Generally, the terms computing device, computer, system, apparatus, entity, and / or similar terms used interchangeably herein can refer to, for example, one or more computers, computing entities, desktop computers, mobile phones, tablet computers, notebook computers, laptop computers, distributed systems, kiosks, input terminals, servers or server networks, blade servers, gateways, switches, processing devices, processing entities, controllers, control systems, set-top boxes, repeaters, routers, network access points, base stations, etc., and / or any combination of apparatus or entities suitable for performing the functions, operations, and / or processes described herein. Such functions, operations, and / or processes may include, for example, sending, receiving, operating, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing, and / or similar terms used interchangeably herein. In one embodiment, these functions, operations, and / or processes may be performed on data, content, information, and / or similar terms used interchangeably herein. The computing device 810 may include any computing apparatus, including, for example, a light detection processing apparatus configured to perform one or more steps / operations of one or more light detection techniques described herein. In some examples, the computing device 810 may determine indirect time of flight (iToF) as described herein. In some examples, the computing device 810 may detect 2D images as described herein. In some embodiments, the computing device 810 may include one or more mobile devices, one or more desktop computers, one or more laptop computers, one or more servers, and / or one or more cloud computing platforms, etc., and / or associated therewith. In some example embodiments, the computing device 810 may be configured to receive and / or transmit light detection instructions, data, etc., between one or more light detection pixels 820 to perform one or more steps / operations of one or more light detection techniques described herein.

[0111] The computing device 810 may include one or more processing elements 802 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms used interchangeably herein), or communicate with one or more processing elements 802, which communicate with other elements within the computing device 810 via, for example, a bus. As will be understood, the processing elements 802 may be implemented in a variety of different ways.

[0112] For example, processing element 802 can be implemented as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, coprocessor entities, application-specific instruction set processors (ASIPs), microcontrollers, and / or controllers. Furthermore, processing element 802 can be implemented as one or more other processing devices or circuit systems. The term "circuit system" can refer to a completely hardware embodiment or a combination of hardware and computer program products. Therefore, processing element 802 can be implemented as an integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and / or a digital circuit system, etc.

[0113] Therefore, as will be understood, processing element 802 can be configured for a particular purpose or configured to execute instructions stored in volatile or non-volatile media or otherwise accessible to processing element 802. Thus, whether configured as a hardware or computer program product or a combination thereof, processing element 802, after appropriate configuration, is capable of performing steps or operations according to embodiments of this disclosure.

[0114] In one embodiment, the computing device 810 may further include one or more memory elements 104, or communicate with one or more memory elements 804. The one or more memory elements 104 may include non-volatile and / or volatile media. For example, memory element 804 may include non-volatile media (also referred to as non-volatile storage device, memory, memory storage device, memory circuitry, and / or similar terms used interchangeably herein). In one embodiment, a non-volatile storage device or memory may include one or more non-volatile storage devices or memory media, including but not limited to: hard disks, ROMs, PROMs, EPROMs, EEPROMs, flash memory, MMC, SD memory cards, Memory Sticks, CBRAMs, PRAMs, FeRAMs, NVRAMs, MRAMs, RRAMs, SONOS, FJG RAMs, Millipede memory, and / or racetrack memory, etc.

[0115] As will be recognized, non-volatile storage devices or memory media can store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, and / or executable instructions, etc. The terms database, database instance, database management system, and / or similarly used interchangeably in this document can refer to a collection of records or data stored in a computer-readable storage medium using one or more database models, such as hierarchical database models, network models, relational models, entity-relational models, object models, document models, semantic models, and / or graphical models, etc.

[0116] Additionally or alternatively, memory element 804 may include volatile memory. For example, computing device 810 may also include or communicate with volatile media (also referred to as volatile memory, memory storage, memory circuitry, and / or similar terms used interchangeably herein). In one embodiment, the volatile storage device or memory may also include one or more volatile storage devices or memory media, including but not limited to: RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, and / or register memory, etc.

[0117] As will be appreciated, volatile storage devices or memory media can be used to store at least a portion of databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, executed by, for example, processing element 802. Therefore, databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc., can be used to control certain aspects of the operation of computing device 810 with the assistance of processing element 802 and operating system.

[0118] As indicated, in one embodiment, computing device 810 may also include one or more communication interfaces 808 for communicating with various computing entities, such as by transmitting data, content, information, and / or similar terms that may be sent, received, manipulated, processed, displayed, and / or stored. Such communication may be performed using wired data transmission protocols such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Cable Data Service Interface Specification (DOCSIS), or any other wired transmission protocol. Similarly, the computing device 810 can be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rate GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolved Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High Speed ​​Downlink Packet Access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, Near Field Communication (NFC) protocol, Wibree, Bluetooth protocol, Wireless Universal Serial Bus (USB) protocol, and / or any other wireless protocol.

[0119] The optical detection system 800 may include an input / output circuitry for communicating with one or more users or other systems or devices. For example, the input / output circuitry may include one or more interfaces for providing and / or receiving information with one or more users or other systems or devices of the optical detection system 800, or vice versa. The input / output circuitry may be configured to receive user input or input from various other systems or devices through one or more interfaces of the optical detection system 800.

[0120] in conclusion

[0121] Many modifications and other embodiments of the disclosure herein will come to mind for those skilled in the art, having benefited from the teachings presented in the foregoing description and the associated drawings. While the figures illustrate only certain components of the apparatus and systems described herein, it should be understood that various other components may be used in conjunction with the system. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. The steps in the methods described above do not necessarily occur in the order depicted in the drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or additional steps may be involved. Although specific terminology is used herein, it is used only in a general and descriptive sense and not for limiting purposes.

[0122] While various embodiments based on the principles disclosed herein have been shown and described above, those skilled in the art can modify them without departing from the spirit and teachings of this disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of this disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of one or more embodiments are also within the scope of this disclosure. Therefore, the scope of protection is not limited by the foregoing description.

[0123] Furthermore, the section headings used herein are provided for the purpose of maintaining consistency with the recommendations of 37 CFR 1.77, or otherwise to provide organizational clues. These headings should not limit or characterize the disclosure(s) that may be set forth in any of the claims issued in this disclosure.

[0124] The use of broader terms such as “comprising,” “including,” and “having” should be understood to support narrower terms such as “consisting of,” “substantially consisting of,” and “truly consisting of.” The use of terms such as “optionally,” “may,” “perhaps,” and “possibly” with respect to any element of the embodiments indicates that the element is not essential, or alternatively, that the element is essential, both of which are within the scope of the embodiments(s). Furthermore, references to examples are for illustrative purposes only and are not intended to be exclusive.

[0125] While this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the foregoing embodiments with various modifications and improvements.

Claims

1. A pixel, characterized in that, include: The substrate is configured to generate one or more charge carriers in response to an incident light beam; A first vertical gate and a second vertical gate are disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more charge carriers to a transfer region of the substrate. as well as A first planar gate and a second planar gate are disposed on a substrate, wherein the first planar gate and the second planar gate are configured to guide the one or more carriers from the transfer region to a first sensing node or a second sensing node.

2. The pixel as described in claim 1, characterized in that, include: The first vertical gate input terminal is electrically coupled to the first vertical gate and configured to receive the first vertical gate control signal; The second vertical gate input terminal is electrically coupled to the second vertical gate and configured to receive the second vertical gate control signal; The first planar gate input terminal is electrically coupled to the first planar gate and configured to receive the first planar gate control signal; as well as The second planar gate input terminal is electrically coupled to the second planar gate and configured to receive the second planar gate control signal, wherein the first planar vertical gate and the second planar vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

3. The pixel as described in claim 2, characterized in that, in: The first vertical gate and the second vertical gate are configured to be activated using the first vertical gate control signal and the second vertical gate control signal, and to guide the one or more charge carriers to the transfer region when activated. The first planar gate is configured to be activated using a first planar gate control signal, and when activated, to direct the one or more charge carriers to the first sensing node; as well as The second planar gate is configured to be activated using a second planar gate control signal, and when activated, to direct one or more charge carriers to the second sensing node.

4. The pixel as described in claim 3, characterized in that, in: The first vertical gate and the second vertical gate are configured to be activated concurrently; The first planar gate is configured to be activated when the second planar gate is deactivated; as well as The second planar gate is configured to be activated when the first planar gate is deactivated.

5. The pixel as described in claim 4, characterized in that, The first vertical gate control signal and the second vertical gate control signal are DC voltages, and the first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

6. The pixel as described in claim 2, characterized in that, Also includes: The third vertical gate is deployed inside the substrate; A fourth vertical gate is disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate and the fourth vertical gate are configured to guide the one or more carriers to the transfer region; The third vertical gate input terminal is electrically coupled to the third vertical gate and configured to receive the DC third gate control signal; The fourth vertical gate input is electrically coupled to the fourth vertical gate and configured to receive the DC fourth vertical gate control signal. A third planar gate, deployed on a substrate and configured to direct one or more charge carriers to a third sensing node when the third planar gate is activated; A fourth planar gate is disposed on the substrate, wherein the fourth planar gate is configured to direct the one or more charge carriers to the fourth sensing node when the fourth planar gate is activated; The third plane gate input terminal is electrically coupled to the third plane gate and configured to receive the third plane gate control signal; as well as The fourth planar gate input is electrically coupled to the fourth planar gate and configured to receive the fourth planar gate control signal, wherein the first planar gate control signal, the second planar gate control signal, the third planar gate control signal and the fourth planar gate control signal comprise periodic waveforms and are spaced apart from each other by a 90° phase shift.

7. The pixel as described in claim 1, characterized in that, Also includes: A first deep insulating trench located on the first side of the substrate; as well as A second deep insulating trench located on a second side of the substrate, wherein the first deep insulating trench and the second deep insulating trench are configured to create a pinning potential at the substrate to deplete the substrate.

8. The pixel as described in claim 1, characterized in that, in: The first planar gate and the second planar gate are configured to be activated alternately using a first planar gate control signal and a second planar gate control signal, wherein at a given time, the first planar gate control signal is the complement of the second planar gate control signal; The first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal; and The pixels are configured to determine the indirect time of flight (iToF).

9. The pixel as described in claim 1, characterized in that, in: The first vertical gate and the second vertical gate are configured to be deactivated simultaneously, and the first planar gate and the second planar gate are configured to be deactivated simultaneously for a first time period; The first vertical gate and the second vertical gate are configured to be activated, and the first planar gate or the second planar gate is configured to be activated for the second time period. as well as The pixels are configured to provide two-dimensional imaging.

10. A pixel, characterized in that, include: The substrate is configured to generate one or more charge carriers in response to an incident light beam; A first vertical gate and a second vertical gate are disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more charge carriers toward the first vertical gate and the second vertical gate. The first planar gate input terminal is electrically coupled to the first planar gate and configured to receive the first planar gate control signal; as well as The second planar gate input is electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first planar gate and the second planar gate are configured to use the first gate control signal and the second gate control signal to guide the one or more charge carriers to the first capacitor or the second capacitor.

11. The pixel as claimed in claim 10, characterized in that, in: The first planar gate is configured to be activated using a first gate control signal, and when activated, to direct the one or more charge carriers to the first capacitor; as well as The second planar gate is configured to be activated using a second planar gate control signal, and when activated, to direct the one or more charge carriers to the second capacitor. The first planar gate and the second planar gate, as well as the first vertical gate and the second vertical gate, are deployed near the same surface of the substrate.

12. The pixel as claimed in claim 11, characterized in that, in: When the second planar gate is activated, the first planar gate is deactivated; When the first planar gate is activated, the second planar gate is deactivated; as well as The first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

Images