Constant current source circuit

Abstract

The utility model relates to a constant current source circuit, which comprises a threshold circuit, a comparator, an integrator, a shaping circuit, a reversing switch, a synchronous circuit, a positive shaping circuit, a negative shaping circuit and a constant current source, the integrator is used for accessing an input current I output end; the shaping circuit is used for accessing the output end of the sampling circuit CP; the shaping circuit outputs a synchronous circuit; the threshold circuit outputs a comparator; the change-over switch is connected to the constant current source, and the output of the change-over switch is connected with the integrator; the comparator comprises a positive comparator and a negative comparator; the synchronous circuit comprises a positive synchronous circuit and a negative synchronous circuit; the shaping circuit outputs a forward synchronous circuit and a forward shaping circuit respectively; the device is reasonable in design, compact in structure and convenient to use.

Description

Technical Field

[0001] This utility model relates to constant current source circuits and belongs to the field of constant current source technology, specifically to a constant current source circuit with single constant current source reset floating ground charge balance technology. Background Technology

[0002] In an inertial navigation system (hereinafter referred to as "INS"), the constant current source circuit is a core component of the I / F and V / F conversion circuits. It provides high-precision, low-temperature-drift current input to the I / F and V / F conversion circuits. Upon receiving the current input from the constant current source circuit, the I / F and V / F conversion circuits linearly convert the current signal into a pulse frequency signal, which is then provided to the navigation computer. After navigation calculation, the displacement information of the vehicle can be obtained. The accuracy of the constant current source circuit and the I / F conversion circuit directly affects the navigation accuracy of the INS.

[0003] Traditional dual constant current source reset, employing a dual-reference and dual-sampling structure, can meet symmetry requirements at room temperature. However, due to the difference in temperature stability between the dual-reference and dual-sampling structures, it cannot meet high- and low-temperature symmetry requirements. Furthermore, dual constant current source reset consumes relatively more power and generates more heat, creating a larger temperature gradient, which fails to meet nonlinearity and symmetry requirements. Utility Model Content

[0004] To meet the increasingly stringent miniaturization and integration requirements of inertial navigation systems and enhance product market competitiveness, the project team decided to conduct research on single constant current source reset floating ground charge balancing technology. The goal is to improve upon existing traditional dual constant current source reset circuits by using a single constant current source. The single constant current source power supply is isolated from the power supply of the preceding signal processing stage, and the single constant current source and the preceding ground are controlled by logic to form a stable dual-channel reset. This single constant current source reset floating ground charge balancing technology circuit can be widely applied in the automatic navigation of aircraft, automobiles, and ships.

[0005] The technical problem to be solved by this utility model is, in general, to provide a constant current source circuit.

[0006] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0007] A constant current source circuit includes a threshold circuit, a comparator, an integrator, a shaping circuit, a commutation switch, a synchronization circuit, a positive shaping circuit, a negative shaping circuit, and a constant current source.

[0008] The integrator is used to connect the input current I. i Output terminal;

[0009] The shaping circuit is used to connect to the CP output terminal of the sampling circuit;

[0010] The shaping circuit outputs a synchronous circuit;

[0011] Threshold circuit output comparator;

[0012] The commutator is connected to a constant current source, and the output of the commutator is connected to an integrator.

[0013] Comparators include positive comparators and negative comparators;

[0014] Synchronization circuits include positive synchronization circuits and negative synchronization circuits;

[0015] The shaping circuit outputs both a positive synchronization circuit and a positive shaping circuit.

[0016] The integrator outputs a positive comparator and a negative comparator respectively;

[0017] The threshold circuit outputs a positive comparator and a negative comparator respectively;

[0018] The positive comparator and the negative comparator are connected to the positive synchronization circuit and the negative synchronization circuit, respectively;

[0019] The forward synchronization circuit outputs a commutation switch and a forward shaping circuit, respectively;

[0020] The negative synchronization circuit outputs a commutation switch and a negative shaping circuit, respectively.

[0021] Furthermore, the positive shaping circuit and the negative shaping circuit respectively output signals f o +、f o -

[0022] Furthermore, the integrator has two states: forward integration and backward integration;

[0023] The integrator includes operational amplifier U1 and capacitor C1;

[0024] Pin 1 of op-amp U1 is grounded, pin 4 is connected to -15V; pin 3 is grounded, pin 2 is split into three paths: one path is grounded through capacitor C1, the second path is connected to current Iin through resistor Rin, and the third path is connected to a constant current source through the FW terminal.

[0025] Pin 6 of op-amp U1 outputs two paths through resistor R1, which are respectively supplied to op-amp U2 and op-amp U3;

[0026] The output terminal of resistor R1 is electrically connected to the bases of transistors Q1 and Q2 respectively;

[0027] The collector of transistor Q1 is connected to +15V through resistor R2;

[0028] The collector of transistor Q2 is grounded through resistor R3.

[0029] Furthermore, the integral charge of the input current of the integrator and the integral charge of the reset of the constant current source are equal in value but opposite in direction. The integral charge of the input current Iin is linearly related to the input current Iin, and the integral charge of the reset is proportional to the reset time.

[0030] The number of output pulses of the integrator is directly proportional to the input current; the integration voltage of the integrator is inversely related to the circuit threshold.

[0031] The comparator circuit includes a comparator circuit and a threshold circuit that are electrically connected;

[0032] Threshold circuit, used to generate comparison threshold voltage;

[0033] The threshold circuit includes a proportional resistor electrically connected to the ±15V power supply.

[0034] The positive comparator includes an operational amplifier U2 that is electrically connected to the +15V power supply of the threshold circuit.

[0035] The negative comparator includes an operational amplifier U3 that is electrically connected to the -15V power supply of the threshold circuit.

[0036] The input terminals of operational amplifiers U2 and U3, and the output terminal of operational amplifier U1, Vout;

[0037] Several resistors are electrically connected between the output terminals of operational amplifier U2 and operational amplifier U3;

[0038] Operational amplifiers U2 and U3 output levels K+ and K-, respectively;

[0039] The FW terminal of the constant current source is connected to the emitters of transistors Q1 and Q2 through a series capacitor C*4 and a resistor R11; the emitters of transistors Q1 and Q2 are connected to pin 2 of operational amplifier U2 and pin 3 of operational amplifier U3, respectively; the emitters of transistors Q1 and Q2 are grounded through resistor R4.

[0040] Pin 3 of op-amp U2 is connected to +15V through resistor R5; pin 2 of op-amp U3 is grounded through resistor R8.

[0041] The reversing switch, as a switching circuit, includes chip U3Z. Pins 8 and 9 are connected to pin 6 of D flip-flop U2AZ, and pins 1 and 16 are connected to pin 8 of D flip-flop U2BZ. Pin 14 is electrically connected to signal FW.

[0042] The constant current source includes operational amplifiers U6 and U7.

[0043] The op-amp U2 has two outputs at pin 7. One output is connected to 5V through resistor R9, and the other output is connected to pin 2 of chip U4A.

[0044] The op-amp U3 has two outputs at pin 7. One output is connected to 5V through resistor R10, and the other output is connected to pin 12 of chip U4B.

[0045] Chip U4A has three outputs at pin 5: one is connected to chip U5B, two are connected to MOSGM1, and the third is grounded through capacitor C6; pin 6 is electrically connected to MOSGM2; the S terminal of MOSGM1 is connected to the FW terminal, and the D terminal is connected to H+15V; the D terminal of MOSGM2 is connected to the FW terminal, and the S terminal is grounded; chip U5B has an output port F-.

[0046] Chip U4B has three outputs at pin 9: one is connected to chip U5A, two are connected to MOSGM3, and the third is grounded through capacitor C*1; pin 8 is electrically connected to MOSGM4; the S terminal of MOSGM3 is connected to the COM terminal, and the D terminal is connected to the FW terminal; the S terminal of MOSGM4 is connected to the COM terminal, and the D terminal is grounded; chip U5A outputs port F+.

[0047] Op-amp U6 is pre-connected to chip U8; pins 2 and 3 of chip U8 are connected to H+15V voltage; pins 9 and 10 of chip U8 are connected to ground through parallel capacitors C3 and C2, and the other is connected to input pin 30 of op-amp U6; pin 2 of op-amp U6 is grounded through resistor R12, and pin 6 is connected to pin 3 of op-amp U7; pin 6 is connected to pin 2 through resistor R13.

[0048] Pin 2 of op-amp U7 is grounded through sampling resistor RS, pin 6 is electrically connected to pin 2 of MOSGQ3, and pin 1 of MOSGQ3 is grounded through capacitor C*3 and connected to the signal COM terminal;

[0049] Pin 1 of MOSGQ3 is electrically connected to the collector of transistor Q4, pin 3 of MOSGQ3 is connected to the base of transistor Q4, and the emitter of transistor Q4 is connected to the sampling resistor RS through resistor R15.

[0050] This invention addresses the shortcomings of existing traditional dual constant current source reset circuits, particularly the differences in temperature stability between dual reference and dual sampling circuits, which fail to meet the requirements for high and low temperature symmetry. Furthermore, dual constant current source reset circuits consume relatively large amounts of power and generate significant heat, creating large temperature gradients and failing to meet nonlinearity and symmetry requirements. The invention provides a high-precision, low-temperature drift single constant current source reset floating ground charge balance technology that employs a single reference and single sampling, with constant current sources fabricated in isolation between the front and rear stages, and the same constant current source used as the reset reference for both positive and negative channel I / F conversion.

[0051] The positive and negative two-channel I / F conversion uses the same constant current source to achieve high-precision, low-temperature drift single constant current source reset floating ground charge balance of the reset reference. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of the principle of this utility model.

[0053] Figure 2 This is a waveform diagram of the circuit operation of this utility model.

[0054] Figure 3 This is a schematic diagram of the integrator principle of this utility model.

[0055] Figure 4 This is a schematic diagram of the negative current input of the integrator output waveform of this utility model.

[0056] Figure 5 This is a schematic diagram of the negative current input of the integrator output waveform of this utility model.

[0057] Figure 6 This is a schematic diagram of the comparator circuit of this utility model.

[0058] Figure 7 This is a schematic diagram of the analog switch circuit structure of this utility model.

[0059] Figure 8 This is a schematic diagram of the constant current source circuit structure of this utility model.

[0060] Figure 9 This is a schematic diagram of the overall circuit structure of this utility model. Detailed Implementation

[0061] like Figure 1-9 As shown, this utility model includes a threshold circuit, a comparator, an integrator, a shaping circuit, a commutation switch, a synchronization circuit, a positive shaping circuit, a negative shaping circuit, and a constant current source.

[0062] Input current I i The output is connected to an integrator;

[0063] The CP output of the sampling circuit is connected to the shaping circuit;

[0064] The shaping circuit outputs a synchronous circuit;

[0065] Threshold circuit output comparator;

[0066] The commutator is connected to a constant current source, and the output of the commutator is connected to an integrator.

[0067] Comparators include positive comparators and negative comparators;

[0068] Synchronization circuits include positive synchronization circuits and negative synchronization circuits;

[0069] The shaping circuit outputs both a positive synchronization circuit and a positive shaping circuit.

[0070] The integrator outputs a positive comparator and a negative comparator respectively;

[0071] The threshold circuit outputs a positive comparator and a negative comparator respectively;

[0072] The positive comparator and the negative comparator are connected to the positive synchronization circuit and the negative synchronization circuit, respectively;

[0073] The forward synchronization circuit outputs a commutation switch and a forward shaping circuit, respectively;

[0074] The negative synchronization circuit outputs a commutation switch and a negative shaping circuit, respectively;

[0075] The positive shaping circuit and the negative shaping circuit output signals f respectively. o +、f o -;

[0076] The operational stability, temperature stability, and dynamic load-carrying capacity of the constant current source circuit directly affect the conversion accuracy and temperature drift of the I / F converter, making it a crucial component of the I / F converter. The constant current source circuit employs a floating-ground single constant current source reset design, serving as the reset reference current for both the negative and positive channels. The overall application circuit schematic is shown below. Figure 1 As shown.

[0077] As for the circuit principle, the specific solution adopted by this utility model is as follows:

[0078] The working process and working principle of the circuit are described using the negative current input state.

[0079] When there is no current input Figure 1 In the I / F converter, the integrator outputs zero voltage, and both the negative comparator and the negative synchronization circuit output low levels. When a negative current is input, the integrator begins positive integration and enters a charging state, causing the output voltage to rise. When the output voltage reaches the threshold voltage of the subsequent comparator, the comparator flips, and the trigger of the negative synchronization circuit flips accordingly, outputting a counting pulse. Simultaneously, the commutation switch opens, controlling the constant current source circuit to reverse charge the integrator through the commutation switch, entering a reset state. The integrator output voltage begins to decrease. When the integrator output voltage drops below the comparator threshold voltage, the synchronization circuit trigger flips, closing the commutation switch and simultaneously shutting off the counting output. The integrator then resumes the negative current charging process, achieving I / F conversion through this closed-loop cycle. The integral charge of the input current and the integral charge of the reset constant current source are equal in value but opposite in direction. The closed-loop operation of the circuit causes the integrator's output voltage to fluctuate around the threshold. The integral charge of the input current is linearly related to the input current, and the integral charge of the reset current is proportional to the reset time. Therefore, the number of output pulses is proportional to the input current, achieving a linear transformation between input current and output frequency. The working process and principle are the same for positive and negative channel current inputs, except that the integral voltage and the circuit threshold are reversed.

[0080] This invention mainly utilizes the "voltage follower characteristic" of operational amplifiers, with appended... Figure 2According to the "virtual short" principle of op-amps, the voltages of the two input pins in3 and in2 of the op-amp are equal. When a stable power supply voltage is input to pin in3 of the op-amp, the voltage across resistor R2 remains constant at Vin. Therefore, no matter how the external circuit changes, the current flowing through resistor R2 remains constant. The current of the load R3 is equal to the current of resistor R2. So even if the power supply of the load R3 is a variable voltage power supply, the current of the load R3 remains constant, thus achieving the effect of constant current.

[0081] Overall circuit principle: When there is no current input, Figure 1-3 In the I / F converter, the integrator outputs zero voltage, and both the negative comparator and the negative synchronization circuit output a low level.

[0082] When a negative current is input, the circuit integrator begins positive integration and enters the charging state, causing the output voltage to rise. When the output voltage reaches the threshold voltage of the subsequent comparator, the comparator flips, and the negative synchronous circuit trigger flips accordingly, outputting a counting pulse. Simultaneously, the commutation switch opens, controlling the constant current source circuit to reverse charge the integrator through the commutation switch, entering a reset state. The integrator output voltage begins to decrease. When the integrator output voltage drops below the comparator threshold voltage, the synchronous circuit trigger flips, closing the commutation switch and simultaneously shutting off the counting output. The circuit integrator then resumes the negative current charging process, achieving I / F conversion through this closed-loop cycle.

[0083] The integrator includes operational amplifier U1 and capacitor C1;

[0084] Pin 1 of op-amp U1 is grounded, pin 4 is connected to -15V; pin 3 is grounded, pin 2 is split into three paths: one path is grounded through capacitor C1, the second path is connected to current Iin through resistor Rin, and the third path is connected to a constant current source through the FW terminal.

[0085] Pin 6 of op-amp U1 outputs two paths through resistor R1, which are respectively supplied to op-amp U2 and op-amp U3;

[0086] The output terminal of resistor R1 is electrically connected to the bases of transistors Q1 and Q2 respectively;

[0087] The collector of transistor Q1 is connected to +15V through resistor R2;

[0088] The collector of transistor Q2 is grounded through resistor R3;

[0089] The integral charge of the input current and the integral charge of the reset constant current source are equal in value but opposite in direction. The closed-loop operation of the circuit causes the integrator's output voltage to fluctuate around the threshold. The integral charge of the input current Iin is linearly related to the input current Iin, and the integral charge of the reset is proportional to the reset time. Therefore, the number of output pulses is proportional to the input current, achieving a linear transformation between input current and output frequency. The working process and principle are the same for positive and negative channel current inputs, except that the integral voltage and the circuit threshold are reversed.

[0090] The integrator has two states: positive integration and negative integration. When a negative input current is received, it integrates the negative input current, V. OUT The output is in a positive voltage integration state, i.e., in the positive direction of integration. The operational amplifier has a very high input resistance, and the input current flows through R... in The current flows into the integrating capacitor C. Since the non-inverting and inverting inputs of the op-amp are virtually shorted, the inverting input is virtually grounded, increasing the integrator output voltage. When the predetermined threshold is reached, an external constant current source (opposite to the input current) reverse-charges the integrating capacitor (discharging process), causing the integrator output voltage to return below the threshold. This process is called the integration-reset process. This process operates cyclically, achieving high-precision I / F conversion. The integrator's output waveform during operation is shown below. Figure 4 , Figure 5 As shown. The integrator operates in the same way as the forward integration mode, only the integration direction is reversed.

[0091] like Figure 6 The comparator circuit includes a comparator circuit and a threshold circuit that are electrically connected. The threshold circuit generates a comparison threshold voltage and consists of a power supply and a proportional resistor. The comparator circuit compares the integrator output signal with the threshold voltage. The comparator periodically flips to identify the input state, providing a control signal to the subsequent synchronization circuit. This control causes the subsequent commutation switch and constant current source to periodically reset, causing the integrator to operate during the integration-reset cycle. The circuit continuously repeats this process in closed-loop operation to achieve I / F conversion.

[0092] For comparator circuits;

[0093] The threshold circuit includes a proportional resistor electrically connected to the ±15V power supply.

[0094] The positive comparator includes an operational amplifier U2 that is electrically connected to the +15V power supply of the threshold circuit.

[0095] The negative comparator includes an operational amplifier U3 that is electrically connected to the -15V power supply of the threshold circuit.

[0096] The input terminals of operational amplifiers U2 and U3, and the output terminal of operational amplifier U1, Vout;

[0097] Several resistors are electrically connected between the output terminals of operational amplifier U2 and operational amplifier U3;

[0098] Operational amplifiers U2 and U3 output levels K+ and K-, respectively;

[0099] The FW terminal of the constant current source is connected to the emitters of transistors Q1 and Q2 through a series capacitor C*4 and a resistor R11; the emitters of transistors Q1 and Q2 are connected to pin 2 of operational amplifier U2 and pin 3 of operational amplifier U3, respectively; the emitters of transistors Q1 and Q2 are grounded through resistor R4.

[0100] Pin 3 of op-amp U2 is connected to +15V through resistor R5; pin 2 of op-amp U3 is grounded through resistor R8.

[0101] The comparator operates as follows: When the input signal is zero, the integrator output Vout is zero, and the outputs K+ and K- of comparators A and B are both low. When a negative current is input, the integrator integrates in the positive direction. When the integrator output voltage Vout is greater than the threshold voltage, comparator A flips, and K+ changes from low to high, controlling the operation of the subsequent synchronization circuit and commutator switch. This shorts the positive constant current source to the current input terminal via the switch. In the design, the reset current is always greater than the input current, so during the output of the negative pulse, the integrator integrates in the reverse direction, causing the circuit to enter the reset state. When the integrator output voltage Vout is less than the preset comparison voltage, K+ changes from high to low, disconnecting the short circuit between the constant current source and the input signal, and the integrator returns to the positive integration state. This cyclical operation achieves I / F conversion.

[0102] like Figure 7 The synchronization circuit includes a positive synchronization circuit and a negative synchronization circuit;

[0103] The positive synchronization circuit includes a D flip-flop U2AZ;

[0104] The negative synchronization circuit includes a D flip-flop U2BZ;

[0105] Pin 1 of the D flip-flop U2AZ is connected to 5V, pin 2 is the input signal, and pin 3 is the input clock signal; pin 3 is connected to the shaping circuit chip U4BZ, which outputs the signal F-.

[0106] Pin 10 of the D flip-flop U2BZ is connected to 5V, pin 12 is the input signal, and pin 11 is the input clock signal; pin 9 is connected to the shaping circuit chip U4AZ, which outputs the signal F+.

[0107] The synchronization circuit employs a mature variable-width triggering method. It utilizes a dual-channel dual D flip-flop. The comparator's periodic flip-flop serves as the input to the synchronization circuit. One output channel controls the on / off state of the subsequent commutation switch, achieving charge balance between the constant current source and the input current. The other channel serves as the output signal for the I / F converter. By counting and performing logic operations on the CLK clock signal, the D flip-flops are triggered and reset.

[0108] The reversing switch, as a switching circuit, includes chip U3Z. Pins 8 and 9 are respectively connected to pin 6 of D flip-flop U2AZ, and pins 1 and 16 are respectively connected to pin 8 of D flip-flop U2BZ; pin 14 is electrically connected to signal FW.

[0109] The working principle of this utility model:

[0110] When a negative current is input,

[0111] D flip-flop U2BZ, i.e. flip-flop B:, when QB=1, is in integral state. At this time, the first switch of the analog switch is open, S1 and D1 are connected, and the com terminal (constant current source output) is grounded.

[0112] At the same time, trigger A: QA=0, QB=1, at this time the analog switch No. 4 is open, S4 and D4 are connected, and H15V is grounded;

[0113] Trigger B: When QB=1 and QB=0, it is in the reset state. At this time, the second switch of the analog switch is open, S2 and D2 are connected, and the COM terminal (constant current source output) is connected to the FW terminal of the integrator.

[0114] At the same time, the D flip-flop U2AZ, i.e., flip-flop A: QA=1, QB=0, at this time, the analog switch No. 3 is opened, S3 and D3 are connected, and the FW terminal is connected to H15V. At this time, a reset current is formed from com to H15V, which charges the integrator in reverse and completes the reset function. The principle of the positive input current is similar to the above principle, except that the direction of the reset current changes to H15V to com terminal.

[0115] The constant current source includes the electrically connected chip U7Z and operational amplifier U8Z;

[0116] Chip U7Z serves as the voltage reference;

[0117] The output of op-amp U8Z is connected to pin 2 of chip U3Z via MOSGQ5Z and transistor Q6Z;

[0118] As Figure 7 Improvements, such as Figure 8 The constant current source includes operational amplifiers U6 and U7, which are electrically connected.

[0119] Op-amp U6 is pre-connected to chip U8; pins 2 and 3 of chip U8 are connected to H+15V voltage; pins 9 and 10 of chip U8 are connected to ground through parallel capacitors C3 and C2, and the other is connected to input pin 30 of op-amp U6; pin 2 of op-amp U6 is grounded through resistor R12, and pin 6 is connected to pin 3 of op-amp U7; pin 6 is connected to pin 2 through resistor R13.

[0120] Pin 2 of op-amp U7 is grounded through sampling resistor RS, pin 6 is electrically connected to pin 2 of MOSGQ3, and pin 1 of MOSGQ3 is grounded through capacitor C*3 and connected to the signal COM terminal;

[0121] Pin 1 of MOSGQ3 is electrically connected to the collector of transistor Q4, pin 3 of MOSGQ3 is connected to the base of transistor Q4, and the emitter of transistor Q4 is connected to the sampling resistor RS through resistor R15.

[0122] Traditional dual constant current source circuits have two actual positive and negative constant current source outputs, but they require a large circuit area, making them unsuitable for miniaturization. They also require more chips and wiring, increasing costs and the risk of circuit problems. Furthermore, the lack of isolation between the front and rear stages means that the circuits can affect each other, impacting circuit performance.

[0123] The single constant current source circuit achieves front-to-back isolation and has the advantages of high precision, low temperature drift, and miniaturization. It can completely replace the traditional dual constant current source circuit and has innovative value.

[0124] Chip U7Z provides a precision voltage reference, op-amp U8Z provides a voltage follower, MOSGQ5Z is used as a current amplification transistor, transistor Q6Z is used as an output transistor, and sampling resistor RS is used for precision sampling.

[0125] A precision voltage reference provides a highly stable reference voltage to the voltage follower. Based on the virtual short principle, the non-inverting and inverting inputs of the operational amplifier are at the same potential. The voltage across the sampling resistor RS is equal to the reference voltage, and the output current IO = VREF / RS. From the above equation, it can be seen that the reference voltage and the sampling resistor determine the magnitude of the output current.

[0126] like Figure 1-9 Example: An I / F converter, specifically an I / F converter using a single constant current source with reset floating ground charge balancing technology. The magnitude of the output reset constant current source determines the I / F converter's scaling factor. Depending on project requirements, in conjunction with the clock input and external precision resistors, a scaling factor adjustment resistor is integrated within the circuit to precisely adjust the scaling factor, meeting range requirements while ensuring accurate scaling. This constant current source circuit offers advantages such as high precision, low temperature drift, and miniaturization, and can completely replace traditional dual constant current source circuits, demonstrating innovative value.

[0127] The positive and negative two-channel I / F conversion uses the same constant current source as the reset reference, which is a high-precision, low-temperature drift single constant current source reset floating ground charge balance technology.

[0128] Synchronization circuits include positive synchronization circuits and negative synchronization circuits;

[0129] The constant current source includes operational amplifiers U6 and U7.

[0130] The op-amp U2 has two outputs at pin 7. One output is connected to 5V through resistor R9, and the other output is connected to pin 2 of chip U4A.

[0131] The op-amp U3 has two outputs at pin 7. One output is connected to 5V through resistor R10, and the other output is connected to pin 12 of chip U4B.

[0132] Chip U4A has three outputs at pin 5: one is connected to chip U5B, two are connected to MOSGM1, and the third is grounded through capacitor C6; pin 6 is electrically connected to MOSGM2; the S terminal of MOSGM1 is connected to the FW terminal, and the D terminal is connected to H+15V; the D terminal of MOSGM2 is connected to the FW terminal, and the S terminal is grounded; chip U5B has an output port F-.

[0133] Chip U4B has three outputs at pin 9: one is connected to chip U5A, two are connected to MOSGM3, and the third is grounded through capacitor C*1; pin 8 is electrically connected to MOSGM4; the S terminal of MOSGM3 is connected to the COM terminal, and the D terminal is connected to the FW terminal; the S terminal of MOSGM4 is connected to the COM terminal, and the D terminal is grounded; chip U5A outputs port F+.

[0134] This utility model is described in detail for the purpose of making the disclosure clearer, and the prior art will not be listed one by one.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. It is obvious to those skilled in the art that multiple technical solutions of this utility model can be combined. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model. All technical contents not described in detail in this utility model are publicly known technologies.

Claims

1. A constant current source circuit, characterized in that: It includes threshold circuits, comparators, integrators, shaping circuits, commutator switches, synchronization circuits, positive shaping circuits, negative shaping circuits, and constant current sources; The integrator is used to connect the input current I. i Output terminal; The shaping circuit is used to connect to the CP output terminal of the sampling circuit; The shaping circuit outputs a synchronous circuit; Threshold circuit output comparator; The commutator is connected to a constant current source, and the output of the commutator is connected to an integrator. Comparators include positive comparators and negative comparators; Synchronization circuits include positive synchronization circuits and negative synchronization circuits; The shaping circuit outputs both a positive synchronization circuit and a positive shaping circuit. The integrator outputs a positive comparator and a negative comparator respectively; The threshold circuit outputs a positive comparator and a negative comparator respectively; The positive comparator and the negative comparator are connected to the positive synchronization circuit and the negative synchronization circuit, respectively; The forward synchronization circuit outputs a commutation switch and a forward shaping circuit, respectively; The negative synchronization circuit outputs a commutation switch and a negative shaping circuit, respectively.

2. The constant current source circuit according to claim 1, characterized in that: The positive shaping circuit and the negative shaping circuit output signals f respectively. o +、f o - 3. The constant current source circuit according to claim 1, characterized in that: The integrator includes operational amplifier U1 and capacitor C1; Pin 1 of op-amp U1 is grounded, and pin 4 is connected to -15V; Pin 3 is grounded, and pin 2 is split into three paths: one path is grounded through capacitor C1, the second path is connected to current Iin through resistor Rin, and the third path is connected to a constant current source through the FW terminal. Pin 6 of op-amp U1 outputs two paths through resistor R1, which are respectively supplied to op-amp U2 and op-amp U3; The output terminal of resistor R1 is electrically connected to the bases of transistors Q1 and Q2 respectively; The collector of transistor Q1 is connected to +15V through resistor R2; The collector of transistor Q2 is grounded through resistor R3.

4. The constant current source circuit according to claim 3, characterized in that: The comparator circuit includes a comparator circuit and a threshold circuit that are electrically connected; the threshold circuit includes a proportional resistor that is electrically connected to the ±15V power supply. The positive comparator includes an operational amplifier U2 that is electrically connected to the +15V power supply of the threshold circuit. The negative comparator includes an operational amplifier U3 that is electrically connected to the -15V power supply of the threshold circuit. The input terminals of operational amplifiers U2 and U3, and the output terminal of operational amplifier U1, Vout; Several resistors are electrically connected between the output terminals of operational amplifier U2 and operational amplifier U3; Operational amplifiers U2 and U3 output levels K+ and K-, respectively; The FW terminal of the constant current source is connected to the emitters of transistors Q1 and Q2 through a series capacitor C*4 and a resistor R11; the emitters of transistors Q1 and Q2 are connected to pin 2 of operational amplifier U2 and pin 3 of operational amplifier U3, respectively; the emitters of transistors Q1 and Q2 are grounded through resistor R4. Pin 3 of op-amp U2 is connected to +15V through resistor R5; pin 2 of op-amp U3 is grounded through resistor R8.

5. The constant current source circuit according to claim 4, characterized in that: The reversing switch, as a switching circuit, includes chip U3Z. Pins 8 and 9 are connected to pin 6 of D flip-flop U2AZ, and pins 1 and 16 are connected to pin 8 of D flip-flop U2BZ. Pin 14 is electrically connected to signal FW.

6. The constant current source circuit according to claim 5, characterized in that: The constant current source includes operational amplifiers U6 and U7. The op-amp U2 has two outputs at pin 7. One output is connected to 5V through resistor R9, and the other output is connected to pin 2 of chip U4A. The op-amp U3 has two outputs at pin 7. One output is connected to 5V through resistor R10, and the other output is connected to pin 12 of chip U4B. Chip U4A has three outputs at pin 5: one is connected to chip U5B, two are connected to MOSGM1, and the third is grounded through capacitor C6; pin 6 is electrically connected to MOSGM2. The S terminal of MOSGM1 is connected to the FW terminal, and the D terminal is connected to H+15V; The drain (D) terminal of MOSGM2 is connected to the ground (FW) terminal, and the source (S) terminal is grounded; the output port of chip U5B is F-. Chip U4B has three outputs at pin 9: one is connected to chip U5A, two are connected to MOSGM3, and the third is grounded through capacitor C*1; pin 8 is electrically connected to MOSGM4. The S terminal of MOSGM3 is connected to the COM terminal, and the D terminal is connected to the FW terminal; the S terminal of MOSGM4 is connected to the COM terminal, and the D terminal is grounded; the output port of chip U5A is F+.

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