Chip packaging structure based on embedded substrate and electronic equipment thereof

Abstract

The utility model provides a chip packaging structure based on an embedded substrate and an electronic device thereof, and the packaging structure comprises a substrate which is provided with a groove and is used for installing a non-filter chip; the at least one non-filter chip is arranged in the groove of the substrate, is electrically connected with the substrate, and is fixed in the groove through curing glue; the solder mask layer is formed above the substrate and the curing glue, and a solder mask opening is formed in the solder mask layer; the at least one filter chip is electrically connected with the substrate through the salient points in the solder resist openings, and a cavity structure is formed below the filter chip; and the packaging layer covers the solder mask layer and the at least one filter chip so as to cover the area of the whole substrate.

Description

Technical Field

[0001] This utility model generally relates to chip packaging structures, and more specifically to a radio frequency filter chip packaging structure based on an embedded substrate and an electronic device having the packaging structure. Background Technology

[0002] Surface acoustic wave (SAW) filters are filtering devices that utilize the piezoelectric effect and the physical properties of surface acoustic wave propagation. They have been widely used in wireless communication systems to filter out signals outside of specific frequencies. SAW filters are characterized by their small size and high performance.

[0003] The working principle of a SAW filter is that sound waves propagate on the surface of the interdigital transducer (IDT) of the SAW filter. Therefore, a cavity structure must be ensured on the surface of the IDT; otherwise, the transmission of sound waves will be affected, thus affecting product performance. Therefore, there are special requirements for the packaging of SAW filters.

[0004] The current industry standard is to first package the filter devices at the wafer level, creating cavities for each filter device on the wafer, and then package the filter devices into the RF module chip. This technology has the disadvantages of large area and high cost. Utility Model Content

[0005] This invention achieves a unique structure where the bottom of the filter device has a cavity, while the bottom of the non-filter device is filled with protective material. This also significantly reduces the overall area of ​​the RF module chip.

[0006] One aspect of this utility model discloses a chip packaging structure based on an embedded substrate, comprising: a substrate having a recess for mounting a non-filter chip; at least one non-filter chip disposed within the recess of the substrate, electrically connected to the substrate, and fixed within the recess by a curing adhesive; a solder resist layer formed above the substrate and the curing adhesive, and having solder resist openings; at least one filter chip electrically connected to the substrate through bumps in the solder resist openings, and having a cavity structure formed below it; and an encapsulation layer covering the solder resist layer and the at least one filter chip to cover the entire area of ​​the substrate.

[0007] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the packaging layer includes a dry film layer and a molding compound layer.

[0008] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the packaging layer includes a black film layer.

[0009] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein a transducer is disposed at the lower part of the at least one filter chip.

[0010] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the height of the cavity is configured in the range of 1-100 μm.

[0011] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the bumps are configured to include tin-coated copper pillars or pure tin balls.

[0012] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the dry film is configured to include a polyester film and a photosensitive adhesive layer.

[0013] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the at least one non-filter chip is configured to include a power amplifier, a low-noise amplifier, or a radio frequency switch chip.

[0014] One aspect of this invention provides a chip packaging structure based on an embedded substrate, wherein the black film is configured to be bonded to the solder resist layer and the at least one filter chip under a low pressure of 0.2 MPa.

[0015] One aspect of this invention provides an electronic device configured to have a chip package structure according to any of the preceding aspects. Attached Figure Description

[0016] Figure 1 This is a schematic diagram showing the structure of a non-filter device embedded in the inner layer of a substrate according to an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram showing the structure of a packaged filter device according to an embodiment of the present invention;

[0018] Figure 3 This is a flowchart illustrating the chip packaging process according to an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the formation process of the embedded substrate according to an embodiment of the present invention; and

[0020] Figure 5 This is a schematic diagram of the packaging process of a filter chip module based on an embedded substrate according to an embodiment of the present invention. Detailed Implementation

[0021] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “coupled,” “connected,” and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are physically in contact with each other. The terms “transmit,” “receive,” and “communicate,” and their derivatives cover both direct and indirect communication. The terms “comprise,” “include,” and their derivatives refer to, but are not limited to, those including, those including, those including, those including. The term “or” is inclusive, meaning and / or. The phrase “associated with,” and its derivatives refer to, including, being contained within, interconnected, containing, being included in, being connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposed, proximate, bound or bound to, having, having attributes, having a relationship or being related to, etc. The term “controller” refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0022] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0023] In this patent document, the application combination of modules and the hierarchical division of sub-modules are for illustrative purposes only. Without departing from the scope of this disclosure, the application combination of modules and the hierarchical division of sub-modules can be in different ways.

[0024] Figure 1 This is a schematic diagram showing the structure of a non-filter device embedded in the inner layer of a substrate according to an embodiment of the present invention.

[0025] like Figure 1As shown, a recess for mounting a non-filter chip is formed in the PCB substrate. The non-filter chip is disposed in the recess and electrically connected to the outside through pre-fabricated circuitry within the recess. The non-filter chip is electrically connected to the substrate below by aligning and soldering with pre-made pads on the substrate. Furthermore, a curing adhesive is disposed on the outside of the non-filter chip to fix it to the substrate. A solder resist layer may also be disposed above the curing adhesive layer. The solder resist layer has multiple solder resist openings for soldering. The solder resist layer may be configured to include structures such as solder resist ink, DAF film, insulating tape, epoxy resin film, phenolic resin film, polyimide film, or liquid crystal polymer film.

[0026] Among them, the non-filter chip can be configured as a power amplifier, low-noise amplifier, RF switch chip, or other types of chip.

[0027] Figure 2 This is a schematic diagram showing the structure of a packaged filter device according to an embodiment of the present invention.

[0028] refer to Figure 2 Within the openings of the solder mask layer, bumps are configured to create electrical connections between the filter chip and the substrate. According to embodiments of the present invention, the bumps can be formed using a metallic material, such as tinned copper pillars or pure tin balls.

[0029] The filter chip is connected to the bump via a flip-chip method. A cavity structure exists between the filter chip and the solder mask layer to accommodate an interdigital transducer disposed beneath the filter chip. The height of the cavity structure is configured to be within the range of 1-100 μm.

[0030] A dry film may also be disposed on the upper part and sides of the filter chip, wherein the dry film is configured to be formed on the upper part and sides of the filter chip by full-surface lamination to block electroplating and etching, and to fix and protect the filter chip. The dry film may be configured to comprise a polyester film, which is configured to have low film flowability so that the film does not penetrate into the cavity structure formed between the filter chip and the substrate during the lamination process.

[0031] According to an embodiment of the present invention, a molding compound layer may also be disposed above the dry film layer. The molding compound layer is configured to be formed using a molding compound, wherein the molding compound is configured to include an epoxy resin film. The molding compound layer is formed on the dry film layer by a compression molding molding process.

[0032] Figure 1 and Figure 2An encapsulation structure based on an embedded substrate process according to an embodiment of the present invention is shown. However, the above embodiments are merely examples, and those skilled in the art can make corresponding modifications without departing from the scope of the present invention. For example, a filter chip can be encapsulated using a black film process to replace the structure of a dry film layer and a molding compound. The black film is configured as a resin material with filler and is configured to have low film flowability.

[0033] Figure 3 This is a flowchart illustrating the chip packaging process according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the formation process of the embedded substrate according to an embodiment of the present invention; and Figure 5 This is a schematic diagram of the packaging process of a filter chip module based on an embedded substrate according to an embodiment of the present invention.

[0034] refer to Figure 3 In step S301, a basic substrate is provided, and pre-fabricated routes are formed on the substrate, wherein the substrate is configured as a multilayer metal substrate for electrically connecting the chip pins inside the package to the outside of the package module.

[0035] In step S302, a groove is formed on the substrate using a laser or etching process.

[0036] In step S303, the non-filter chip is placed in the recess and electrically connected. In the structure formed in step S303, there is no cavity between the non-filter chip and the substrate. (Reference) Figure 4 In the embodiments of this utility model, an example of a non-filter chip is provided, but those skilled in the art should understand that it may include different numbers of filter chips.

[0037] In step S304, curing adhesive is injected to fix the non-filter chip in the groove to complete the filling of the groove.

[0038] In step S305, curing adhesive is injected and the substrate is ground to expose the substrate, and the circuit on the substrate is further fabricated to complete the fabrication of the embedded substrate.

[0039] refer to Figure 4According to an embodiment of this utility model, when the curing adhesive is injected, the curing adhesive fills the groove and also covers the entire upper surface of the substrate. Once the curing adhesive has cured, a grinding process is used to remove the cured adhesive from the upper surface of the substrate to expose the substrate. Furthermore, circuit fabrication is further performed on the ground substrate. A solder resist layer is formed on the substrate with the completed circuit fabrication, and solder resist openings are formed in the solder resist layer to provide contacts for forming electrical connections with the chips on the upper part of the substrate. The openings are configured to include at least one contact corresponding to a bump of a filter chip within one opening.

[0040] In step S306, a filter chip is provided, the filter chip having bumps for electrical connection with an embedded substrate, wherein the bumps can be configured to be formed by tinned copper pillars or pure tin balls. (Reference) Figure 5 In the embodiments of this utility model, an example of two filter chips (i.e., filter chip 1 and filter chip 2) is provided, but those skilled in the art should understand that different numbers of filter chips may be included.

[0041] In step S307, the filter chip is flip-chip soldered onto the embedded substrate using surface mount technology (SMT).

[0042] In step S308, a dry film layer is attached to the surface of the filter chip (e.g., by full-surface lamination). Attaching the dry film layer to the surface of the filter chip creates a cavity structure between the bottom of the filter chip and the embedded substrate. (Reference) Figure 5 The height of the cavity structure is configured to be in the range of 1-100 μm. The dry membrane has low membrane fluidity to prevent membrane permeation into the cavity structure.

[0043] In step S309, a molding compound is formed on the surface of the dry film layer using a compression molding process. The molding compound is configured to include an epoxy resin layer to provide protection for the packaged chip. During the formation of the epoxy resin layer, low-pressure molding is used, with pressure parameters controlled between 0.6 and 1.0 MPa and a temperature set between 150 and 175°C. This prevents the epoxy resin layer from penetrating into the dry film layer and ensures the reliable formation of the cavity structure required by the filter chip.

[0044] Although this invention illustrates the formation of the dry film layer and molding layer for encapsulation via steps S308 and S309, those skilled in the art will understand that the module can be encapsulated using a black film with low film flowability. The black film layer covers the solder resist layer and the at least one filter chip, thus covering the entire area of ​​the substrate. The black film is attached to the substrate using a low-pressure molding process; preferably, it is attached to the solder resist layer and the at least one filter chip using a low-pressure bonding process of 0.2 MPa.

[0045] In step S310, the module is laser-marked and cut to complete the module packaging.

[0046] According to embodiments of this invention, by combining an embedded substrate process, non-filter components that are difficult to process are embedded inside the substrate for filling and protection, while filter components are placed on the outer side of the substrate for overall film coating. Finally, a low-pressure molding process is used for compression molding to ensure the reliability of the filter chip bumps. Simultaneously, embedding non-filter devices into the inner layer of the substrate significantly reduces the planar area of ​​the RF module chip, making the product more competitive. Furthermore, by forming grooves to load the non-filter chips and encapsulating them with curing adhesive, the process is simplified, eliminating the need to consider the rearrangement of circuitry for the non-filter chip portion. Moreover, the stress distribution in the substrate can be adjusted by controlling the grooves and the curing adhesive.

[0047] This invention also provides an electronic device, including the above-mentioned chip packaging structure based on an embedded substrate. By adopting this packaging structure, the non-filter chip is fixed inside the substrate for packaging, thereby reducing the packaging area and lowering the cost.

[0048] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0049] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined solely by the claims.

Claims

1. A chip packaging structure based on an embedded substrate, characterized in that, include: A substrate having recesses for mounting non-filter chips; At least one non-filter chip is disposed in a groove of a substrate, forms an electrical connection with the substrate, and is fixed in the groove by a curing adhesive. A solder resist layer is formed over the substrate and the cured adhesive, and is provided with solder resist openings; At least one filter chip, which is electrically connected to a substrate through bumps in a solder mask opening, and has a cavity structure formed beneath it; and An encapsulation layer covers the solder resist layer and the at least one filter chip to cover the entire area of ​​the substrate.

2. The chip packaging structure according to claim 1, characterized in that, The encapsulation layer includes a dry film layer and a molding layer.

3. The chip packaging structure according to claim 1, characterized in that, The encapsulation layer includes a black film layer.

4. The chip packaging structure according to claim 1, characterized in that, A transducer is provided at the bottom of the at least one filter chip.

5. The chip packaging structure according to claim 1, characterized in that, The height of the cavity is configured to be in the range of 1 to 100 μm.

6. The chip packaging structure according to claim 1, characterized in that, The bumps are configured to include tinned copper pillars or pure tin balls.

7. The chip packaging structure according to claim 2, characterized in that, The dry film is configured to include a polyester film and a photosensitive adhesive layer.

8. The chip packaging structure according to claim 1, characterized in that, The at least one non-filter chip is configured to include a power amplifier, a low-noise amplifier, or an RF switch chip.

9. The chip packaging structure according to claim 3, characterized in that, The black film layer is configured to be bonded to the solder mask layer and the at least one filter chip under low pressure of 0.2 MPa.

10. An electronic device, characterized in that, The electronic device is configured to have a chip package structure according to any one of claims 1-9.

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