Performance testing device for analog-to-digital converter

Abstract

The utility model discloses a performance testing device for an analog-to-digital converter. The device comprises a power supply module, a voltage regulation module, a signal generation and control module and a test execution module. The power supply module provides a direct current power supply, and the voltage regulation module regulates voltage through the DC / DC converter and the low dropout linear regulator. The signal generation and control module integrates a DAC, an MCU and an ADC, realizes closed-loop control through an SPI interface, and accurately adjusts the power supply voltage. The test execution module uses the transistor to control the power supply of the chip to be tested. And the data communication module is connected with an upper computer through a USART interface to realize sending of a test command and receiving of data. According to the utility model, through an automatic test process and accurate voltage control, manual operation is reduced, and stability and reliability of performance test are ensured.

Description

Technical Field

[0001] This utility model relates to a performance testing device for analog-to-digital converters, belonging to the field of integrated circuit testing technology. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as the bridge between the analog and digital worlds, and their performance has a decisive impact on the overall system performance. With advancements in digital signal processing technology and increasing demands for system sensitivity, the market requires ADCs to offer higher speeds and greater accuracy. Particularly in fields like mobile communications and image acquisition, ADCs need high sampling rates to process wideband input signals and high resolution to distinguish minute variations. Therefore, ADC performance testing becomes crucial to ensure accuracy under high-speed sampling conditions.

[0003] ADC performance testing is generally divided into two main categories: static testing and dynamic testing. Static testing mainly examines the relationship between analog input and digital output, while dynamic testing focuses on the ADC's performance under AC conditions. These tests not only ensure that the ADC performance meets design specifications and satisfies users' needs for high-quality signal conversion, but the test results also provide a basis for subsequent calibration, further improving product performance and reliability. Chinese patent application number 202010425305.2 discloses an ADC performance testing circuit. This circuit includes a test module and a control module. The test module is responsible for inputting test signals to the chip under test (DUT), storing the generated test data in an array, and then transferring the data to a first storage module. The control module reads the stored test data and processes it to obtain the static and dynamic parameters of the DUT. This technical solution enables effective and reliable automated testing of the ADC's dynamic and static parameters.

[0004] However, traditional ADC testing methods have some drawbacks, including: the need to repeatedly use a multimeter to measure the accuracy of the chip's power supply voltage and the signal generator's output voltage; incomplete test modes, especially when testing ADC dual-channel alternating acquisition, which requires manual setup of the test circuit, leading to errors and circuit differences between different samples; increased power consumption as the operating frequency of the chip under test or the number of peripherals increases may cause a drop in the power supply voltage, affecting the test results; and a small number of test samples, resulting in low efficiency and being time-consuming and labor-intensive. Summary of the Invention

[0005] The technical problem to be solved by this utility model is to provide a performance testing device for analog-to-digital converters.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A performance testing device for analog-to-digital converters includes a power supply module, a voltage regulation module, a signal generation and control module, and a test execution module. The power supply module provides DC power, and the voltage regulation module includes a DC / DC converter and multiple low-dropout linear regulators. The DC power supply is connected to the DC / DC converter, and the converted voltage is fed into the low-dropout linear regulators for further conversion into the operating voltage.

[0008] The signal generation and control module includes a DAC, an MCU, and an ADC; wherein the MCU is connected to the DAC and the ADC via an SPI interface; the DAC receives control signals from the MCU to output an analog voltage to control the low dropout linear regulator and power the chip under test;

[0009] The test execution module includes multiple transistors, each of which is connected to the chip under test and is opened / closed under the control of the MCU.

[0010] Preferably, the signal generation and control module further includes a signal generator, an SMA connector, and a relay; wherein the MCU is connected to the relay via an SPI interface;

[0011] The signal generator is connected to the relay via the SMA connector to provide the analog signals required for performance testing.

[0012] Preferably, the analog voltage output by the DAC is input to the feedback pin of the low-dropout linear regulator to adjust the output voltage of the low-dropout linear regulator.

[0013] Preferably, the analog voltage is output from the VOUTA pin of the DAC and connected to the feedback pin of the low dropout linear regulator via a current-limiting resistor; the current-limiting resistor and the capacitor together form a low-pass filter to stabilize the voltage of the feedback pin.

[0014] Preferably, the performance testing device further includes a data communication module;

[0015] The data communication module includes a USART interface and a serial communication interface, and the MCU connects to the host computer through the USART interface.

[0016] Preferably, the MCU receives test commands sent by the host computer and transmits the commands to multiple chips under test for testing via serial communication.

[0017] Preferably, the MCU controls the transistor to supply power to the chip under test and acquires the voltage through the ADC to ensure that the output voltage of the DAC reaches the target value required for the test.

[0018] Compared with existing technologies, this invention has the following technical features: First, by using an MCU as the control center, it automates ADC performance testing, which not only reduces manual operation but also improves testing efficiency and accuracy. Second, the device uses the analog voltage output from the DAC to adjust the feedback pin of the LDO and uses the ADC to acquire the voltage output from the LDO, achieving closed-loop control and ensuring the stability of the power supply voltage, effectively solving the problem of repeatedly measuring the power supply voltage in traditional testing methods. Furthermore, through the coordinated operation of the DAC and ADC, the device can accurately control and monitor the power supply voltage, ensuring the accuracy of ADC testing. Finally, this invention communicates with the host computer via a USART interface, enabling the sending of test commands and the receiving of test data, which facilitates data analysis and problem localization. Attached Figure Description

[0019] Figure 1 Structural block diagram of the performance testing device for analog-to-digital converters provided by this utility model;

[0020] Figure 2 This is a circuit schematic diagram of the DC / DC converter in an embodiment of the present invention;

[0021] Figure 3 This is a circuit diagram of the low dropout linear regulator LDO1 in this embodiment of the present invention;

[0022] Figure 4 This is a circuit diagram of the low dropout linear regulator LDO3 in this embodiment of the present invention;

[0023] Figure 5 This is a circuit diagram of the low dropout linear regulator LDO4 in this embodiment of the present invention;

[0024] Figure 6 This is a circuit diagram of the DAC in an embodiment of the present invention;

[0025] Figure 7 This is a circuit schematic diagram of the ADC in an embodiment of the present invention;

[0026] Figure 8 This is a circuit schematic diagram of the MCU in an embodiment of the present invention. Detailed Implementation

[0027] The technical content of this utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] like Figure 1As shown, the performance testing device for analog-to-digital converters provided by this utility model includes a power supply module, a voltage regulation module, a signal generation and control module, a test execution module, and a data communication module. The power supply module provides a 12V DC power supply. The voltage regulation module includes a DC / DC converter and multiple low-dropout linear regulators. The 12V DC power supply from the power supply module is first connected to the DC / DC converter, which converts the 12V voltage to different voltage levels required by the performance testing device. The converted voltage is then fed to the low-dropout linear regulator LDO 1, which further reduces the voltage to 6.1V, supplying the other two low-dropout linear regulators (LDO3 and LDO4). LDO3 and LDO4 then reduce the voltage to a level suitable for the operation of other functional modules.

[0029] In one embodiment of this invention, the signal generation and control module includes a DAC (digital-to-analog converter), an MCU (microcontroller), an ADC (analog-to-digital converter), a signal generator, an SMA connector, and a relay. The DAC receives control signals from the MCU via an SPI interface to output a specific analog voltage. This analog voltage is input to the feedback (FB) pin of the LDO4 to regulate the output voltage of the low-dropout linear regulator, providing a precise power supply voltage to the chip under test (DUT, specifically an analog-to-digital converter in this embodiment). Simultaneously, the MCU controls the ADC via the SPI interface to acquire the voltage at the relay, ensuring that the DAC output voltage reaches the target value required for testing. The signal generator is connected to the relay via an SMA connector to provide the analog signals required for performance testing. These signals are sent to the chip under test for performance testing through the control of the relay and transistor.

[0030] The relay plays a crucial switching role in this performance testing device. Controlled by the MCU, it correctly routes signals during testing. When the MCU, via the SPI interface, controls the ADC to acquire the target voltage at the relay, it sends a command to the chip under test (DUT) via serial port to configure the DUT's ADC function and begin acquisition. After acquisition, the DUT's output signal is sent back to the MCU via serial port, and the MCU then uploads the data to the host computer via UART interface, forming the final test data.

[0031] In one embodiment of this invention, the test execution module includes multiple transistors, each connected to a corresponding chip under test (DUT). Each transistor is switched on / off under the control of the MCU to provide the power required for performance testing of its corresponding DUT. This transistor control ensures that the DUT receives adequate power during performance testing and also allows for switching as needed.

[0032] In one embodiment of this invention, the data communication module includes a USART interface and a serial communication interface, used to implement general synchronous / asynchronous transmit / receive transmission functions and serial communication functions, respectively. These communication interfaces enable the MCU to connect to a host computer and DAC / ADC to send test commands and receive test data.

[0033] Figure 2 This is a circuit diagram of a DC / DC converter according to one embodiment of the present invention. See also... Figure 2 As shown, U1, as a DC-DC converter chip, is responsible for reducing the input voltage VIN to a stable 8V output. Before the circuit starts working, capacitor C2 (BOOT capacitor) provides the startup voltage to the SW pin of U1. Once started, U1 receives the enable signal through the EN pin and begins to regulate the switching state of the SW pin, controlling the current in inductor L1 to store and release energy during the switching cycle. Inductor L1, together with capacitors C8, C9, C10, and C4 at the output, smooths the output voltage and reduces ripple. Schottky diode D5 provides a freewheeling path for inductor L1 when the SW pin is off, ensuring current continuity. The FB pin monitors the output voltage and adjusts the switching frequency or duty cycle of the SW pin through an internal feedback mechanism to maintain a stable 8V output. Capacitors C3, C6, and C7 at the input filter out high-frequency noise, while resistors R4 and R15 are used to set the startup conditions or current sensing. Resistor R5 at the output is also used to set the output voltage or current sensing. Using the circuit described above, efficient voltage conversion can be achieved while maintaining the stability of the output voltage.

[0034] Figure 3 This is a circuit diagram of a low-dropout linear regulator (LDO) 1 in one embodiment of the present invention. The main function of this circuit is to stably convert an 8V input voltage (VIN) to a 6.1V output voltage (VOUT). U3, as a low-dropout linear regulator, receives the input voltage through its INPUT pin and provides a stable output voltage through its OUT pin. Between the INPUT and OUT pins of U3, D2 is a protection diode used to prevent reverse current from damaging the circuit. C17 and C22 are bypass capacitors at the input terminal, used to filter out high-frequency noise in the input voltage to ensure stable operation of the LDO. C11 and C18 are bypass capacitors at the output terminal; they help reduce output voltage ripple and noise, providing a smoother voltage to the load. R7 and R16 are feedback resistors, which form a voltage divider, feeding a portion of the output voltage back to the GND pin of U3 so that LDO 1 can adjust its output according to the feedback voltage, ensuring the stability of the output voltage.

[0035] Figure 4This is a circuit diagram of a low-dropout linear regulator (LDO3) in one embodiment of the present invention. U4, acting as a low-dropout linear regulator, receives the input voltage through the IN1 and IN2 pins and provides a stable output voltage through the OUT1 and OUT2 pins. At the input, C4 and C9 are bypass capacitors used to filter out high-frequency noise in the input voltage, ensuring stable operation of the LDO3. R11 is a resistor connected to the EN pin, used to control the enable state of U4. At the output, C13, C23, and C20 are bypass capacitors for OUT1, used to reduce ripple and noise in the 5.6V output voltage, providing a smoother voltage to the load. R8, R9, and R17 are feedback resistors, forming a voltage divider that feeds a portion of the OUT1 output voltage back to the FB pin, allowing U4 to adjust its output according to the feedback voltage, ensuring output voltage stability. C25 is a capacitor connected to the NR pin, used for noise suppression, improving the circuit's anti-interference capability.

[0036] Figure 5 This is a circuit diagram of a low-dropout linear regulator (LDO4) in one embodiment of the present invention. This circuit converts a 6.1V input voltage into a stable output voltage to power the chip under test. U6, acting as a low-dropout linear regulator, receives the input voltage through the IN1 and IN2 pins and provides a stable output voltage through the OUT1 and OUT2 pins. R20 is a resistor connected to the EN pin, used to control the enable state of U6. C27 and C28 are bypass capacitors at the input, used to filter out high-frequency noise in the input voltage, ensuring stable operation of the LDO regulator. C42 is a capacitor connected to the NR pin, used to reduce regulator noise and improve the circuit's anti-interference capability. At the output, R19 and R23 form a voltage divider, feeding a portion of the output voltage back to the FB pin, allowing U6 to adjust its output based on the feedback voltage, ensuring output voltage stability. C31, C32, and C33 are bypass capacitors at the output terminal, used to reduce output voltage ripple and noise, and provide a smoother voltage to the chip under test.

[0037] Figure 6This is a circuit schematic of the DAC in one embodiment of the present invention. U7, as the DAC chip, is used to convert digital signals to analog signals. It communicates via an SPI interface. The DAC's power supply voltage range is 2.7V to 5.5V. Its VOUTA pin provides an analog voltage output, which is connected to the FB pin of a low-dropout linear regulator to adjust the output voltage of the regulator. R21 is a current-limiting resistor, which, together with C37, forms a low-pass filter to stabilize the voltage at the FB pin. The DAC's reference voltage (VREFIN) pin is connected to an external reference voltage source (VREF1) to provide a precise voltage reference for the DAC. The AVDD pin provides analog power to the DAC, while the DIN, SCLK, and SYNC# pins are used for data input, clock signal, and synchronization signal, respectively. These pins are connected to an external controller (such as an MCU) to perform digital-to-analog signal conversion. C38, C39, and C40 are decoupling capacitors used to filter out power supply noise and ensure stable operation of the DAC.

[0038] Figure 7 This is a circuit schematic of an ADC in one embodiment of the present invention. U16, as the ADC chip, is used to convert analog signals into digital signals. It communicates with the MCU via an SPI interface. The ADC's SCLK, CS, CLK, DGND, AVSS, and REFNO pins are used for clock signal, chip select, analog ground, and reference ground, respectively. The AIN pin is used to receive analog input signals, where AIN0 to AIN7 are eight analog input channels that can receive analog signals from different sensors or signal sources. The REFP0 and REFN0 pins are used to provide a reference voltage, and are decoupled by capacitors C88 and C89 to stabilize the reference voltage. R38, R39, R40, and R41 are resistors used for matching and current limiting. The ADC's DIN, DOUT / DRDY, DVDD, and AVDD pins are used for data input, data output / data preparation, digital power supply, and analog power supply, respectively. VOUT1 to VOUT3 are the voltages that the ADC needs to acquire. C93 to C96 are decoupling capacitors used to filter out power supply noise and ensure stable operation of the ADC.

[0039] Figure 8 This is a circuit schematic of an MCU in one embodiment of the present invention. The MCU includes power supply pins (such as VDD, VSS), ground pin (GND), reset pin (NRST), and boot pin (BOOT0). In addition, it has multiple multi-functional pins that can be configured for different peripheral functions, such as UART interface, SPI interface, I2C interface, ADC, DAC, and timer (TIM). These pins can be configured via software to communicate with or control external devices.

[0040] The performance testing device provided by this utility model operates as follows: After the device is started, the MCU sends a control signal to the DAC via the SPI interface, outputting a preset voltage to the FB pin of the low-dropout linear regulator, thus adjusting the low-dropout linear regulator to output a stable voltage. Once the voltage acquired by the ADC is confirmed to be correct, the MCU controls the transistor to supply power to the chip under test. Simultaneously, the MCU sends a configuration command to the chip under test to start the performance test. After the performance test is completed, the chip under test sends the acquired data back to the MCU via a serial port. The MCU then uploads the data to the host computer for analysis, obtaining the performance test results of the chip under test. This testing process not only improves the efficiency and accuracy of the test but also reduces the need for manual operation, ensuring the reliability and consistency of the test results.

[0041] Compared with existing technologies, the performance testing device provided by this invention utilizes an MCU as the control center, controlling the DAC output a precise voltage via an SPI interface. This voltage is used to adjust the FB pin of the low-dropout linear regulator. The MCU also controls the ADC to acquire the voltage, ensuring the accuracy of the output voltage, thus achieving closed-loop control and a stable output voltage. Furthermore, when the voltage reaches a preset target, the MCU controls the transistor to close, providing a stable power supply to subsequent circuits. This design unifies the testing environment, significantly reduces the complexity of setting up the testing environment, and solves the problem of repeatedly measuring the supply voltage. Because the MCU in this invention can repeatedly check the accuracy of the power supply to the chip under test, ensuring that the voltage is normal before starting ADC-related performance testing. Regarding the testing process, this invention can connect to a host computer via a USART interface to receive test commands sent by the host computer. After receiving the command, the MCU transmits the command to multiple chips under test via serial communication to execute the test. This design simplifies the testing steps, enhances the reproducibility of the testing environment, and thus significantly improves the efficiency and stability of performance testing.

[0042] Furthermore, this invention uses an MCU as the main control chip, significantly reducing the workload of testing personnel. Testing personnel can be freed from tedious manual testing and concentrate their energy on data analysis and problem localization, effectively saving labor costs. Utilizing its high reproducibility, this invention can test multiple samples in a short time, which greatly improves testing efficiency.

[0043] The performance testing device for analog-to-digital converters provided by this utility model has been described in detail above. Any obvious modifications made to this utility model by those skilled in the art without departing from its essential content will constitute an infringement of the patent rights of this utility model and will incur corresponding legal liability.

Claims

1. A performance testing device for analog-to-digital converters, characterized in that... It includes a power supply module, a voltage regulation module, a signal generation and control module, and a test execution module; among which, The power module is used to provide DC power. The voltage regulation module includes a DC / DC converter and multiple low-dropout linear regulators. The DC power is connected to the DC / DC converter, and the converted voltage is sent to the low-dropout linear regulators for further conversion into the operating voltage. The signal generation and control module includes a DAC, an MCU, and an ADC; wherein the MCU is connected to the DAC and the ADC via an SPI interface; the DAC receives control signals from the MCU to output an analog voltage to control the low dropout linear regulator and power the chip under test; The test execution module includes multiple transistors, each of which is connected to the chip under test and is opened / closed under the control of the MCU.

2. The performance testing device as described in claim 1, characterized in that... The signal generation and control module also includes a signal generator, an SMA connector, and a relay; wherein the MCU is connected to the relay via GPIO. The signal generator is connected to the relay via the SMA connector to provide the analog signals required for performance testing.

3. The performance testing device as described in claim 2, characterized in that: The analog voltage output from the DAC is input to the feedback pin of the low-dropout linear regulator to adjust the output voltage of the low-dropout linear regulator.

4. The performance testing device as described in claim 3, characterized in that: The analog voltage is output from the VOUTA pin of the DAC and connected to the feedback pin of the low dropout linear regulator through a current-limiting resistor (R21). The current-limiting resistor and the capacitor (C37) together form a low-pass filter to stabilize the voltage of the feedback pin.

5. The performance testing device as described in claim 1, characterized in that... It also includes a data communication module; The data communication module includes a USART interface and a serial communication interface, and the MCU connects to the host computer through the USART interface.

6. The performance testing apparatus as described in claim 5, characterized in that: The MCU receives test commands sent by the host computer and transmits the commands to multiple chips under test for testing via serial communication.

7. The performance testing device as described in claim 1, characterized in that: The MCU controls the transistor to supply power to the chip under test and collects voltage through the ADC to ensure that the output voltage of the DAC reaches the target value required for the test.

8. The performance testing apparatus as described in claim 1, characterized in that... The SW pin of the DC / DC converter is connected to a BOOT capacitor (C2) to provide the startup voltage.

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