Packaging substrate, LVDS buffer chip packaging structure and resistor packaging structure

Abstract

The utility model relates to the technical field of packaging substrates, and discloses a packaging substrate, an LVDS (Low Voltage Differential Signaling) buffer chip packaging structure and a resistor packaging structure, the packaging substrate comprises a PCB (Printed Circuit Board), a plurality of first bonding pad groups, a plurality of second bonding pad groups and second lead bonding pads connected with the second bonding pad groups; the first bonding pad group comprises a first bonding pad and a second bonding pad; the first bonding pad group is suitable for being connected with an enabling pin group or a power supply pin group of the LVDS buffer chip; the second bonding pad group comprises a third bonding pad and a fourth bonding pad; the second bonding pad group is suitable for being connected with a signal pin group or a resistor of the LVDS buffer chip; the distance between the third bonding pad and the fourth bonding pad in the second bonding pad group is smaller than the distance between the first bonding pad and the second bonding pad in the first bonding pad group; the second lead bonding pad is suitable for being connected with an LVDS signal line. Compared with the prior art, the direct connection between the input end and the output end of the LVDS signal line can be realized, and the detection efficiency of signals and the accuracy of detection results are improved.

Description

Technical Field

[0001] This utility model relates to the field of packaging substrate technology, specifically to a packaging substrate, an LVDS buffer chip packaging structure, and a resistor packaging structure. Background Technology

[0002] LVDS buffer chips, as an indispensable component of display circuits, are widely used in various display modules to protect and isolate the display screen. During circuit design and debugging, if an anomaly is detected in the LVDS signal, and analysis of the problem is required, the buffer chip becomes a major obstacle. It's necessary to first check the buffer chip's input and configuration, then measure and analyze the chip's input and output LVDS signals. If the cause of the problem cannot be identified, the buffer chip needs to be removed to directly connect the LVDS signal. However, because the chip has already disconnected the LVDS signal input and output, it's difficult to directly connect the LVDS signal line for debugging.

[0003] The commonly used method is to set flying wires on the pads of the packaged buffer chip pins to connect the input and output of the LVDS signal. This method is time-consuming and labor-intensive, with low detection efficiency. At the same time, the flying wires may also break or have poor contact, which will lead to inaccurate detection results.

[0004] Therefore, a solution is needed that allows for easier removal of the buffer chip during testing, enabling direct connection of the input and output of the LVDS signal lines to improve testing efficiency. Utility Model Content

[0005] In view of this, the present invention provides a packaging substrate, an LVDS buffer chip packaging structure, and a resistor packaging structure to solve the problem in related technologies that it is difficult to achieve direct connection between the input and output of LVDS signal lines when detecting LVDS signals, resulting in low detection efficiency and poor accuracy.

[0006] In a first aspect, this utility model provides a packaging substrate for packaging LVDS buffer chips or resistors, the packaging substrate comprising:

[0007] PCB board, including a first direction and a second direction that are perpendicular to each other;

[0008] Several first pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each first pad group includes a first pad and a second pad disposed opposite to each other in a first direction; the first pad groups are adapted to connect to the enable pin group or the power pin group of the LVDS buffer chip.

[0009] Several second pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each second pad group includes a third pad and a fourth pad disposed opposite to each other in a first direction; the second pad groups are adapted to connect the signal pin group or resistor of the LVDS buffer chip.

[0010] The first pad group and the second pad group are arranged separately in the second direction of the PCB board; the second pad group is located between multiple first pad groups.

[0011] The distance between the third and fourth pads in the second pad group is less than the distance between the first and second pads in the first pad group;

[0012] Several second lead pads are provided, with the second lead pads located on the side of the third pad facing away from the fourth pad or on the side of the fourth pad facing away from the third pad; each second lead pad is connected to the third pad or the fourth pad; the second lead pads are adapted to connect the first LVDS signal line and the second LVDS signal line.

[0013] The packaging substrate provided by this utility model, by setting several second pad groups, wherein the distance between the third and fourth pads in the second pad group is less than the distance between the first and second pads in the first pad group, allows the packaging substrate to be used for both packaging LVDS buffer chips and packaging resistors. When it is necessary to test the LVDS signal, it is only necessary to remove the LVDS buffer chip and package the resistor in the second pad group to achieve direct connection between the input and output terminals of the LVDS signal line. The operation is convenient and can improve the detection efficiency and accuracy of the detection results of LVDS signals.

[0014] In one alternative implementation, the first pad group includes a first sub-pad group, a second sub-pad group, a seventh sub-pad group, and an eighth sub-pad group; the seventh sub-pad group is adapted to connect to the enable pin group of the LVDS buffer chip; the first sub-pad group, the second sub-pad group, and the eighth sub-pad group are adapted to connect to the three power supply pin groups of the LVDS buffer chip.

[0015] The second pad group includes a third sub-pad group, a fourth sub-pad group, a fifth sub-pad group, and a sixth sub-pad group; the second pad group is suitable for connecting the four signal pin groups or four resistors of the LVDS buffer chip;

[0016] The first pad group and the second pad group are arranged in the following order in the second direction: first sub-pad group, second sub-pad group, third sub-pad group, fourth sub-pad group, fifth sub-pad group, sixth sub-pad group, seventh sub-pad group, and eighth sub-pad group.

[0017] In one optional embodiment, the distance between the first pad and the second pad in the first pad group is 7.0 mm to 8.0 mm;

[0018] The distance between the third and fourth pads in the second pad group is 0.6mm to 0.8mm.

[0019] The packaging substrate provided by this utility model has a distance of 7.0mm to 8.0mm between the first and second pads in the first pad group and a distance of 0.6mm to 0.8mm between the third and fourth pads in the second pad group. This allows the packaging substrate to be used for both packaging LVDS buffer chips and resistors. When it is necessary to test the LVDS signal, it is only necessary to remove the LVDS buffer chip and package the resistor in the second pad group to achieve direct connection between the input and output terminals of the LVDS signal line. This is convenient to operate and can improve the detection efficiency and accuracy of the detection results.

[0020] In one alternative implementation, the distance between the first pad and the second pad in the first pad group is 7.62 mm;

[0021] The distance between the third and fourth pads in the second pad group is 0.76 mm.

[0022] In one alternative implementation, the lengths of the first pad and the second pad are greater than or equal to the pad lengths of the LVDS buffer chip.

[0023] The lengths of the third and fourth pads are greater than or equal to the length of the resistor pads.

[0024] The packaging substrate provided by this utility model has a first pad and a second pad with lengths greater than or equal to the pin length of the LVDS buffer chip; and a third pad and a fourth pad with lengths greater than or equal to the pin length of the resistor. This makes the packaging of the LVDS buffer chip and the resistor more stable, thereby improving the packaging reliability.

[0025] In one optional embodiment, the lengths of the first pad and the second pad are 2.0 mm to 2.2 mm;

[0026] The lengths of the third and fourth pads are 5mm to 6mm.

[0027] In one alternative embodiment, the packaging substrate further includes:

[0028] Several first lead pads, each first lead pad being located on the side of the first pad facing away from the second pad or on the side of the second pad facing away from the first pad; each first lead pad is connected to either the first pad or the second pad.

[0029] Secondly, this utility model provides an LVDS buffer chip packaging structure for connecting an LVDS buffer chip between a first LVDS signal line and a second LVDS signal line. The LVDS buffer chip packaging structure includes the packaging substrate and the LVDS buffer chip provided in the first aspect.

[0030] The LVDS buffer chip includes several enable pin groups, several power pin groups, and several signal pin groups; each enable pin group includes a first enable pin and a second enable pin that are arranged opposite to each other; each power pin group includes a first power pin and a second power pin that are arranged opposite to each other; each signal pin group includes a first signal pin and a second signal pin that are arranged opposite to each other.

[0031] The first enable pin and the first power supply pin are located on the first pad; the second enable pin and the second power supply pin are located on the second pad; the first signal pin is located on the third pad; and the second signal pin is located on the fourth pad.

[0032] The second lead pad connects to the first LVDS signal line and the second LVDS signal line;

[0033] The LVDS buffer chip is connected to the first LVDS signal line and the second LVDS signal line through a packaging substrate.

[0034] The LVDS buffer chip packaging structure provided by this utility model connects the enable pin group, power pin group, and signal pin group of the LVDS buffer chip to the first LVDS signal line and the second LVDS signal line respectively on the first pad group and the second pad group of the packaging substrate. This can improve the stability and reliability of the LVDS buffer chip packaging structure and enable the LVDS buffer chip to achieve the buffering function.

[0035] Thirdly, this utility model provides a resistor packaging structure for directly connecting a first LVDS signal line and a second LVDS signal line. The resistor packaging structure includes the packaging substrate provided in the first aspect and a plurality of resistors.

[0036] Each resistor is packaged on a second set of pads;

[0037] Each resistor includes a first resistor pin and a second resistor pin; the first resistor pin is located on a third pad; the second resistor pin is located on a fourth pad;

[0038] The second lead pad connects to the first LVDS signal line and the second LVDS signal line;

[0039] The resistor directly connects the first LVDS signal line and the second LVDS signal line through the package substrate.

[0040] The resistor packaging structure provided by this utility model encapsulates the resistor on the second pad group of the packaging substrate. The resistor can be directly connected to the first LVDS signal line and the second LVDS signal line through the second pad group and the second lead pad, thereby realizing the direct connection between the input end and the output end of the LVDS signal line. It is convenient to operate and can improve the detection efficiency and the accuracy of the detection results.

[0041] In one alternative implementation, the resistor is a 0402 resistor; the resistance value is 0 to 1 MΩ. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this utility model, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a packaging substrate for related technologies.

[0044] Figure 2 This is a schematic diagram of the structure of a packaging substrate according to an embodiment of the present utility model.

[0045] Figure 3 This is a schematic diagram of the connection method between a packaging substrate and an LVDS buffer chip or resistor according to an embodiment of the present invention.

[0046] Figure 4 This is a schematic diagram of the structure of an LVDS buffer chip according to an embodiment of the present invention.

[0047] Figure 5 This is a schematic diagram of an LVDS buffer chip packaging structure according to an embodiment of the present utility model.

[0048] Figure 6 This is a schematic diagram of a resistor packaging structure according to an embodiment of the present utility model.

[0049] Figure label:

[0050] 1. Pad; 2. Flying lead; 111. First pad; 112. Second pad; 121. Third pad; 122. Fourth pad; 130. PCB board; 141. First lead pad; 142. Second lead pad; 200. LVDS buffer chip; 211. First enable pin; 212. Second enable pin; 221. First power supply pin; 222. Second power supply pin; 231. First signal pin; 232. Second signal pin; 300. Resistor. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.

[0052] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of this utility model. Various structural schematic diagrams according to embodiments of this utility model are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this utility model, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0053] LVDS buffer chips, as an indispensable component of display circuits, are widely used in various display modules to protect and isolate the display screen. During circuit design and debugging, if an anomaly is detected in the LVDS signal, and analysis of the problem is required, the buffer chip becomes a major obstacle. It's necessary to first check the buffer chip's input and configuration, then measure and analyze the chip's input and output LVDS signals. If the cause of the problem cannot be identified, the buffer chip needs to be removed to directly connect the LVDS signal. However, because the chip has already disconnected the LVDS signal input and output, it's difficult to directly connect the LVDS signal line for debugging.

[0054] Currently, commonly used methods in related technologies include... Figure 1 As shown, by setting a flying wire 2 on the pad 1 of the packaged buffer chip pin, the input and output of the LVDS signal are connected. This method is time-consuming and labor-intensive, with low detection efficiency. At the same time, the flying wire may also break or have poor contact, which will lead to inaccurate detection results.

[0055] like Figure 2 As shown, this embodiment provides a packaging substrate for packaging LVDS buffer chips or resistors. The packaging substrate includes:

[0056] PCB board 130 includes a first direction and a second direction that are perpendicular to each other;

[0057] A plurality of first pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each first pad group includes a first pad 111 and a second pad 112 disposed opposite to each other in a first direction; the first pad group 10 is adapted to connect to the enable pin group or the power pin group of the LVDS buffer chip.

[0058] Several second pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each second pad group includes a third pad 121 and a fourth pad 122 disposed opposite to each other in a first direction; the second pad groups are adapted to connect the signal pin group or resistor of the LVDS buffer chip.

[0059] The first pad group and the second pad group are arranged separately in the second direction of the PCB board; the first pad group is located between multiple second pad groups.

[0060] The distance between the third pad 121 and the fourth pad 122 in the second pad group is less than the distance between the first pad 111 and the second pad 112 in the first pad group;

[0061] Several second lead pads 142 are located on the side of the third pad 121 facing away from the fourth pad 122 or on the side of the fourth pad 122 facing away from the third pad 121; each second lead pad is connected to the third pad 121 or the fourth pad 122; the second lead pads 142 are adapted to connect the first LVDS signal line and the second LVDS signal line.

[0062] In practice, the materials for the first pad group, the second pad group, the first lead pad, and the second lead pad are conductive materials such as copper and tin. The first LVDS signal line and the second LVDS signal line are the input and output terminals of the LVDS signal, respectively. The first direction is the horizontal direction shown in the figure, and the second direction is the vertical direction shown in the figure.

[0063] like Figure 3 As shown, the packaging substrate can be used to package LVDS buffer chips or resistors. Since the size of the resistor is smaller than that of the LVDS buffer chip, and the pin spacing of the resistor is also smaller than that of the LVDS buffer chip, the distance between the third pad 21 and the fourth pad 22 in the second pad group is set to be smaller than the distance between the first pad 11 and the second pad 12 in the first pad group. This allows the third pad 21 and the fourth pad 22 in the second pad group to be used for both packaging LVDS buffer chips and resistors.

[0064] When the packaging substrate is used to package an LVDS buffer chip, the first pad group 10 is adapted to connect the enable pin group or power pin group of the LVDS buffer chip, and the second pad group is adapted to connect the signal pin group of the LVDS buffer chip; when the packaging substrate is used to package a resistor, the second pad group is adapted to connect the resistor, and the resistor achieves direct connection between the first LVDS signal line and the second LVDS signal line through the second pad group and the second lead pad 142.

[0065] The packaging substrate provided by this utility model, by setting several second pad groups, wherein the distance between the third and fourth pads in the second pad group is less than the distance between the first and second pads in the first pad group, allows the packaging substrate to be used for both packaging LVDS buffer chips and packaging resistors. When it is necessary to test the LVDS signal, it is only necessary to remove the LVDS buffer chip and package the resistor in the second pad group to achieve direct connection between the input and output terminals of the LVDS signal line. The operation is convenient and can improve the detection efficiency and the accuracy of the detection results.

[0066] In some alternative implementations, the first pad group includes a first sub-pad group, a second sub-pad group, a seventh sub-pad group, and an eighth sub-pad group; the seventh sub-pad group is adapted to connect to the enable pin group of the LVDS buffer chip; the first sub-pad group, the second sub-pad group, and the eighth sub-pad group are adapted to connect to the three power supply pin groups of the LVDS buffer chip.

[0067] The second pad group includes a third sub-pad group, a fourth sub-pad group, a fifth sub-pad group, and a sixth sub-pad group; the second pad group is suitable for connecting the four signal pin groups or four resistors of the LVDS buffer chip;

[0068] The first pad group and the second pad group are arranged in the following order in the second direction: first sub-pad group, second sub-pad group, third sub-pad group, fourth sub-pad group, fifth sub-pad group, sixth sub-pad group, seventh sub-pad group, and eighth sub-pad group.

[0069] In practical implementation, the structure of the LVDS buffer chip is as follows: Figure 4 As shown, the LVDS buffer chip has a first pin group, an enable pin group, three power pin groups, and four signal pin groups; specifically, from top to bottom, there are two power pin groups, four signal pin groups, one enable pin group, and one power pin group. Each enable pin group includes a first enable pin 211 and a second enable pin 212 positioned opposite each other; each power pin group includes a first power pin 221 and a second power pin 222 positioned opposite each other; each signal pin group includes a first signal pin 231 and a second signal pin 232 positioned opposite each other. The power pin groups can be either power supply pin groups or ground pin groups. For example, in... Figure 4In this configuration, the first power supply pin can be either power supply pin VCC1 or ground pin GND1, the second power supply pin can be either power supply pin VCC2 or ground pin GND2, the first enable pin is EN1, and the second enable pin is EN2.

[0070] When the packaging substrate is used to package an LVDS buffer chip, the seventh sub-pad group is suitable for connecting the enable pin group of the LVDS buffer chip; the first, second, and eighth sub-pad groups are suitable for connecting the three power pin groups of the LVDS buffer chip; and the third, fourth, fifth, and sixth sub-pad groups are respectively connected to the four signal pin groups of the LVDS buffer chip. The arrangement order of the first and second pad groups in the second direction is as follows: first sub-pad group, second sub-pad group, third sub-pad group, fourth sub-pad group, fifth sub-pad group, sixth sub-pad group, seventh sub-pad group, and eighth sub-pad group.

[0071] When the packaging substrate is used to package resistors, four second pad groups are adapted to connect four resistors, and each second pad group is adapted to connect one resistor; the third pad 121 of each signal pin group is connected to the first resistor pin, and the fourth pad 122 of each signal pin group is connected to the second resistor pin. The resistors achieve direct connection between the first LVDS signal line and the second lead pad 142.

[0072] In some alternative implementations, the distance between the first pad and the second pad in the first pad group is 7.0 mm to 8.0 mm, for example, 7.0 mm, 7.5 mm, 7.62 mm, 7.84 mm or 8.0 mm;

[0073] The distance between the third and fourth pads in the second pad group is 0.6mm to 0.8mm, for example, 0.6mm, 0.68mm, 0.7mm, 0.76mm or 0.8mm.

[0074] In practice, the distance between pads mentioned in this embodiment refers to the distance between the opposite edges of two pads.

[0075] The packaging substrate provided in this embodiment has a distance of 7.0mm to 8.0mm between the first and second pads in the first pad group, and a distance of 0.6mm to 0.8mm between the third and fourth pads in the second pad group. This allows the packaging substrate to be used for both packaging LVDS buffer chips and resistors. When testing LVDS signals, it is only necessary to remove the LVDS buffer chip and package the resistor in the second pad group to achieve direct connection between the input and output terminals of the LVDS signal line. This is convenient to operate and can improve the detection efficiency and accuracy of the detection results.

[0076] In some alternative implementations, the distance between the first pad and the second pad in the first pad group is 7.62 mm;

[0077] The distance between the third and fourth pads in the second pad group is 0.76 mm.

[0078] In practical implementation, since the pin pitch of the LVDS buffer chip is 8mm to 10mm and the size of the 0402 resistor is 1mm × 0.5mm, the distance between the first and second pads in the first pad group is set to 7.62mm, and the distance between the third and fourth pads in the second pad group is set to 0.76mm. This can better balance the packaging of the LVDS buffer chip and the resistor, improve packaging reliability, and prevent short circuits.

[0079] In some alternative implementations, the lengths of the first pad and the second pad are greater than or equal to the pad lengths of the LVDS buffer chip;

[0080] The lengths of the third and fourth pads are greater than or equal to the length of the resistor pads.

[0081] The packaging substrate provided in this embodiment has the lengths of the first and second pads being greater than or equal to the pin lengths of the LVDS buffer chip; and the lengths of the third and fourth pads being greater than or equal to the pin lengths of the resistor. This makes the packaging of the LVDS buffer chip and the resistor more robust, thereby improving packaging reliability.

[0082] In some alternative implementations, the lengths of the first pad and the second pad are 2.0 mm to 2.2 mm, for example, 2.0 mm, 2.1 mm, or 2.2 mm;

[0083] The lengths of the third and fourth pads are 5.0mm to 6.0mm, for example, 5.0mm, 5.2mm, 5.4mm, 5.5mm, 5.6mm, 5.8mm or 6.0mm.

[0084] In some alternative embodiments, the packaging substrate further includes:

[0085] A plurality of first lead pads 141 are located on the side of the first pad 111 facing away from the second pad 112 or on the side of the second pad 112 facing away from the first pad 111; each first lead pad is connected to the first pad 111 or the second pad 112.

[0086] In practice, the first lead pad is suitable for connecting the power supply lead, ground lead, or enable lead corresponding to the enable pin and power supply pin of the LVDS buffer chip.

[0087] like Figure 5As shown, this embodiment provides an LVDS buffer chip package structure for connecting an LVDS buffer chip between a first LVDS signal line and a second LVDS signal line. The LVDS buffer chip package structure includes a package substrate and an LVDS buffer chip 200.

[0088] The LVDS buffer chip 200 includes several enable pin groups, several power supply pin groups, and several signal pin groups; each enable pin group includes a first enable pin 211 and a second enable pin 212 arranged opposite to each other; each power supply pin group includes a first power supply pin 221 and a second power supply pin 222 arranged opposite to each other; each signal pin group includes a first signal pin 231 and a second signal pin 232 arranged opposite to each other.

[0089] The first enable pin 211 and the first power supply pin 221 are located on the first pad 111; the second enable pin 212 and the second power supply pin 222 are located on the second pad 112; the first signal pin 231 is located on the third pad 121; and the second signal pin 232 is located on the fourth pad 122.

[0090] The second lead pad 142 connects the first LVDS signal line and the second LVDS signal line;

[0091] The LVDS buffer chip 200 is connected to the first LVDS signal line and the second LVDS signal line through the packaging substrate.

[0092] The LVDS buffer chip packaging structure provided in this embodiment connects the LVDS buffer chip to the first LVDS signal line and the second LVDS signal line by connecting the enable pin group, power pin group and signal pin group of the LVDS buffer chip to the first pad group and the second pad group of the packaging substrate, respectively. This can improve the stability and reliability of the LVDS buffer chip packaging structure and enable the LVDS buffer chip to achieve the buffering function.

[0093] In some implementations, the LVDS buffer chip 200 has the following structure: Figure 4 As shown, the LVDS buffer chip 200 includes one enable pin group, three power supply pin groups, and four signal pin groups; specifically, the arrangement from top to bottom is two power supply pin groups, four signal pin groups, one enable pin group, and one power supply pin group. Each enable pin group includes a first enable pin 211 and a second enable pin 212 positioned opposite each other; each power supply pin group includes a first power supply pin 221 and a second power supply pin 222 positioned opposite each other; each signal pin group includes a first signal pin 231 and a second signal pin 232 positioned opposite each other. The enable pin group or power supply pin group can be either a power supply pin group or an enable pin group. For example, in... Figure 4In this configuration, the first power supply pin can be either power supply pin VCC1 or ground pin GND1, the second power supply pin can be either power supply pin VCC2 or ground pin GND2, the first enable pin is EN1, and the second enable pin is EN2.

[0094] In the LVDS buffer chip package structure, the seventh sub-pad group in the first pad group of the package substrate is adapted to connect the enable pin group of the LVDS buffer chip; the first, second, and eighth sub-pad groups are adapted to connect the three power supply pin groups of the LVDS buffer chip; the third, fourth, fifth, and sixth sub-pad groups are respectively connected to the four signal pin groups of the LVDS buffer chip 200. Specifically, the first enable pin 211 and the first power supply pin 221 are located on the first pad 111; the second enable pin 212 and the second power supply pin 222 are located on the second pad 112; the first signal pin 231 is located on the third pad 121; and the second signal pin 232 is located on the fourth pad 122. The arrangement order of the first and second pad groups in the second direction is, in order, the first sub-pad group, the second sub-pad group, the third sub-pad group, the fourth sub-pad group, the fifth sub-pad group, the sixth sub-pad group, the seventh sub-pad group, and the eighth sub-pad group.

[0095] like Figure 6 As shown, this embodiment provides a resistor package structure for directly connecting the first LVDS signal line and the second LVDS signal line. The resistor package structure includes the above-mentioned package substrate and a plurality of resistors 300.

[0096] Each 300Ω resistor is packaged on a second pad group;

[0097] Each resistor 300 includes a first resistor pin and a second resistor pin; the first resistor pin is located on a third pad; the second resistor pin is located on a fourth pad;

[0098] The second lead pad 142 connects the first LVDS signal line and the second LVDS signal line;

[0099] Resistor 300 directly connects the first LVDS signal line and the second LVDS signal line through the package substrate.

[0100] The resistor packaging structure provided in this embodiment encapsulates the resistor on the second pad group of the packaging substrate. The resistor can be directly connected to the first LVDS signal line and the second LVDS signal line through the second pad group and the second lead pad, thereby realizing the direct connection between the input end and the output end of the LVDS signal line. This is convenient to operate and can improve the detection efficiency and the accuracy of the detection results.

[0101] In one alternative embodiment, resistor 300 is a 0402 resistor; the resistance value of resistor 300 is 0 to 1 MΩ, for example 0, 10 Ω, 50 Ω, 100 Ω, 5 kΩ or 1 MΩ.

[0102] In practice, the resistance value can be set according to actual needs, and this embodiment does not limit it.

[0103] In the description of this specification, the terms "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0104] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention. The protection scope of the present invention is determined by the scope of the appended claims.

Claims

1. A packaging substrate for packaging LVDS buffer chips or resistors, characterized in that, The packaging substrate includes: PCB board, including a first direction and a second direction that are perpendicular to each other; A plurality of first pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each first pad group includes a first pad and a second pad disposed opposite to each other in a first direction; the first pad groups are adapted to connect to the enable pin group or the power pin group of the LVDS buffer chip. A plurality of second pad groups are disposed on the surface of the PCB board and arranged in a second direction of the PCB board; each second pad group includes a third pad and a fourth pad disposed opposite to each other in a first direction; the second pad groups are adapted to connect to the signal pin group of the LVDS buffer chip or the resistor. The first pad group and the second pad group are arranged separately in a second direction on the PCB board; the second pad group is located among multiple first pad groups. The distance between the third pad and the fourth pad in the second pad group is less than the distance between the first pad and the second pad in the first pad group; A plurality of second lead pads are provided, wherein the second lead pads are located on the side of the third pad facing away from the fourth pad or on the side of the fourth pad facing away from the third pad; each second lead pad is connected to the third pad or the fourth pad; the second lead pads are adapted to connect to a first LVDS signal line and a second LVDS signal line.

2. The packaging substrate according to claim 1, characterized in that, The first pad group includes a first sub-pad group, a second sub-pad group, a seventh sub-pad group, and an eighth sub-pad group; the seventh sub-pad group is adapted to connect to the enable pin group of the LVDS buffer chip; the first sub-pad group, the second sub-pad group, and the eighth sub-pad group are adapted to connect to the three power pin groups of the LVDS buffer chip. The second pad group includes a third sub-pad group, a fourth sub-pad group, a fifth sub-pad group, and a sixth sub-pad group; the second pad group is adapted to connect the four signal pin groups of the LVDS buffer chip or the four resistors; The first pad group and the second pad group are arranged in the following order in the second direction: first sub-pad group, second sub-pad group, third sub-pad group, fourth sub-pad group, fifth sub-pad group, sixth sub-pad group, seventh sub-pad group and eighth sub-pad group.

3. The packaging substrate according to claim 1, characterized in that, The distance between the first pad and the second pad in the first pad group is 7.0mm to 8.0mm; The distance between the third and fourth pads in the second pad group is 0.6mm to 0.8mm.

4. The packaging substrate according to claim 3, characterized in that, The distance between the first pad and the second pad in the first pad group is 7.62 mm; The distance between the third and fourth pads in the second pad group is 0.76 mm.

5. The packaging substrate according to claim 1, characterized in that, The lengths of the first and second pads are greater than or equal to the pad lengths of the LVDS buffer chip; The lengths of the third and fourth pads are greater than or equal to the pad length of the resistor.

6. The packaging substrate according to claim 5, characterized in that, The lengths of the first pad and the second pad are 2.0 mm to 2.2 mm; The lengths of the third and fourth pads are 5.0 mm to 6.0 mm.

7. The packaging substrate according to claim 1, characterized in that, The packaging substrate further includes: A plurality of first lead pads, wherein the first lead pads are located on the side of the first pad facing away from the second pad or on the side of the second pad facing away from the first pad; each first lead pad is connected to the first pad or the second pad.

8. An LVDS buffer chip package structure for connecting an LVDS buffer chip between a first LVDS signal line and a second LVDS signal line, characterized in that, The LVDS buffer chip packaging structure includes a packaging substrate as described in any one of claims 1 to 7 and an LVDS buffer chip; The LVDS buffer chip includes several enable pin groups, several power pin groups, and several signal pin groups; each enable pin group includes a first enable pin and a second enable pin arranged opposite to each other; each power pin group includes a first power pin and a second power pin arranged opposite to each other; each signal pin group includes a first signal pin and a second signal pin arranged opposite to each other. The first enable pin and the first power supply pin are located on the first pad; the second enable pin and the second power supply pin are located on the second pad; the first signal pin is located on the third pad; and the second signal pin is located on the fourth pad. The second lead pad connects to the first LVDS signal line and the second LVDS signal line; The LVDS buffer chip is connected to the first LVDS signal line and the second LVDS signal line through the packaging substrate.

9. A resistor package structure for directly connecting a first LVDS signal line and a second LVDS signal line, characterized in that, The resistor packaging structure includes a packaging substrate as described in any one of claims 1 to 7 and a plurality of resistors; Each of the resistors is packaged on a second set of pads; Each resistor includes a first resistor pin and a second resistor pin; the first resistor pin is located on the third pad; the second resistor pin is located on the fourth pad; The second lead pad connects to the first LVDS signal line and the second LVDS signal line; The resistor directly connects the first LVDS signal line and the second LVDS signal line through the packaging substrate.

10. The resistor packaging structure according to claim 9, characterized in that, The resistor is a 0402 resistor; the resistance value of the resistor is 0 to 1 MΩ.

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