Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure, comprising a first trace used for electrical connection; and a first curved layer on the first trace, a top surface of the first curved layer being recessed toward the first trace. The utility model aims to provide a semiconductor packaging structure so as to at least improve the yield of the semiconductor packaging structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor packaging structure. Background Technology

[0002] Figure 1 The diagram shows a perspective view of the fineline structure 1 formed on the dielectric layer 4 and a top view of the stress on the stress line 2. In products with fineline structures, such as the fineline structure 1 with a diameter of several hundred nanometers, it is increasingly easy for defects such as cracks / breaks 5 to occur on the surface along the stress line 2 due to product bending. The electrical problems caused by the break 5 are the main reason for the low yield of the final product.

[0003] The reason for this is that during the bending process of the product, the bending stress 3 will generate the maximum stress on the surface in the middle of the thin wire structure 1. When the maximum stress is greater than the strength of the material of the thin wire structure 1 (such as copper), it will cause fracture 5. The thicker the thin wire structure 1, the more obvious the fracture will be. Utility Model Content

[0004] In view of the problems existing in the related technologies, the purpose of this utility model is to provide a semiconductor packaging structure to at least improve the yield of semiconductor packaging structures.

[0005] To achieve the above objectives, this utility model provides a semiconductor packaging structure, including: a first trace for electrical connection; and a first bending layer located on the first trace, with the top surface of the first bending layer recessed toward the first trace.

[0006] In some embodiments, the strength of the material of the first bending layer is greater than that of the first trace.

[0007] In some embodiments, the material of the first trace is metal.

[0008] In some embodiments, the thickness of the first bending layer is less than that of the first trace.

[0009] In some embodiments, the sidewalls of the first curved layer are aligned with the sidewalls of the first trace.

[0010] In some embodiments, the top surface of the first trace is recessed toward the bottom surface of the first trace.

[0011] In some embodiments, the first curved layer conforms to the top surface of the first trace.

[0012] In some embodiments, the first bending layer has a uniform thickness.

[0013] In some embodiments, the first trace is a nanowire.

[0014] In some embodiments, the semiconductor package structure further includes: a first seed layer; a second seed layer located on the first seed layer, and a first trace located on the second seed layer.

[0015] In some embodiments, the semiconductor package structure further includes: a second trace; a first dielectric layer covering the second trace, wherein the first trace is located above the first dielectric layer.

[0016] In some embodiments, the top surface of the second trace is a plane.

[0017] In some embodiments, the top surface of the second trace is recessed toward the bottom surface of the second trace.

[0018] In some embodiments, the semiconductor package structure further includes a second bending layer disposed between the top surface of the second trace and the first dielectric layer.

[0019] In some embodiments, the second curved layer conforms to the top surface of the second trace.

[0020] In some embodiments, when projected in a top-to-bottom direction, the first trace and the second trace at least partially overlap.

[0021] In some embodiments, the semiconductor package structure further includes: a first dielectric layer covering the first trace and the first bending layer; and a second trace located above the first dielectric layer, the top surface of the second trace being planar.

[0022] In some embodiments, the semiconductor package structure further includes: a carrier; a second dielectric layer located on the carrier, wherein the first dielectric layer is located on the second dielectric layer.

[0023] In some embodiments, the first trace and the second trace are separated by a first dielectric layer.

[0024] A semiconductor package structure includes: a first trace, the top surface of which is recessed toward the bottom surface of the first trace; and a first bending layer located on the first trace, the first bending layer being conformal to the top surface of the first trace.

[0025] In some embodiments, the material of the first bending layer is titanium, tungsten, stainless steel, ceramic, glass, or graphene.

[0026] The beneficial technical effects of this utility model are as follows:

[0027] In the embodiments of this application, the top surface of the first bending layer is recessed downwards, which counteracts the bending stress caused by product bending by redistributing stress and direction, thus solving the problem of trace breakage caused by bending stress. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It is worth noting that, according to industry standard practice, the components are not drawn to scale and are only used for illustrative purposes. In fact, for clarity of discussion, the dimensions of the components can be arbitrarily increased or decreased.

[0029] Figure 1 A three-dimensional diagram of the current fine-line structure is shown.

[0030] Figure 2 The carrier and the second dielectric layer are shown.

[0031] Figure 3 The formation of the third seed layer is shown.

[0032] Figure 4 The formation of the fourth seed layer is shown.

[0033] Figure 5 The formation of the first mask layer is shown.

[0034] Figure 6 The photolithography process of the first mask layer is shown.

[0035] Figure 7 The first mask layer has been removed.

[0036] Figure 8 The structure obtained by etching the fourth seed layer and the third seed layer is shown.

[0037] Figure 9 The formation of the first dielectric layer is shown.

[0038] Figure 10 The formation of the second seed layer is shown.

[0039] Figure 11 The formation of the second mask layer is shown.

[0040] Figure 12 The photolithography process for completing the second mask layer is shown.

[0041] Figure 13 The portion showing the etched first trace is illustrated.

[0042] Figure 14 The formation of the first curved layer is shown.

[0043] Figure 15 The structure obtained by removing a portion of the first curved layer is shown.

[0044] Figure 16 The structure obtained by removing the second mask layer is shown.

[0045] Figure 17 The etching of the second seed layer is shown.

[0046] Figure 18 The etching of the first seed layer is shown.

[0047] Figure 19 A semiconductor package structure according to an embodiment of this application is shown.

[0048] Figure 20 A perspective view of a nanowire structure according to an embodiment of this application is shown.

[0049] Figure 21 It shows the relationship with Figure 19 Semiconductor package structures in different embodiments.

[0050] Figure 22 It shows the relationship with Figure 19 Semiconductor package structures in different embodiments.

[0051] Figure 23 and Figure 24 Panel-level carriers and wafer-level carriers are shown respectively. Detailed Implementation

[0052] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0053] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0054] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate minor variations. When used in conjunction with an event or situation, these terms may refer to examples in which the event or situation occurred precisely or in examples in which the event or situation occurred very approximately.

[0055] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0056] For ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0057] Figures 2 to 19 The process of forming a semiconductor package structure 100 according to an embodiment of this application is shown.

[0058] Figure 2 The preparation of the carrier 50 is shown, on which a second dielectric layer 42 is formed.

[0059] Figure 3 The diagram illustrates, for example, the formation of a third seed layer 33 on a second dielectric layer 42 using a physical vapor deposition (PVD) process. The third seed layer 33 serves as a bonding seed layer for bonding a subsequent fourth seed layer 34. The material is a metal, such as Ti.

[0060] Figure 4 The diagram illustrates, for example, the formation of a fourth seed layer 34 on a third seed layer 33 using a PVD process. The fourth seed layer 34 is an electroplating seed layer for subsequent electroplating processes, and the material is a metal, such as Cu.

[0061] Figure 5 The diagram illustrates, for example, the formation of a first mask layer 61 on a fourth seed layer 34 via a lamination process, followed by the execution of a first exposure process 71. In some embodiments, the material of the first mask layer 61 is a photoresist (PR).

[0062] Figure 6 The image shows the development of the first mask layer 61 to complete the photolithography process of the first mask layer 61, resulting in a patterned first mask layer 61. A second trace 12 is formed on the fourth seed layer 34 exposed by the patterned first mask layer 61, for example by electroplating copper. The top surface of the second trace 12 is planar.

[0063] Figure 7 The diagram shows the removal of the first mask layer 61, and the execution of a first chemical etching process 81 using the second trace 12 as a mask to etch the fourth seed layer 34 and the third seed layer 33, resulting in... Figure 8 The structure shown consists of the fourth seed layer 34, the third seed layer 33, and the second trace 12, which together form a microtrace or nanotrace.

[0064] Figure 9 A first dielectric layer 41 is shown forming a first dielectric layer 41 covering the second trace 12, the fourth seed layer 34, and the third seed layer 33, and the first seed layer 31 is formed on the first dielectric layer 41 by, for example, performing a PVD process. The first seed layer 31 is an adhesive seed layer for bonding the subsequent second seed layer 32.

[0065] Figure 10 The diagram illustrates, for example, the formation of a second seed layer 32 on a first seed layer 31 using a PVD process, the second seed layer 32 being an electroplating initiation seed layer for subsequent electroplating processes.

[0066] Figure 11 The diagram illustrates, for example, the formation of a second mask layer 62 on a second seed layer 32 via a lamination process, followed by the execution of a second exposure process 72. In some embodiments, the material of the second mask layer 62 is a photoresist (PR).

[0067] Figure 12 The image shows the development of a second mask layer 62 to complete the photolithography process on the second mask layer 62, resulting in a patterned second mask layer 62. A first trace 11 is formed on the second seed layer 32 exposed by the patterned second mask layer 62, for example by electroplating metal. The first trace 11 is a nanowire and serves as an inner redistribution layer (Inner RDL). The first trace 11 and the second trace 12 are separated by a first dielectric layer 41 and projected in a top-to-bottom direction. The first trace 11 and the second trace 12 at least partially overlap.

[0068] Figure 13 The second chemical etching process 82 is shown. Due to the boundary effect, the portion of the first trace 11 near the second mask layer 62 is etched less, while the middle region is etched more. Thus, the second chemical etching process 82 etches the portion of the first trace 11 above the dashed line, so that the first trace 11 has a downwardly recessed top surface, with the top surface of the first trace 11 recessed toward the bottom surface of the first trace 11.

[0069] Figure 14The diagram illustrates, for example, the formation of a first curved layer 21 on a first trace 11 and a second mask layer 62 using a PVD process. The portion of the first curved layer 21 on the first trace 11 is conformal to the top surface of the first trace 11, thus also recessing downwards. The first curved layer 21 is an reinforcement layer where the material strength is greater than that of the first trace 11, enhancing structural strength and further overcoming surface stresses on the nanowire structure. In some embodiments, the first curved layer 21 has a uniform thickness, less than that of the first trace 11. In some embodiments, since the sidewalls of the patterned second mask layer 62 are vertical, the sidewalls of the first curved layer 21 formed therein are aligned with the sidewalls of the first trace 11.

[0070] A third chemical etching process 83 is performed to remove the portion of the first curved layer 21 located on the second mask layer 62, resulting in... Figure 15 The structure shown.

[0071] Remove the second mask layer 62 to obtain Figure 16 As shown in the structure, the second mask layer 62 can be removed in the same step as a portion of the first curved layer 21 above it.

[0072] Figure 17 The fourth chemical etching process 84 is shown, in which the second seed layer 32 is etched using the first curved layer 21 and the first trace 11 as a mask.

[0073] Figure 18 The fifth chemical etching process 85 is shown, in which the first seed layer 31 is etched using the first curved layer 21, the first trace 11 and the second seed layer 32 as a mask.

[0074] Figure 19 A semiconductor package structure 100 according to an embodiment of this application is shown. The semiconductor package structure 100 includes a first trace 11 for electrical connection; and a first bent layer 21 located on the first trace 11, the top surface of the first bent layer 21 being recessed toward the first trace 11. The first bent layer 21, the first trace 11, the first seed layer 31, and the second seed layer 32 constitute a nano-trace structure. Figure 19 The width in the cross-sectional view shown is, for example, several hundred nanometers; the pitch of adjacent nanowire structures is, for example, several hundred nanometers; the thickness of the first bent layer 21, the first trace 11, the first seed layer 31, and the second seed layer 32 is, for example, tens to hundreds of nanometers; and the top surface of the first bent layer 21 is... Figure 19 The cross-sectional view shown is in the shape of an arc, with a radius of, for example, several hundred nanometers.

[0075] In some embodiments, the material of the first dielectric layer 41 may be selected from non-metallic materials such as polyimide (PI), epoxy resin, Ajinomoto build-up film (ABF), prepreg (PP) or / and acrylic, and may be a dielectric made using organic photosensitive or / and non-photosensitive liquid or / and dry film materials.

[0076] The materials for the second seed layer 32 and the first trace 11 can be Cu, Au, Ag, Al, Pd, Pt, Ni, or their alloys. The material for the first seed layer 31 can be Ti, Cu, Pd, Pt, Ni, or their alloys. The second seed layer 32, the first trace 11, and the first seed layer 31 can be formed using processes such as physical vapor deposition (PVD), electroplating, electroless plating, printing, or potting.

[0077] The material of the first bending layer 21 can be a metal, such as Ti, W, stainless steel alloy, etc., or a non-metal, such as ceramic, glass, graphene, etc. The first bending layer 21 can be formed using processes such as PVD, electroplating, electroless plating, printing, potting, etc.

[0078] Figure 20 A perspective view of the nanowire structure according to an embodiment of this application and a top view of the stress on the stress line 95 are shown. Since the top surface of the first bending layer 21 is concave downwards, the bending stress 90 is distributed on the bent surface as two stresses: tensile stress 91 and compressive stress 92. The maximum tensile and compressive stresses on the upper surface of the first bending layer 21 are generated at the edge and center line of the upper surface, respectively. The tensile stress is perpendicular to the stress line 95 and faces outwards from both ends (i.e., in the same direction as the bending stress 90). Its force is less than half of the bending stress 90, which helps to reduce the influence of the bending stress 90. The compressive stress 92 is also perpendicular to the stress line 95 and faces in the opposite direction to the tensile stress 91, i.e., in the opposite direction to the bending stress 90, which helps to overcome the influence of the bending stress 90. The compressive stress 95 compresses towards the middle stress line 95, and its maximum value is equal to the bending stress 90. Therefore, the tensile stress 91 and the compressive stress 92 cancel each other out, making the total stress on the nanowire structure less than the original bending stress 90. The embodiments of this application provide a thin, ultra-fine line redistribution layer structure design, which relates to fan-out technology. The first trace 11 with a curved concave surface and the first curved layer 21 can offset the bending stress 90 caused by product bending by redistributing stress and direction compared to planar lines, thereby solving the problem of trace breakage caused by bending stress 90 and reducing the probability of fine lines breaking.

[0079] Figure 21 It shows the relationship with Figure 19 In a semiconductor package structure 100 of different embodiments, the top surface of the second trace 12 is recessed toward the bottom surface of the second trace 12, a second bending layer 22 is formed on the top surface of the second trace 12 and disposed between the top surface of the second trace 12 and the first dielectric layer 41, and the second bending layer 22 is conformal to the top surface of the second trace 12.

[0080] Figure 22 It shows the relationship with Figure 19 Different embodiments of the semiconductor package structure 100, wherein, Figure 19 The first trace 11 in the illustrated embodiment is exposed to the first dielectric layer 41. Figure 22 In the embodiment shown, the first trace 11 is embedded in the first dielectric layer 41, the first dielectric layer 41 covers the first trace 11 and the first bending layer 21, and the second trace 12, whose top surface is flat, is formed above the first dielectric layer 41.

[0081] Figure 23 and Figure 24 The diagrams show a square panel-level (PNL) carrier 50 and a circular wafer-level (WL) carrier 50. In some embodiments, multiple first traces 11 and second traces 21 of this application can be simultaneously formed on the PNL carrier 50 or the WL carrier 50. Chips 98 can also be optionally formed as needed to mass-produce and cost-effective semiconductor package structures 100, which are then processed using a monolithic process to obtain the final product. Figure 19 , Figure 21 or Figure 22 The monolithic semiconductor package structure 100 is shown.

[0082] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A semiconductor packaging structure, characterized in that, include: A first trace is used for electrical connection, wherein the top surface of the first trace is recessed toward the bottom surface of the first trace; A first curved layer is located on the first trace, with its top surface recessed towards the first trace. The first curved layer is conformal to the top surface of the first trace, and the first curved layer has a consistent thickness, and the material of the first curved layer has a greater strength than that of the first trace.

2. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the first curved layer is less than that of the first trace.

3. The semiconductor packaging structure according to claim 1, characterized in that, The side of the first curved layer is aligned with the sidewall of the first trace.

4. The semiconductor packaging structure according to claim 1, characterized in that, The first trace is a nanowire.

5. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: First seed layer; The second seed layer is located on the first seed layer, and the first trace is located on the second seed layer.

6. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: Second trace; A first dielectric layer covers the second trace, and the first trace is located above the first dielectric layer.

7. The semiconductor packaging structure according to claim 6, characterized in that, Projected along a top-to-bottom direction, the first trace and the second trace at least partially overlap.

8. The semiconductor packaging structure according to claim 6, characterized in that, The first trace and the second trace are separated by the first dielectric layer.

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