Motor control circuit

Abstract

The utility model relates to a motor control circuit. The circuit comprises a signal extraction sub-circuit, a delay sub-circuit, a control time sequence sub-circuit, a gate drive sub-circuit and an amplification sub-circuit. The signal extraction sub-circuit and the delay sub-circuit are in dual-phase connection; the output end of the time delay sub-circuit is also connected with the input end of the time sequence control sub-circuit; the output end of the control time sequence sub-circuit is connected with the input end of the gate driving sub-circuit; the output end of the gate drive sub-circuit is connected with the input end of the amplification sub-circuit. A signal extraction sub-circuit is added to actively identify signals of rotation direction conversion of the brushless motor, turn-off of an MOS tube in a power amplification circuit is realized, damage of large current generated by rotation direction conversion of the brushless motor to an inverter is reduced, disturbance to power supply voltage is reduced, and efficiency and reliability of the inverter are improved; instantaneous large current generated in the instantaneous commutation driver is suppressed, and a driver circuit is protected, so that the working efficiency and the stability of the driver are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a motor control circuit. BACKGROUND

[0002] When the motor changes direction, the back electromotive force inside the motor interacts with the electromotive force provided by the external power supply, and the back electromotive force of the motor and the electromotive force of the power supply produce a superposition effect, which produces a large instantaneous current.

[0003] However, the generation of a large instantaneous current often leads to damage to the driving circuit, an impact on the power supply voltage, and further causes system failure, and may even have adverse effects on other related equipment; in particular, when the motor is in a servo control state, frequent forward and reverse conversion will cause thermal accumulation effect, mechanical impact and vibration, and the impact of large current on the driving system and power supply will also be intensified, further increasing the risk of equipment failure, affecting the stability and reliability of the entire system.

[0004] Therefore, there is an urgent need to develop a motor control circuit to solve one or more of the above problems. SUMMARY

[0005] In view of this, in order to solve the above technical problems or part of the technical problems, the utility model embodiment provides a motor control circuit.

[0006] In a first aspect, the application provides a motor control circuit, the circuit comprising: a signal extraction sub-circuit, a delay sub-circuit, a control timing sub-circuit, a gate drive sub-circuit and an amplification sub-circuit;

[0007] The signal extraction sub-circuit and the delay sub-circuit are connected in dual phase;

[0008] The output end of the delay sub-circuit is also connected to the input end of the control timing sub-circuit;

[0009] The output end of the control timing sub-circuit is connected to the input end of the gate drive sub-circuit;

[0010] The output end of the gate drive sub-circuit is connected to the input end of the amplification sub-circuit.

[0011] In one possible implementation, the output end of the signal extraction sub-circuit is connected to the input end of the control timing sub-circuit.

[0012] In one possible implementation, the circuit further comprises an execution sub-circuit;

[0013] The input end of the execution sub-circuit is connected to the output end of the delay sub-circuit, and the output end of the execution sub-circuit is connected to the input end of the control timing sub-circuit and the input end of the gate drive sub-circuit.

[0014] In a possible implementation, the signal extraction sub-circuit comprises a collection integrated unit, a first extraction capacitor, a second extraction capacitor, a first extraction resistor, a second extraction resistor, a first extraction diode, and a second extraction diode.

[0015] One end of the first extraction capacitor is connected to the second port and the thirteenth port of the collection integrated unit, and the other end of the first extraction capacitor is connected to one end of the first extraction resistor and the anode of the first extraction diode.

[0016] The other end of the first extraction resistor is connected to one end of the second extraction resistor and the ground, and the other end of the second extraction resistor is connected to one end of the second extraction capacitor and the anode of the second extraction diode.

[0017] The other end of the second extraction capacitor is connected to the twelfth port of the collection integrated unit.

[0018] The cathode of the first extraction diode and the cathode of the second extraction diode are connected to the input end of the delay sub-circuit, for outputting a pulse trigger signal to the delay sub-circuit.

[0019] In a possible implementation, the first port and the third port of the collection integrated unit are connected to a motor, for inputting a direction control signal output by the motor.

[0020] The tenth port of the collection integrated unit is connected to the input end of the control timing sub-circuit, for outputting a second brake signal to the control timing sub-circuit.

[0021] The eleventh port of the collection integrated unit is connected to the output end of the delay sub-circuit, for inputting a first brake signal output by the delay sub-circuit.

[0022] In a possible implementation, the delay sub-circuit comprises a timing integrated unit, a first delay capacitor, a second delay capacitor, a third delay capacitor, a first delay resistor, a second delay resistor, and a first delay diode.

[0023] The first port of the timing integrated unit is connected to one end of the first delay capacitor and the ground.

[0024] The other end of the first delay capacitor is connected to the fourth port of the timing integrated unit, the eighth port of the timing integrated unit, and one end of the first delay resistor.

[0025] The other end of the first delay resistor is connected to the seventh port of the timing integrated unit and the cathode of the first delay diode.

[0026] An anode of the first delay diode is connected to an input of the control timing sub-circuit, for outputting a first delay signal to the control timing sub-circuit;

[0027] A sixth port of the timing integration unit is connected to one end of the second delay resistor and one end of the second delay capacitor;

[0028] The other end of the second delay resistor is connected to a fifth port of the timing integration unit through a third delay capacitor;

[0029] The other end of the second delay capacitor is connected to an output of the signal extraction sub-circuit, for inputting a pulse trigger signal output by the signal extraction sub-circuit;

[0030] A seventh port of the timing integration unit is also connected to an input of the signal extraction sub-circuit, for outputting a first brake signal to the signal extraction sub-circuit.

[0031] In a possible implementation, the control timing sub-circuit comprises a suppression timing unit and a control integration unit;

[0032] An input of the suppression timing unit is connected to an output of the delay sub-circuit;

[0033] An output of the suppression timing unit is connected to an input of the control integration unit;

[0034] The input of the control integration unit is also connected to an output of the execution sub-circuit;

[0035] An output of the control integration unit is connected to an input of the gate drive sub-circuit.

[0036] In a possible implementation, a first end, an eighth end, and a thirteenth end of the control integration unit are connected to an output of the suppression timing unit, for inputting a second delay signal output by the suppression timing unit;

[0037] A second end, a ninth end, and a twelfth end of the control integration unit are connected to an output of the execution sub-circuit, for sequentially inputting a first execution sub-signal, a sixth execution sub-signal, and a fifth execution sub-signal output by the execution sub-circuit;

[0038] A third end, a tenth end, and an eleventh end of the control integration unit are connected to an input of the gate drive sub-circuit, for sequentially outputting a first timing sub-signal, a third timing sub-signal, and a second timing sub-signal to the gate drive sub-circuit.

[0039] In a possible implementation, the gate drive sub-circuit comprises three groups of driving modules with the same structure;

[0040] The output end of the driving module is connected with the input end of the amplification sub-circuit; the input end of the driving module is connected with the output end of the execution sub-circuit and the output end of the control timing sub-circuit.

[0041] In one possible implementation, any of the driving modules comprises a driving integrated unit, a first driving resistor, and a second driving resistor.

[0042] The fifth port of the driving integrated unit is connected with the input end of the amplification sub-circuit through the first driving resistor, for outputting a first self-sensing signal to the amplification sub-circuit, the first self-sensing signal comprising a LU signal, a LV signal, and a LW signal.

[0043] The seventh port of the driving integrated unit is connected with the input end of the amplification sub-circuit through the second driving resistor, for outputting a second self-sensing signal to the amplification sub-circuit, the second self-sensing signal comprising a HU signal, a HV signal, and a HW signal.

[0044] The sixth port of the driving integrated unit is connected with the input end of the amplification sub-circuit, for outputting a three-phase signal to the amplification sub-circuit, the three-phase signal comprising a U signal, a V signal, and a W signal.

[0045] The second port of the driving integrated unit is connected with the output end of the execution sub-circuit, for inputting an execution signal output by the driving integrated unit, the execution signal comprising a second execution sub-signal, a third execution sub-signal, and a fourth execution sub-signal.

[0046] The third port of the driving integrated unit is connected with the output end of the control timing sub-circuit, for inputting a timing sub-signal output by the control timing sub-circuit, the timing sub-signal comprising a first timing sub-signal, a second timing sub-signal, and a third timing sub-signal.

[0047] Compared with the prior art, the above technical solution provided by the embodiments of the present application has the following advantages: the motor control circuit provided by the embodiments of the present application actively identifies the signal of the rotation direction conversion of the brushless motor through the signal extraction sub-circuit, and when the direction is converted, the MOS tube in the power amplification circuit is turned off through the signal extraction sub-circuit, the delay sub-circuit, the control timing sub-circuit, the execution sub-circuit, the gate driving sub-circuit, and the amplification sub-circuit, the large current generated by the rotation direction conversion of the brushless motor is reduced to damage the inverter, the disturbance to the power supply voltage is reduced, the efficiency and reliability of the inverter are improved, the instantaneous large current generated in the instantaneous commutation driver is inhibited, and the driver circuit is protected, so that the working efficiency and stability of the driver are realized. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without any creative effort.

[0050] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting of the present application, and the same or similar reference numerals designate similar or like elements throughout the several views of the drawings, as readily understood in the art. The drawings of the application in which are shown by way of illustration the present application, not to the limit of the application.

[0051] Figure 1 A circuit principle block diagram of a motor control circuit provided for the embodiments of the present application is shown in the figure.

[0052] Figure 2 A structure schematic diagram of an execution sub-circuit provided for the embodiments of the present application is shown in the figure.

[0053] Figure 3 A structure schematic diagram of a signal extraction sub-circuit provided for the embodiments of the present application is shown in the figure.

[0054] Figure 4 A structure schematic diagram of a delay sub-circuit provided for the embodiments of the present application is shown in the figure.

[0055] Figure 5 A structure schematic diagram of a control timing sub-circuit provided for the embodiments of the present application is shown in the figure.

[0056] Figure 6 A structure schematic diagram of a gate drive sub-circuit provided for the embodiments of the present application is shown in the figure.

[0057] Figure 7 A structure schematic diagram of an amplification sub-circuit provided for the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort belong to the scope of protection of the present application.

[0059] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the elements of the particular examples are described in the following disclosure. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application can repeatedly refer to reference numerals and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or arrangements being discussed.

[0060] In order to solve the technical problem that in the prior art, when the motor commutates during rotation, the inertia in the original rotation direction needs to be overcome, and acceleration in the new direction needs to be added, resulting in a great impact on the mechanism and the driving circuit during the commutation rotation of the motor, and even possible damage to the mechanism and the driving circuit, causing failure, the present application provides a motor control circuit, which can turn off the MOS tube in the power amplifier circuit, reduce the damage of the large current generated during the rotation direction conversion of the brushless motor to the inverter, reduce the disturbance to the power supply voltage, improve the efficiency and reliability of the inverter, suppress the instantaneous large current generated in the instantaneous commutation driver, and protect the driver circuit, so as to realize the working efficiency and stability of the driver.

[0061] Figure 1 The circuit principle block diagram of the motor control circuit provided by the embodiment of the present application is shown as Figure 1 The motor control circuit comprises a signal extraction sub-circuit 101, a delay sub-circuit 102, a control timing sub-circuit 103, a gate drive sub-circuit 105, and an amplification sub-circuit 106.

[0062] The signal extraction sub-circuit 101 is connected to the delay sub-circuit 102 in double phase;

[0063] The output end of the delay sub-circuit 102 is also connected to the input end of the control timing sub-circuit 103;

[0064] The output end of the control timing sub-circuit 103 is connected to the input end of the gate drive sub-circuit 105;

[0065] The output end of the gate drive sub-circuit 105 is connected to the input end of the amplification sub-circuit 106.

[0066] In the embodiment, the signal extraction sub-circuit 101 receives the high and low level changes of the external direction control signal, filters and converts the high and low level changes of the direction into positive pulse trigger signals through the NOT gate and its peripheral circuit; the delay sub-circuit 102 receives the pulse trigger signals generated by the signal extraction sub-circuit 101, generates a second delay signal; the control timing sub-circuit 103 receives the delay protection signal of the delay sub-circuit 102, generates a protection timing signal; the execution sub-circuit 104 receives the timing signal generated by the control timing sub-circuit 103; the gate drive sub-circuit 105 receives the protected execution signal, generates a level for turning off the power amplification circuit; and the amplification sub-circuit 106 receives the turn-off signal of the gate drive sub-circuit 105, and turns off the MOS tube.

[0067] Optionally, the signal extraction sub-circuit 101 is connected with the external direction control signal, the input end of the delay sub-circuit 102 is connected with the signal extraction sub-circuit 101, the input end of the control timing sub-circuit 103 is connected with the signal extraction sub-circuit 101, the input end of the execution sub-circuit 104 is connected with the control timing sub-circuit 103, the input end of the gate drive sub-circuit 105 is connected with the execution sub-circuit 104, and the input end of the amplification sub-circuit 106 is connected with the gate drive sub-circuit 105.

[0068] In an optional scheme of the embodiment of the utility model, the output end of the signal extraction sub-circuit 101 is connected with the input end of the control timing sub-circuit 103.

[0069] The motor control method provided by the application actively identifies the signal of the rotation direction conversion of the brushless motor through the signal extraction sub-circuit 101, and when the direction is converted, the signal extraction sub-circuit 101, the delay sub-circuit 102, the control timing sub-circuit 103, the execution sub-circuit 104, the gate drive sub-circuit 105 and the amplification sub-circuit 106 are used to realize the turn-off of the MOS tube in the power amplification circuit, the current generated by the superposition of the motor back electromotive force and the power supply voltage and the power supply voltage fluctuation are greatly reduced, the damage of the large current brought by the rotation direction conversion of the brushless motor to the inverter is reduced, the disturbance to the power supply voltage is reduced, the efficiency and reliability of the inverter are improved, the instantaneous large current generated in the instantaneous commutation driver is inhibited, the driver circuit is protected, and the working efficiency and stability of the driver are improved.

[0070] Figure 2 The execution sub-circuit provided by the embodiment of the application is shown in the structure diagram as Figure 2 The motor control circuit further comprises an execution sub-circuit 104.

[0071] The input end of the execution sub-circuit 104 is connected with the output end of the delay sub-circuit 102, the output end of the execution sub-circuit 104 is connected with the input end of the control timing sub-circuit 103 and the input end of the gate drive sub-circuit 105.

[0072] In the embodiment, the execution sub-circuit 104 realizes the related functions through the components and the connection mode in Figure 2 The second delay signal generated by the delay sub-circuit 102 is connected with the first delay signal PTC through a diode, and the second delay signal is a low-level pulse trigger signal. The PTC signal and the direction control signal pass through an AND gate, and then generate the gate drive sub-circuit 105 control signal together with the position recognition signal; when the second delay signal is generated, the PTC signal can be pulled to low level through the diode, and no delay signal is generated, and the PTC signal remains the original state; after the PTC signal is pulled low, the outputs of the AND gates passed by the PTC signal all become low level, resulting in that the gate drive sub-circuit 105 control signals of the outputs of the above three three-input AND gates all become low level, thereby achieving the purpose of closing the working state of the gate drive sub-circuit 105 during the low-level pulse time of the delay signal, and finally achieving the closing of the three-phase bridge power discharge circuit.

[0073] After the low-level pulse trigger signal of the second delay signal ends, the delay sub-circuit 102 outputs a high level, and due to the unidirectional conduction of the diode, the PTC signal remains the original state and is not affected by the delay circuit.

[0074] The LG11, the LG22, the LG32, the LG12, the LG21 and the LG31 in the execution sub-circuit 104 are output ports, and sequentially output the first execution sub-signal, the second execution sub-signal, the third execution sub-signal, the fourth execution sub-signal, the fifth execution sub-signal and the sixth execution sub-signal.

[0075] Figure 3 The structural schematic diagram of the signal extraction sub-circuit 101 provided by the embodiment is shown as Figure 3 The signal extraction sub-circuit 101 includes the collection integration unit U11, the first extraction capacitor C29, the second extraction capacitor C30, the first extraction resistor R16, the second extraction resistor R19, the first extraction diode D5 and the second extraction diode D4.

[0076] One end of the first extraction capacitor C29 is connected with the second port and the thirteenth port of the collection integration unit U11, and the other end of the first extraction capacitor C29 is connected with one end of the first extraction resistor R16 and the anode of the first extraction diode D5.

[0077] The other end of the first extraction resistor R16 is connected to one end of the second extraction resistor R19 and then grounded; the other end of the second extraction resistor R19 is connected to one end of the second extraction capacitor C30 and the anode of the second extraction diode D4;

[0078] The other end of the second extraction capacitor C30 is connected to the twelfth port of the collection integrated unit U11.

[0079] The cathode of the first extraction diode D5 is connected to the cathode of the second extraction diode D4 and then connected to the input end of the delay sub-circuit 102, for outputting a pulse trigger signal to the delay sub-circuit 102.

[0080] In an optional scheme of the embodiment of the utility model, the first port and the third port of the collection integrated unit U11 are connected to a motor, for inputting a direction control signal output by the motor;

[0081] The tenth port of the collection integrated unit U11 is connected to the input end of the control timing sub-circuit 103, for outputting a second brake signal to the control timing sub-circuit 103.

[0082] The eleventh port of the collection integrated unit U11 is connected to the output end of the delay sub-circuit 102, for inputting a first brake signal output by the delay sub-circuit 102.

[0083] In the embodiment, the signal extraction sub-circuit 101 realizes the related functions through components and connection modes in Figure 3 , wherein U11 represents the collection integrated unit of the signal extraction sub-circuit 101, R16, R19, R20 and R22 represent the first extraction resistor, the second extraction resistor, the third extraction resistor and the fourth extraction resistor respectively in sequence, C29, C30 and C31 represent the first extraction capacitor, the second extraction capacitor and the third extraction capacitor respectively in sequence, D4 and D5 represent the second extraction diode and the first extraction diode, which are the same rectifier diodes. DIRX is a direction control terminal inputting a second delay signal, DIR is a direction output terminal inputting a direction output signal, BRA is a protection time brake port inputting a first brake signal, / BRA is a protection time brake output non-port outputting a second brake signal, and TR is a pulse trigger signal port outputting a pulse trigger signal.

[0084] Figure 4 The structure diagram of the delay sub-circuit 102 provided in the embodiment of the utility model is shown in Figure 4 , which comprises a timing integrated unit U12, a first delay capacitor C28, a second delay capacitor C27, a third delay capacitor C26, a first delay resistor R30, a second delay resistor R15 and a first delay diode D6.

[0085] The first port of the timing integrated unit U12 is connected with one end of the first delay capacitor C28 and then grounded.

[0086] The other end of the first delay capacitor C28 is connected with the fourth port of the timing integrated unit U12, the eighth port of the timing integrated unit U12, and one end of the first delay resistor R30.

[0087] The other end of the first delay resistor R30 is connected with the seventh port of the timing integrated unit U12 and the cathode of the first delay diode D6.

[0088] The anode of the first delay diode D6 is connected with the input end of the control timing sub-circuit 103, for outputting the first delay signal to the control timing sub-circuit 103.

[0089] The sixth port of the timing integrated unit U12 is connected with one end of the second delay resistor R15 and one end of the second delay capacitor C27.

[0090] The other end of the second delay resistor R15 is connected with the fifth port of the timing integrated unit U12 through the third delay capacitor C26.

[0091] The other end of the second delay capacitor C27 is connected with the output end of the signal extraction sub-circuit 101, for inputting the pulse trigger signal outputted by the signal extraction sub-circuit 101.

[0092] The seventh port of the timing integrated unit U12 is also connected with the input end of the signal extraction sub-circuit 101, for outputting the first brake signal to the signal extraction sub-circuit 101.

[0093] In the embodiment, the delay sub-circuit 102 realizes the related functions through the components and connection modes in Figure 4 , wherein U12 represents a timing integrated unit, R15 is a second delay resistor, R30 is a first delay resistor, C28 is a first delay capacitor, C27 is a second delay capacitor, C26 is a third delay capacitor, D6 represents a first delay diode, TR is a pulse trigger signal input terminal for inputting a pulse trigger signal, BRA is a brake signal terminal for outputting a first brake signal, and PTC is an upper bridge arm protection signal terminal for outputting a first delay signal.

[0094] Figure 5 The structure schematic diagram of the control timing sub-circuit 103 provided in the embodiment is shown in Figure 5 The control timing sub-circuit 103 comprises a suppression timing unit and a control integrated unit U13.

[0095] The input end of the suppression timing unit is connected with the output end of the delay sub-circuit 102.

[0096] The output end of the inhibition timing unit is connected to the input end of the control integrated unit U13;

[0097] The input end of the control integrated unit U13 is also connected to the output end of the execution sub-circuit 104;

[0098] The output end of the control integrated unit U13 is connected to the input end of the gate drive sub-circuit 105.

[0099] In an optional scheme of the embodiment of the utility model, the first end, the eighth end, the thirteenth end of the control integrated unit U13 are connected to the output end of the inhibition timing unit, for inputting the second delay signal output by the inhibition timing unit;

[0100] The second end, the ninth end, the twelfth end of the control integrated unit U13 are connected to the output end of the execution sub-circuit 104, for sequentially inputting the first execution sub-signal, the sixth execution sub-signal, the fifth execution sub-signal output by the execution sub-circuit 104;

[0101] The third end, the tenth end, the eleventh end of the control integrated unit are connected to the input end of the gate drive sub-circuit 105, for sequentially outputting the first timing sub-signal, the third timing sub-signal, the second timing sub-signal to the gate drive sub-circuit 105.

[0102] In the embodiment, the control timing sub-circuit 103 realizes the related functions through the components and the connection mode in Figure 5 , wherein U13 represents the control integrated unit of the control timing sub-circuit 103, R21, R31, R32 represent different resistances respectively, C36, C37 represent different capacitors respectively, D7, D8 represent the same rectifier diode, BRA represents the protection brake signal terminal input and output first brake signal, / BRA represents the protection brake signal non-signal terminal output second brake signal, PTC represents the upper bridge arm protection signal terminal input first delay signal, DBRA represents the lower bridge arm protection signal terminal output second delay signal, BU1 / BV1 / BW1 lower bridge logic input terminal output first timing sub-signal, third timing sub-signal, second timing sub-signal.

[0103] Figure 6 The structural schematic diagram of the gate drive sub-circuit 105 provided by the embodiment of the application is as shown in Figure 6 The gate drive sub-circuit 105 includes three groups of driving modules with the same structure;

[0104] The output end of the driving module is connected with the input end of the amplification sub-circuit 106; the input end of the driving module is connected with the output end of the execution sub-circuit 104 and the output end of the control timing sub-circuit 103.

[0105] In an optional scheme of the embodiment of the utility model, any driving module includes a driving integrated unit, a first driving resistor and a second driving resistor.

[0106] The fifth port of the driving integrated unit is connected with the input end of the amplification sub-circuit 106 through the first driving resistor, for outputting a first self-induction signal to the amplification sub-circuit 106, and the first self-induction signal includes LU signal, LV signal and LW signal.

[0107] The seventh port of the driving integrated unit is connected with the input end of the amplification sub-circuit 106 through the second driving resistor, for outputting a second self-induction signal to the amplification sub-circuit 106, and the second self-induction signal includes HU signal, HV signal and HW signal.

[0108] The sixth port of the driving integrated unit is connected with the input end of the amplification sub-circuit 106, for outputting a three-phase signal to the amplification sub-circuit 106, and the three-phase signal includes U signal, V signal and W signal.

[0109] The second port of the driving integrated unit is connected with the output end of the execution sub-circuit 104, for inputting an execution signal outputted by the driving integrated unit, and the execution signal includes a second execution sub-signal, a third execution sub-signal and a fourth execution sub-signal.

[0110] The third port of the driving integrated unit is connected with the output end of the control timing sub-circuit 103, for inputting a timing sub-signal outputted by the control timing sub-circuit 103, and the timing sub-signal includes a first timing sub-signal, a second timing sub-signal and a third timing sub-signal.

[0111] In the embodiment, the gate drive sub-circuit 105 realizes relevant functions through components and connection modes in Figure 6 , wherein U8, U9 and U10 represent driving integrated units of the gate drive sub-circuit 105, R23, R24, R25, R26, R27 and R28 represent different resistors, wherein R23, R25 and R27 are first driving resistors, and R28, R26 and R24 are second driving resistors.

[0112] C7, C8, C9, C14, C15, C16 represent different capacitors respectively, BU1, BU2, BU3 are the labels of terminals, which are connected with the terminals with the same labels in the internal of the control timing sub-circuit 103. LG12, LG22, LG32 are the labels of terminals, which are connected with the terminals with the same labels in the internal of the execution sub-circuit 104. HU, HV, HW, LU, LV, LW, U1, V1, W1 are the labels of terminals, which are connected with the terminals with the same labels in the internal of the amplification sub-circuit 106, and sequentially output HU signal, HV signal, HW signal, LU signal, LV signal, LW signal, U signal, V signal, W signal.

[0113] Figure 7 The structural schematic diagram of the amplification sub-circuit 106 provided by the embodiment of the present application is shown as follows, Figure 7 The amplification sub-circuit 106 realizes the related functions through the components and the connection mode in Figure 7 , wherein Q1, Q2, Q3, Q4, Q5, Q6 represent MOS tubes, R10, R11, R12, R13, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53 represent different resistances respectively, HU, HV, HW, LU, LV, LW, U1, V1, W1 are the labels of terminals, which are connected with the terminals with the same labels in the internal of the gate driving sub-circuit 105, and sequentially input HU signal, HV signal, HW signal, LU signal, LV signal, LW signal, U signal, V signal, W signal.

[0114] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software plus a general hardware platform, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions essentially or say the part which contributes to the related art can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the method described in each embodiment or some part of the embodiment.

[0115] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0116] The above description is merely that of the specific embodiments of the application and as such is not to be taken in a limiting sense. Various modifications and alterations of the embodiments described herein will become apparent to those skilled in the art from the foregoing description, which does not limit the generality presented. It is the intention that all such modifications and alterations be considered equaliy by the spirit and scope of this application. It is therefore intended to cover in the appended claims all such changes and alterations that come within the scope of this application.

Claims

1. A motor control circuit, characterized by comprising: The application relates to a signal extraction circuit, which comprises a signal extraction subcircuit, a delay subcircuit, a control timing subcircuit, a gate drive subcircuit and an amplification subcircuit. The signal extraction subcircuit and the delay subcircuit are connected in dual phase. The output end of the delay subcircuit is also connected to the input end of the control timing subcircuit. The output end of the control timing subcircuit is connected to the input end of the gate drive subcircuit. The output end of the gate drive subcircuit is connected to the input end of the amplification subcircuit. The output end of the signal extraction subcircuit is connected to the input end of the control timing subcircuit.

2. The motor control circuit of claim 1, wherein, The signal extraction circuit further comprises an execution subcircuit.

3. The motor control circuit of claim 2, wherein, The input end of the execution subcircuit is connected to the output end of the delay subcircuit, and the output end of the execution subcircuit is connected to the input end of the control timing subcircuit and the input end of the gate drive subcircuit. The signal extraction subcircuit comprises a collection integrated unit, a first extraction capacitor, a second extraction capacitor, a first extraction resistor, a second extraction resistor, a first extraction diode and a second extraction diode.

4. The motor control circuit of claim 1, wherein, One end of the first extraction capacitor is connected to the second port and the thirteenth port of the collection integrated unit, and the other end of the first extraction capacitor is connected to one end of the first extraction resistor and the anode of the first extraction diode. The other end of the first extraction resistor is connected to one end of the second extraction resistor and then grounded. The other end of the second extraction resistor is connected to one end of the second extraction capacitor and the anode of the second extraction diode. The other end of the second extraction capacitor is connected to the twelfth port of the collection integrated unit. The cathode of the first extraction diode is connected to the cathode of the second extraction diode and then connected to the input end of the delay subcircuit, and is used for outputting a pulse trigger signal to the delay subcircuit. The first port and the third port of the collection integrated unit are connected to a motor, and are used for inputting a direction control signal output by the motor.

5. The motor control circuit of claim 4, wherein, The tenth port of the collection integrated unit is connected to the input end of the control timing subcircuit, and is used for outputting a second brake signal to the control timing subcircuit. The eleventh port of the collection integrated unit is connected to the output end of the delay subcircuit, and is used for inputting a first brake signal output by the delay subcircuit. The delay subcircuit comprises a timing integrated unit, a first delay capacitor, a second delay capacitor, a third delay capacitor, a first delay resistor, a second delay resistor and a first delay diode.

6. The motor control circuit of claim 5, wherein, The first port of the timing integrated unit is connected to one end of the first delay capacitor and then grounded. The other end of the first delay capacitor is connected to the fourth port of the timing integrated unit, the eighth port of the timing integrated unit and one end of the first delay resistor. The other end of the first delay resistor is connected to the seventh port of the timing integrated unit and the cathode of the first delay diode. The anode of the first delay diode is connected to the input end of the control timing subcircuit, and is used for outputting a first delay signal to the control timing subcircuit. The sixth port of the timing integrated unit is connected to one end of the second delay resistor and one end of the second delay capacitor. The other end of the second delay resistor is connected to the fifth port of the timing integrated unit through the third delay capacitor. ​ Another end of the second delay capacitor is connected to an output end of the signal extraction sub-circuit, for inputting a pulse trigger signal output by the signal extraction sub-circuit; The seventh port of the timing integration unit is also connected to an input end of the signal extraction sub-circuit, for outputting a first brake signal to the signal extraction sub-circuit.

7. The motor control circuit of claim 3, wherein, The control timing sub-circuit comprises a suppression timing unit and a control integration unit; An input end of the suppression timing unit is connected to an output end of the delay sub-circuit; An output end of the suppression timing unit is connected to an input end of the control integration unit; An input end of the control integration unit is also connected to an output end of the execution sub-circuit; An output end of the control integration unit is connected to an input end of the gate drive sub-circuit.

8. The motor control circuit of claim 7, wherein, A first end, an eighth end and a thirteenth end of the control integration unit are connected to an output end of the suppression timing unit, for inputting a second delay signal output by the suppression timing unit; A second end, a ninth end and a twelfth end of the control integration unit are connected to an output end of the execution sub-circuit, for sequentially inputting a first execution sub-signal, a sixth execution sub-signal and a fifth execution sub-signal output by the execution sub-circuit; A third end, a tenth end and an eleventh end of the control integration unit are connected to an input end of the gate drive sub-circuit, for sequentially outputting a first timing sub-signal, a third timing sub-signal and a second timing sub-signal to the gate drive sub-circuit.

9. The motor control circuit of claim 3, wherein, The gate drive sub-circuit comprises three groups of driving modules with the same structure; An output end of the driving module is connected to an input end of the amplification sub-circuit; and an input end of the driving module is connected to an output end of the execution sub-circuit and an output end of the control timing sub-circuit.

10. The motor control circuit of claim 9, wherein, Any one of the driving modules comprises a driving integration unit, a first driving resistor and a second driving resistor; A fifth port of the driving integration unit is connected to the input end of the amplification sub-circuit through the first driving resistor, for outputting a first self-induction signal to the amplification sub-circuit, the first self-induction signal comprising a LU signal, a LV signal and a LW signal; A seventh port of the driving integration unit is connected to the input end of the amplification sub-circuit through the second driving resistor, for outputting a second self-induction signal to the amplification sub-circuit, the second self-induction signal comprising a HU signal, a HV signal and a HW signal; A sixth port of the driving integration unit is connected to the input end of the amplification sub-circuit, for outputting a three-phase signal to the amplification sub-circuit, the three-phase signal comprising a U signal, a V signal and a W signal; A second port of the driving integration unit is connected to the output end of the execution sub-circuit, for inputting an execution signal output by the driving integration unit, the execution signal comprising a second execution sub-signal, a third execution sub-signal and a fourth execution sub-signal; A third port of the driving integration unit is connected to the output end of the control timing sub-circuit, for inputting a timing sub-signal output by the control timing sub-circuit, the timing sub-signal comprising a first timing sub-signal, a second timing sub-signal and a third timing sub-signal.

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