Semiconductor device integrated with temperature sensor and semiconductor device array integrated with temperature sensor

Abstract

The utility model discloses a semiconductor device integrated with a temperature sensor and a semiconductor device array integrated with the temperature sensor. An N + substrate layer, an N-drift layer, a P-type base region, a P + source region, an N + source region, a gate oxide layer, a polycrystalline silicon layer, an electrode layer, a passivation layer, a silicon nitride layer, a gate electrode layer, a gate dielectric layer, a source electrode layer, a drain electrode layer, a laser filament marked and ablated MXene conductive channel and a silicon nitride protective layer are sequentially arranged from bottom to top. The array type temperature sensor is directly integrated on the surface of the VDMOS device, the working temperature of the device can be accurately reflected in real time, errors caused by position deviation or heat conduction delay of an external temperature sensor are avoided, additional temperature sensor assemblies and connecting circuits are not needed, and the manufacturing cost and complexity are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a vertical double-diffused metal-oxide-semiconductor (VDMOS) device integrated with a temperature sensor. BACKGROUND

[0002] The vertical double-diffused metal-oxide-semiconductor (VDMOS) device is widely used in power management, electric vehicle control, industrial control and other fields due to its low power consumption, high frequency response, high voltage resistance and good thermal characteristics. During the operation of the VDMOS device, temperature changes have an important influence on its performance. Excessive temperature may cause the performance of the device to decline or fail, and therefore temperature monitoring and protection of the VDMOS device are needed. The commonly used temperature monitoring method is to achieve it through an external temperature sensor, which usually requires additional hardware devices and connection lines, which not only increases the complexity of the system, but also increases the cost. At the same time, the external temperature sensor cannot accurately reflect the internal temperature of the VDMOS device. CONTENT OF THE UTILITY MODEL

[0003] In view of the above technical problems, the present application proposes a semiconductor device integrated with a temperature sensor, in order to solve the problem that the related VDMOS device cannot reflect the internal temperature of the VDMOS device using an external temperature sensor.

[0004] In a first aspect, the present application provides a semiconductor device integrated with a temperature sensor. The semiconductor device comprises: a semiconductor device substrate; a temperature sensor directly located on the semiconductor device substrate and the temperature sensor having a buried field effect transistor structure.

[0005] Optionally, the buried field effect transistor structure comprises: an isolation layer directly located on the semiconductor device substrate; a gate electrode located on the isolation layer; a gate dielectric layer located on the gate electrode layer; a source electrode and a drain electrode located on the gate dielectric layer, wherein the projection of the gate electrode on the semiconductor device substrate is located between the projection of the source electrode on the semiconductor device substrate and the projection of the drain electrode on the semiconductor device substrate; a temperature-sensitive material layer located on the gate dielectric layer, the source electrode and the drain electrode; and a protective layer located on the conductive layer.

[0006] Optionally, the isolation layer is a silicon nitride layer with a thickness of 200 nm.

[0007] Optionally, the thickness of each of the source electrode and the drain electrode is 10-20 nm or 50-100 nm.

[0008] Optionally, the protective layer is a silicon nitride layer with a thickness of 400-500 nm.

[0009] In a second aspect, the application provides an integrated temperature sensor semiconductor device array, comprising: the semiconductor device of the first aspect; and a detection circuit configured to detect a current in the temperature sensor and determine a temperature in a substrate of the semiconductor device based on the current.

[0010] The VDMOS device with integrated on-chip array temperature sensing provided by the utility model has the following beneficial effects:

[0011] (1) The integrated on-chip array temperature sensing design makes temperature monitoring more accurate. Since the temperature sensor is directly integrated on the surface of the VDMOS device, it can accurately reflect the working temperature of the device in real time, avoiding errors caused by position deviation or thermal conduction delay of external temperature sensors. Without additional temperature sensor components and connection circuits, the manufacturing cost and complexity are reduced.

[0012] (2) The array layout improves the resolution and coverage of temperature monitoring, and can more comprehensively reflect the temperature distribution inside the device.

[0013] (3) The buried field effect transistor structure makes the coupling between the gate and the channel more closely, thereby improving the regulation efficiency of the gate on the temperature sensor device. This close coupling helps the gate voltage to more effectively control the current in the channel, achieving more accurate temperature sensing. In addition, the field effect transistor structure temperature sensor has a fast response speed. They can sense temperature changes in a very short time and respond quickly, which is important for real-time monitoring of temperature changes

[0014] (4) The femtosecond laser plasma channel marking ablation technology is used to realize the patterning preparation of the MXene sensitive layer, which is environmentally friendly and sustainable, and can realize efficient preparation of the sample. At the same time, the femtosecond laser plasma channel ablation technology can optimize the thickness uniformity of the MXene sensitive layer, effectively improving the sensitivity and response speed of the device. BRIEF DESCRIPTION OF DRAWINGS

[0015] The drawings incorporated herein and forming a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. It is to be expressly understood, however, that the drawings are included herein for illustrative purposes only and that they are subject to interpretation, modification and / or change in light of this disclosure and of current art.

[0016] Figure 1A The structure diagram of the integrated temperature sensor semiconductor device of the present application is shown in the figure.

[0017] Figure 1BA schematic diagram of an array of integrated temperature sensor VDMOS devices of the present application.

[0018] Figure 2 A schematic diagram of an array of integrated temperature sensor VDMOS devices of the present application. DETAILED DESCRIPTION

[0019] For the purposes of the present application, the technical solutions and advantages will be more clearly apparent from the following detailed description of the application, which will be made with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0020] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. "Multiple" generally includes at least two.

[0021] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0022] Reference Figure 1A , Figure 1A A schematic diagram of an integrated on-chip array temperature sensor semiconductor device of the present application. The integrated on-chip array temperature sensor semiconductor device of the present application includes a semiconductor device substrate 1 and a temperature sensor 2 directly on the semiconductor device substrate 1. The semiconductor device substrate 1 can be a vertical double diffusion metal oxide semiconductor device (VDMOS), and the temperature sensor 2 has a buried field effect transistor structure.

[0023] Specifically, the buried field effect transistor structure of the temperature sensor 2 includes a silicon nitride layer 21 directly on the VDMOS device 1, a gate electrode layer 22, a gate dielectric layer 23, a source electrode layer 24, a drain electrode layer 25, an MXene conductive channel 26 formed by femtosecond laser plasma channel marking technology ablation, and a silicon nitride protective layer 27. The MXene conductive channel 26 is composed of MXene material. The MXene conductive channel 26 as a temperature sensitive material, the chemical formula of MXene is M n+1 X n Tx where n = 1-4, M is a pre-transition metal element, such as Sc, Lu, Ti, Zr, Hf, Nb, Mo, Mn, X represents carbon (C) and / or nitrogen (N) elements, T x represent functional surface end groups and functional groups present in MXene, such as hydroxyl (-OH), oxygen (-O), and halogen elements (-F, -Cl).

[0024] The conductivity of the MXene material can vary with temperature. As the temperature increases, the resistance of the MXene material decreases. The temperature dependence of the resistance of the MXene material can change the conductive resistance between the source electrode layer 24 and the drain electrode layer 25, so that by regulating the voltage applied to the gate electrode 22, the temperature change of the VDMOS device 1 can be determined by the current value between the source electrode layer 24 and the drain electrode layer 25, so as to sensitively determine the temperature on the VDMOS device 1.

[0025] In some embodiments, the thickness of the silicon nitride (SiNx) layer 21 is 100-300 nm, for example, 200 nm, 250 nm, etc. Silicon nitride is used as an isolation layer between the VDMOS device 1 and the temperature sensor 2.

[0026] In some embodiments, the material of the gate electrode layer 22 can be chromium (Cr) or platinum (Pt). The thickness of the gate electrode layer 22 can be 10 nm or 50 nm. The material of the gate dielectric layer 23 can be SiO2 or other suitable material for forming a gate dielectric layer, and the thickness of the gate dielectric layer 23 can be 100 nm or other values.

[0027] In some embodiments, the material of the source electrode layer 24 and the drain electrode layer 25 can be chromium (Cr) or gold (Au), and the thickness of the source electrode layer 24 and the drain electrode layer 25 can be 10-20 nm or 50-100 nm. The source electrode layer 24 and the drain electrode layer 25 can be formed in the same photolithography step.

[0028] Optionally, the projection of the source electrode layer 24 and the drain electrode layer 25 on the semiconductor device does not overlap with the projection of the gate electrode layer 22 on the semiconductor device.

[0029] In some embodiments, the material of the silicon nitride protective layer 7 is Si3N4, and the thickness is 400-500 nm.

[0030] In the embodiments of the present application, the temperature sensor 2 is directly integrated on the surface of the VDMOS device 1, which can accurately reflect the working temperature of the VDMOS device 1 in real time, avoids the errors caused by the position deviation or thermal conduction delay of the related external temperature sensor, and does not need additional temperature sensor components and connection circuits, thereby reducing the manufacturing cost and complexity. As a temperature-sensitive material, the MXene conductive channel opens up a new way for the development of high-sensitivity temperature sensors 2 based on its high electron mobility, excellent electrical and thermal properties. In addition, the MXene sensitive layer is prepared by using the femtosecond laser plasma channel marking ablation technology, which is environmentally friendly and sustainable, and realizes efficient sample preparation. At the same time, the femtosecond laser plasma channel ablation technology can optimize the thickness uniformity of the MXene sensitive layer, effectively improving the sensitivity and response speed of the device.

[0031] Optionally, as shown in Figure 1B , Figure 1B is a structural schematic diagram of an example of the semiconductor device of the integrated on-chip array temperature sensor of the present application. In some examples, the VDMOS device 1 can include, from bottom to top, an N+ substrate layer 11, an N- drift layer 12, a P+ source region 13, a P-type base region 14, an N+ source region 15, a gate oxide layer 16, a polysilicon layer 17, an electrode layer 18, and a passivation layer 19. Of course, the structure of the VDMOS device 1 can also be other structures, which are not described in detail herein.

[0032] Referring to Figure 2 , Figure 2 is a structural schematic diagram of the array of the VDMOS device of the integrated temperature sensor of the present application. In the embodiments of the present application, the VDMOS device can be formed in an array structure, for example, an array formed by N×M VDMOS devices, where N and M are both positive integers greater than 1. Figure 2 An array formed by 1×3 VDMOS devices is shown in Figure 2 Although three VDMOS devices are shown in

[0033] Optionally, the area of the projection of the MXene conductive channel 26 of the temperature sensor 2 corresponding to the VDMOS device 1 on the plane where the VDMOS device 1 is located is greater than or equal to the projection of the VDMOS device 1 on the plane.

[0034] Optionally, as shown in Figure 2As shown, the source electrode layer 24, the drain electrode layer 25 and the gate electrode 22 of each temperature sensor 2 are electrically connected to the corresponding detection circuit 3. The detection circuit 3 can be configured to provide a corresponding voltage to the gate electrode 22, and detect the current flowing through the source electrode layer 24 and the drain electrode layer 25, and determine the temperature change of the corresponding VDMOS device 1 according to the current.

[0035] The arrayed layout of the present application improves the resolution and coverage of temperature monitoring, and can more comprehensively reflect the temperature distribution inside the VDMOS device 1. The buried field effect transistor structure makes the coupling between the gate and the channel more close, thereby improving the regulation efficiency of the gate on the temperature sensing device 2, and achieving fast response.

[0036] The details of this embodiment of the present application can refer to the description of the foregoing method embodiment. In order to avoid repetition, the present application will not be repeated here.

[0037] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An integrated temperature sensor semiconductor device, comprising: a semiconductor device substrate; a temperature sensor directly on the semiconductor device substrate and having a buried field effect transistor structure, wherein the buried field effect transistor structure comprises: an isolation layer directly on the semiconductor device substrate; a gate electrode on the isolation layer; a gate dielectric layer on the gate electrode layer; a source electrode and a drain electrode on the gate dielectric layer, wherein a projection of the gate electrode on the semiconductor device substrate is between a projection of the source electrode on the semiconductor device substrate and a projection of the drain electrode on the semiconductor device substrate; a temperature sensitive material layer on the gate dielectric layer, the source electrode and the drain electrode; and a protective layer on the conductive layer.

2. The semiconductor device of claim 1, wherein, The isolation layer is a silicon nitride layer having a thickness of 200 nm.

3. The semiconductor device of claim 1, wherein, Each of the source electrode and the drain electrode has a thickness of 10 nm to 20 nm or 50 nm to 100 nm.

4. The semiconductor device of claim 1, wherein, The protective layer is a silicon nitride layer having a thickness of 400 nm to 500 nm.

5. An integrated temperature sensor semiconductor device array, comprising: a plurality of semiconductor devices according to any one of claims 1 to 4; and a probing circuit configured to probe a current in the temperature sensor and determine a temperature in the semiconductor device substrate based on the current. ​

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