Semiconductor device
By designing an asymmetric structure in semiconductor devices and using the PN junction between the source region and the bulk contact region for isolation, the problems of punch-through risk and increased cost of medium-voltage devices under the shrinking Moore's Law have been solved, achieving a dual reduction in area and cost.
Patent Information
- Application Number
- CN202520629987.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-04-03
AI Technical Summary
As Moore's Law shrinks feature size, the punch-through risk of medium-voltage devices increases, and manufacturing costs cannot be reduced by shrinking device feature size.
By designing asymmetric structures in semiconductor devices, isolation is achieved using the PN junction between the source region and the body contact region, reducing the use of shallow trench isolation structures. Combining deep well and shallow trench isolation structures ensures isolation capability and withstand voltage characteristics.
While ensuring isolation and withstand voltage characteristics, the area of semiconductor devices is reduced, costs are lowered, punch-through risk is reduced, and the negative impact of feature size reduction is avoided.
Smart Images
Figure CN223957885U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, especially relates to a semiconductor device. BACKGROUND
[0002] With the device feature size constantly according to Moore's law reduces, the area of single chip will also reduce, the chip number on single wafer manufacture increases, and the cost of chip manufacture will also reduce along with the evolution of Moore's law, but some kinds of chips cannot reduce the manufacturing cost according to the evolution of Moore's law due to the restriction of use scene.
[0003] Taking the medium voltage device (MV Device) in DDIC (Display Driver IC, display driver IC) chip as an example, the medium voltage device needs to bear higher voltage (for example 8V) as the source driver, and if the feature size is blindly reduced (for example the length and width of the gate are reduced) according to Moore's law, the risk of punchthrough of the medium voltage device will increase. Therefore, it is particularly important to develop a method for obtaining chip area benefit without reducing the device feature size. SUMMARY
[0004] The utility model discloses a semiconductor device, which can reduce the area of the semiconductor device while ensuring the isolation capability.
[0005] To achieve the above object, the utility model provides a semiconductor device, which comprises:
[0006] a substrate;
[0007] a body region extending from the top surface of the substrate into the substrate;
[0008] a gate structure located on the top surface of the body region;
[0009] a source region and a drain region located in the body region on both sides of the gate structure respectively, and the doping type of the source region and the drain region is opposite to that of the body region;
[0010] a first body contact region and a second body contact region located in the body region on the side away from the gate structure of the source region and the drain region respectively, the source region is in contact with the first body contact region, a first shallow trench isolation structure is formed between the drain region and the second body contact region, and the doping type of the first body contact region and the second body contact region is the same as that of the body region.
[0011] Optionally, the semiconductor device further comprises:
[0012] a first lightly-doped source region and a first lightly-doped drain region in the body region on both sides of the gate structure, and the first lightly-doped source region and the first lightly-doped drain region each extend to a part of the bottom surface of the gate structure, and the doping type of the first lightly-doped source region and the first lightly-doped drain region is opposite to the doping type of the body region.
[0013] Optionally, the first lightly-doped source region and the first lightly-doped drain region each extend from the bottom surface of the gate structure to the bottom surface of the source region and the drain region respectively.
[0014] Optionally, the semiconductor device further comprises:
[0015] a second lightly-doped source region in the body region at the bottom surface of the first body contact region, the second lightly-doped source region is in contact with the first lightly-doped source region, and the doping type of the second lightly-doped source region is opposite to the doping type of the first lightly-doped source region.
[0016] Optionally, the doping concentration of the second lightly-doped source region is lower than the doping concentration of the first body contact region.
[0017] Optionally, the doping concentration of the first lightly-doped source region and the first lightly-doped drain region is respectively lower than the doping concentration of the source region and the drain region respectively.
[0018] Optionally, the depth of the first shallow trench isolation structure is greater than the depth of the drain region, the second body contact region and the first lightly-doped drain region and is less than the depth of the body region.
[0019] Optionally, the semiconductor device further comprises:
[0020] a deep well region extending into the substrate from the top surface of the substrate, and the deep well region encloses the body region, and the doping type of the deep well region is opposite to the doping type of the body region.
[0021] Optionally, the semiconductor device further comprises:
[0022] a second shallow trench isolation structure extending into the substrate from the top surface of the substrate, and the second shallow trench isolation structure is between the deep well region and the body region.
[0023] Optionally, the depth of the second shallow trench isolation structure is greater than the depth of the source region, the drain region, the first lightly-doped source region, the first lightly-doped drain region, the first body contact region and the second body contact region and is less than the depth of the body region.
[0024] Compared with the prior art, the semiconductor device has the advantages that the source region and the first body contact region are in contact, the doping type of the source region and the first body contact region is opposite, isolation between the source region and the first body contact region is realized through a PN junction formed between the source region and the first body contact region, the source region and the first body contact region do not need to be isolated through the first shallow trench isolation structure, the semiconductor device has an area benefit of a width of the first shallow trench isolation structure, while the isolation capability and the voltage resistance characteristic are ensured, the area of the semiconductor device is reduced, the total area of the chip is reduced, and the cost is reduced; and the area of the semiconductor device is reduced without reducing the feature size of the semiconductor device, and the risk of the semiconductor device being penetrated is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0025] Fig. 1 is a structural schematic view of a semiconductor device of an embodiment of the utility model;
[0026] Fig. 2 is a structural schematic view of a semiconductor device of another embodiment of the utility model.
[0027] Among them, the attached Figs. 1-2 The attached reference signs are explained as follows:
[0028] 10-substrate; 11-deep well region; 12-body region; 13-gate structure; 131-gate dielectric layer; 132-gate layer; 141-source region; 142-drain region; 151-first lightly doped source region; 152-first lightly doped drain region; 161-first body contact region; 162-second body contact region; 17-second lightly doped source region; 18-first shallow trench isolation structure; 19-second shallow trench isolation structure. DETAILED DESCRIPTION
[0029] In order to make the purpose, advantages and characteristics of the utility model more clear, the semiconductor device proposed by the utility model is further described in detail below. It should be noted that the drawings are all very simplified and use non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0030] The utility model discloses an embodiment provides a kind of semiconductor devices, comprising: substrate;Body area, from the substrate top surface extends to the substrate inside;Gate structure, located the body area top surface;Source region and drain region, respectively in the body area on the two sides of the gate structure, the doping type of the source region and the drain region is opposite with the doping type of the body area;First body contact area and second body contact area, respectively corresponding in the body area on the side of the source region and the drain region away from the gate structure, the source region is contacted with the first body contact area, the first shallow trench isolation structure is formed between the drain region and the second body contact area, the doping type of the first body contact area and the second body contact area is same with the doping type of the body area.
[0031] Reference is made below Figs. 1-2 More detailed introduction is provided to the semiconductor device of the embodiment, Figs. 1-2 It is the profile schematic diagram of device.
[0032] The substrate 10 can be composed of any appropriate semiconductor material, including but not limited to: silicon, germanium, silicon germanium, silicon carbon germanium, silicon carbide and other semiconductors.
[0033] The body area 12 extends from the substrate 10 top surface to the substrate 10 inside.
[0034] The doping type of the substrate 10 is opposite with the doping type of the body area 12.
[0035] The gate structure 13 is located the body area 12 top surface.
[0036] The gate structure 13 includes from bottom to top stacked gate dielectric layer 131 and gate layer 132.
[0037] The gate dielectric layer 131 can be single-layer structure or at least two-layer stacked structure.
[0038] The material of the gate dielectric layer 131 can be at least one of insulating material such as silicon oxide, silicon oxynitride and silicon nitride, and the material of the gate layer 132 can be polysilicon or metal.
[0039] The sidewall of the gate structure 13 can also be formed with side wall (not shown).
[0040] The source region 141 and the drain region 142 are respectively located in the body area 12 on the two sides of the gate structure 13, and the doping type of the source region 141 and the drain region 142 is opposite with the doping type of the body area 12.
[0041] The source region 141 and the drain region 142 have the same depth, and the source region 141 and the drain region 142 have the same doping concentration, i.e., the source region 141 and the drain region 142 are formed by the same process.
[0042] The source region 141 and the drain region 142 can respectively extend from one side of the gate structure 13 away from the side wall to at least a part of the bottom surface of the side wall, or the source region 141 and the drain region 142 can respectively extend from one side of the gate structure 13 away from the side wall through the bottom surface of the side wall to a part of the bottom surface of the gate structure 13.
[0043] The first body contact region 161 and the second body contact region 162 are respectively located in the body region 12 on one side of the source region 141 and the drain region 142 away from the gate structure 13, the source region 141 is in contact with the first body contact region 161, and the drain region 142 is in contact with the second body contact region 162, and a first shallow trench isolation structure 18 is formed between the first body contact region 161 and the second body contact region 162, and the first body contact region 161 and the second body contact region 162 have the same doping type as the body region 12.
[0044] Since the source region 141 is in contact with the first body contact region 161, and the doping type of the source region 141 is opposite to the doping type of the first body contact region 161, a PN junction is formed between the source region 141 and the first body contact region 161.
[0045] The first body contact region 161 and the second body contact region 162 have the same depth, and the first body contact region 161 and the second body contact region 162 have the same doping concentration, i.e., the first body contact region 161 and the second body contact region 162 are formed by the same process.
[0046] The depth of the first body contact region 161 can be greater than, less than, or equal to the depth of the source region 141, and the depth of the second body contact region 162 can be greater than, less than, or equal to the depth of the drain region 142.
[0047] The doping concentration of the first body contact region 161 and the second body contact region 162 is greater than the doping concentration of the body region 12, and the first body contact region 161 and the second body contact region 162 are used to lead out the body region 12.
[0048] The semiconductor device further comprises: a first lightly-doped source region 151 and a first lightly-doped drain region 152 in the body region 12 on both sides of the gate structure 13, and the first lightly-doped source region 151 and the first lightly-doped drain region 152 both extend to part of the bottom surface of the gate structure 13, and the doping type of the first lightly-doped source region 151 and the first lightly-doped drain region 152 is opposite to the doping type of the body region 12.
[0049] The depth of the first lightly-doped source region 151 and the first lightly-doped drain region 152 is the same, and the doping concentration of the first lightly-doped source region 151 and the first lightly-doped drain region 152 is the same, that is, the first lightly-doped source region 151 and the first lightly-doped drain region 152 are formed by the same process.
[0050] The depth of the first lightly-doped source region 151 and the first lightly-doped drain region 152 can be greater than, less than, or equal to the depth of the source region 141 and the drain region 142, respectively.
[0051] In an embodiment, as shown in Fig. 1 and Fig. 2 The first lightly-doped source region 151 and the first lightly-doped drain region 152 extend from the bottom surface of the gate structure 13 to the bottom surface of the source region 141 and the drain region 142, respectively, that is, the first lightly-doped source region 151 extends from the bottom surface of the gate structure 13 to the bottom surface of the source region 141 through the side of the source region 141 close to the gate structure 13, and the first lightly-doped drain region 152 extends from the bottom surface of the gate structure 13 to the bottom surface of the drain region 142 through the side of the drain region 142 close to the gate structure 13.
[0052] In another embodiment, the first lightly-doped source region 151 and the first lightly-doped drain region 152 extend from the bottom surface of the gate structure 13 to the side of the source region 141 and the drain region 142 close to the gate structure 13, respectively, and the first lightly-doped source region 151 is in contact with the side of the source region 141 close to the gate structure 13, and the first lightly-doped drain region 152 is in contact with the side of the drain region 142 close to the gate structure 13.
[0053] The doping concentration of the first lightly-doped source region 151 and the first lightly-doped drain region 152 is lower than the doping concentration of the source region 141 and the drain region 142, respectively.
[0054] The first body contact region 161 can be in contact with the first lightly-doped source region 151 extending to the bottom surface of the source region 141 or not in contact, and the second body contact region 162 is not in contact with the first lightly-doped drain region 152 extending to the bottom surface of the drain region 142.
[0055] The first shallow trench isolation structure 18 has a depth greater than that of the drain region 142, the second body contact region 162 and the first lightly doped drain region 152 and less than that of the body region 12, so that the drain region 142 and the first lightly doped drain region 152 can be isolated from the second body contact region 162 by the first shallow trench isolation structure 18.
[0056] Preferably, as shown in Fig. 1, the semiconductor device further comprises a second lightly doped source region 17 in the body region 12 at the bottom surface of the first body contact region 161, the second lightly doped source region 17 being in contact with the first lightly doped source region 151 extending to the bottom surface of the source region 141, the second lightly doped source region 17 having a doping type opposite to that of the first lightly doped source region 151, so that a PN junction is formed between the second lightly doped source region 17 and the first lightly doped source region 151. Fig. 2
[0057] The second lightly doped source region 17 has a doping concentration lower than that of the first body contact region 161.
[0058] The bottom surface of the second lightly doped source region 17 can be higher than, lower than or flush with that of the first lightly doped source region 151.
[0059] The semiconductor device further comprises a deep well region 11 extending from the top surface of the substrate 10 into the substrate 10 and wrapping the body region 12, the deep well region 11 having a doping type opposite to that of the body region 12.
[0060] When the source region 141, the drain region 142, the first lightly doped source region 151, the first lightly doped drain region 152 and the deep well region 11 have an N-type doping type, the first body contact region 161, the second body contact region 162, the second lightly doped source region 17 and the body region 12 have a P-type doping type; when the source region 141, the drain region 142, the first lightly doped source region 151, the first lightly doped drain region 152 and the deep well region 11 have a P-type doping type, the first body contact region 161, the second body contact region 162, the second lightly doped source region 17 and the body region 12 have an N-type doping type.
[0061] Since the doping type of the deep well region 11 is opposite to that of the body region 12, a PN junction is formed between the deep well region 11 and the body region 12 to isolate the substrate noise while preventing carrier injection into the substrate 10; and since the doping type of the substrate 10 is the same as that of the body region 12, a P-N-P structure or an N-P-N structure is formed between the substrate 10, the deep well region 11 and the body region 12, bidirectional isolation is realized through a reverse-biased PN junction, and the latch-up effect is inhibited.
[0062] The semiconductor device further comprises a second shallow trench isolation structure 19 extending from the top surface of the substrate 10 into the substrate 10, and the second shallow trench isolation structure 19 is located between the deep well region 11 and the body region 12.
[0063] The second shallow trench isolation structure 19 surrounds the source region 141, the drain region 142, the first lightly doped source region 151, the first lightly doped drain region 152, the first body contact region 161, the second body contact region 162, the second lightly doped source region 17 and the first shallow trench isolation structure 18.
[0064] The depth of the second shallow trench isolation structure 19 is greater than that of the source region 141, the drain region 142, the first lightly doped source region 151, the first lightly doped drain region 152, the second lightly doped source region 17, the first body contact region 161 and the second body contact region 162 and is less than that of the body region 12.
[0065] Preferably, the depth of the first shallow trench isolation structure 18 is the same as that of the second shallow trench isolation structure 19, and the material of the first shallow trench isolation structure 18 is the same as that of the second shallow trench isolation structure 19, that is, the first shallow trench isolation structure 18 and the second shallow trench isolation structure 19 are formed by the same process to simplify the process steps.
[0066] The second shallow trench isolation structure 19 can further block possible longitudinal leakage paths (such as carrier injection into the substrate 10) to improve isolation reliability; and the second shallow trench isolation structure 19 can further inhibit the latch-up effect.
[0067] In the existing semiconductor device, not only the isolation between the drain region 142 and the second body contact region 162 is realized by the first shallow trench isolation structure 18, but also the isolation between the source region 141 and the first body contact region 161 is realized by the first shallow trench isolation structure 18, that is, the semiconductor device is a symmetric structure; if the characteristic size of the semiconductor device is reduced according to Moore's law, the risk of punch through of the semiconductor device will be increased. For example, when the length of the gate structure 13 (that is, the length of the gate structure 13 in the direction from the source region 141 to the drain region 142) is reduced, the distance between the source region 141 and the drain region 142 and the distance between the first lightly doped source region 151 and the first lightly doped drain region 152 will be reduced, and then the depletion region will be expanded from the drain to the source in the working state (that is, in the pressurized state), that is, the depletion region is laterally expanded to directly connect the drain and the source, the electric field penetrates through the entire channel region, and then the device loses the blocking ability, the current increases sharply, and thus the failure is caused.
[0068] Since the source region 141 and the first body contact region 161 are grounded and the drain region 142 is connected to a positive voltage (that is, VDD) in the working state, the working voltage borne by the source region 141 and the first body contact region 161 is low, so that the isolation requirement between the source region 141 and the first body contact region 161 is low; and the working voltage borne by the drain region 142 and the second body contact region 162 is high, so that the isolation requirement between the drain region 142 and the second body contact region 162 is high. Therefore, in the semiconductor device provided by the utility model, by contacting the source region 141 and the first body contact region 161, the isolation between the source region 141 and the first body contact region 161 can be realized by the PN junction formed between the source region 141 and the first body contact region 161, and the isolation between the source region 141 and the first body contact region 161 does not need to be realized by forming the first shallow trench isolation structure 18; and the isolation between the drain region 142 and the second body contact region 162 is still realized by forming the first shallow trench isolation structure 18, so as to ensure the isolation effect.
[0069] Therefore, in the semiconductor device provided by the utility model, the first shallow trench isolation structure 18 between the source region 141 and the first body contact region 161 is removed, the semiconductor device is changed from the existing symmetric structure to an asymmetric structure, an area benefit of the width of the first shallow trench isolation structure 18 is obtained, the area of the semiconductor device is reduced while the isolation ability and the voltage resistance characteristic are ensured, the total area of the chip is reduced, and the cost is reduced; and the area of the semiconductor device is reduced without reducing the characteristic size of the semiconductor device, so as to reduce the risk of punch through of the semiconductor device.
[0070] The width and depth of the PN junction formed between the source region 141 and the first body contact region 161 can be adjusted by adjusting the doping concentration, depth and other parameters of the source region 141 and the first body contact region 161, thereby optimizing the isolation effect.
[0071] When the semiconductor device further comprises the second lightly doped source region 17, a PN junction is formed between the second lightly doped source region 17 and the first lightly doped source region 151, so that the depth of the PN junction for isolation is increased, thereby increasing the isolation effect.
[0072] The semiconductor device can be a medium-voltage device, a low-voltage device and a high-voltage device.
[0073] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; The body region extends from the top surface of the substrate into the substrate; A gate structure is located on the top surface of the body region; The source region and the drain region are located in the body regions on both sides of the gate structure, and the doping type of the source region and the drain region is opposite to that of the body region. The first body contact region and the second body contact region are respectively located in the body region on the side of the source region and the drain region away from the gate structure. The source region is in contact with the first body contact region, and a first shallow trench isolation structure is formed between the drain region and the second body contact region. The doping type of the first body contact region and the second body contact region is the same as the doping type of the body region.
2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: The first lightly doped source region and the first lightly doped drain region are respectively located in the body regions on both sides of the gate structure, and the first lightly doped source region and the first lightly doped drain region both extend to a portion of the bottom surface of the gate structure. The doping type of the first lightly doped source region and the first lightly doped drain region is opposite to the doping type of the body region.
3. The semiconductor device as described in claim 2, characterized in that, The first lightly doped source region and the first lightly doped drain region extend from the bottom surface of the gate structure to the bottom surface of the source region and the drain region, respectively.
4. The semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes: The second lightly doped source region is located in the body region at the bottom of the first body contact region. The second lightly doped source region is in contact with the first lightly doped source region, and the doping type of the second lightly doped source region is opposite to that of the first lightly doped source region.
5. The semiconductor device as claimed in claim 4, characterized in that, The doping concentration of the second lightly doped source region is lower than the doping concentration of the first body contact region.
6. The semiconductor device as claimed in claim 2, characterized in that, The doping concentrations of the first lightly doped source region and the first lightly doped drain region are respectively lower than the doping concentrations of the source region and the drain region.
7. The semiconductor device as claimed in claim 2, characterized in that, The depth of the first shallow trench isolation structure is greater than the depth of the drain region, the second body contact region and the first lightly doped drain region and less than the depth of the body region.
8. The semiconductor device as claimed in claim 2, characterized in that, The semiconductor device further includes: A deep well region extends from the top surface of the substrate into the substrate and encloses the body region, and the deep well region has the opposite doping type to the body region.
9. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor device further includes: A second shallow trench isolation structure extends from the top surface of the substrate into the substrate, and the second shallow trench isolation structure is located between the deep well region and the body region.
10. The semiconductor device as claimed in claim 9, characterized in that, The depth of the second shallow trench isolation structure is greater than the depth of the source region, the drain region, the first lightly doped source region, the first lightly doped drain region, the first body contact region, and the second body contact region, but less than the depth of the body region.