Semiconductor device structure

Abstract

Embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes first and second source / drain regions disposed on a substrate, and an isolation region disposed between the first and second source / drain regions. The isolation region includes a first top surface having an inclined portion and a flat portion, and a portion of the isolation region between the inclined portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height. The width is greater than the height. The semiconductor device structure further includes a plurality of semiconductor layers disposed adjacent the first and second source / drain regions, a gate electrode layer surrounding a portion of each of the semiconductor layers, and a spacer disposed between the gate electrode layer and the first source / drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each designed to improve processing performance, increase capacity, and reduce cost of the IC. In general, the semiconductor manufacturing process has been a driving force behind the increase in performance and capacity of ICs. These improvements in IC design and manufacturing have resulted in higher performance and greater capacity at lower cost.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. SUMMARY

[0004] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region and a second source / drain region disposed on a substrate, and an isolation region disposed between the first source / drain region and the second source / drain region. The isolation region includes a first top surface having a sloped portion and a flat portion, and a portion of the isolation region between the sloped portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height. The width is greater than the height. The semiconductor device structure further includes a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a spacer disposed between the gate electrode layer and the first source / drain region.

[0005] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed on a first substrate portion, a second source / drain region disposed on a second substrate portion, a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and an isolation region. The isolation region includes a first top surface between the first substrate portion and the second substrate portion, and a second top surface below the gate electrode layer. The first top surface has a U-shaped profile, and the second top surface has a flat profile.

[0006] Yet other embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed on a first substrate portion, a second source / drain region disposed on a second substrate portion, a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and an isolation region. The isolation region includes a first top surface between the first substrate portion and the second substrate portion and a second top surface below the gate electrode layer. The first top surface has a U-shaped profile and the second top surface has a flat profile, wherein the first top surface forms an angle with respect to a side surface of the first substrate portion, the angle ranging from 105 degrees to 130 degrees. BRIEF DESCRIPTION OF DRAWINGS

[0007] The various features illustrated are set forth in detail in connection with the following detailed description. Note that the various features are not necessarily drawn to scale. Rather, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. Skilled artisans recognize the patents or applications filed by the same assignee, and to be assigned to the same assignee, as the present patent application have a proper technical scope based on their disclosures.

[0008] Figures 1 to 6 perspective views of various stages in the fabrication of a semiconductor device structure in accordance with some embodiments;

[0009] Figure 7 cross-sectional top view of a semiconductor device structure taken along line Figure 6 A-A thereof in accordance with some embodiments;

[0010] Figures 8 to 12 perspective views of various stages in the fabrication of a semiconductor device structure in accordance with some embodiments;

[0011] Figure 13 cross-sectional top view of a semiconductor device structure taken along line Figure 12 B-B thereof in accordance with some embodiments;

[0012] Figures 14 to 16 perspective views of various stages in the fabrication of a semiconductor device structure in accordance with some embodiments;

[0013] Figure 17 cross-sectional top view of a semiconductor device structure taken along line Figure 16 C-C thereof in accordance with some embodiments.

[0014] KEY

[0015] 100: semiconductor device structure

[0016] 101: substrate

[0017] 103: first sacrificial layer

[0018] 104: semiconductor layer

[0019] 105: second sacrificial layer

[0020] 106: first semiconductor layer

[0021] 108: second semiconductor layer

[0022] 110: oxide layer

[0023] 111: nitride layer

[0024] 112: fin structure

[0025] 113: flat portion

[0026] 114: trench

[0027] 115: sloped portion

[0028] 116: substrate portion

[0029] 118: insulating material

[0030] 119: top surface

[0031] 119c: top surface

[0032] 120: isolation region

[0033] 121: native oxide layer

[0034] 130: sacrificial gate structure

[0035] 132: sacrificial gate dielectric layer

[0036] 134: sacrificial gate electrode layer

[0037] 135: oxide layer

[0038] 136: mask structure

[0039] 137: nitride layer

[0040] 139: planar

[0041] 140: spacer

[0042] 140a: first portion

[0043] 140b: second portion

[0044] 144: dielectric spacer

[0045] 146: S / D region

[0046] 162: contact etch stop layer (CESL)

[0047] 163: interlayer dielectric (ILD) layer

[0048] 168: interface layer

[0049] 170: gate dielectric layer

[0050] 172: gate electrode layer

[0051] A: angle

[0052] A-A, B-B, C-C: line

[0053] D1, D2, D3: distance

[0054] H: height

[0055] W: width

[0056] X, Y, Z: direction DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. Each of the following described embodiments and / or examples and what is described in connection therewith can be implemented as method, apparatus, system, program, and / or article of manufacture, among other examples. The following descriptions and examples are presented to provide details on certain features and implementations. However, it should be understood that each of the

[0058] Furthermore, spatial or directional terms, such as "below," "above," "lower," "upper," "up," "down," "top," "bottom," and the like can be used in this disclosure to describe the relative relationship between one element or feature and another element or feature as illustrated in the figures. The spatial or directional terms are used for purposes of clarity and convenience in understanding the descriptions and examples presented herein. It should be understood that the spatial or directional terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional descriptions used herein can be interpreted accordingly.

[0059] Embodiments of the disclosure provide a semiconductor device structure including an isolation region having a tilted top surface. As a result, there is no residue of the sacrificial gate electrode layer, thereby reducing gate electrode layer defects.

[0060] While the embodiments of this disclosure discuss nanostructured channel FETs, such as horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and forksheet FETs, implementations of certain forms of this disclosure can be used with other processes and / or other devices, such as FinFETs, planar FETs, and other suitable devices. Other modifications that may be considered within the scope of this disclosure will be readily apparent to those skilled in the art. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern these structures, including dual-patterning processes or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography processes and self-alignment processes to allow the creation of patterns, for example, patterns with a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the GAA structure.

[0061] Figures 1 to 17 This illustration depicts an exemplary method for manufacturing a semiconductor device structure 100 according to embodiments of this disclosure. It will be understood that... Figures 1 to 17 Additional operations may be provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limited and is interchangeable.

[0062] Figures 1 to 6 This is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate, wherein an insulating layer (not shown) is disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer.

[0063] The substrate 101 can include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants can be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0064] The semiconductor layer 104 stack includes alternating semiconductor layers made of different materials to facilitate formation of a nanostructured channel in a multi-gate device, such as a nanostructured channel FET. In some embodiments, the semiconductor layer 104 stack includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer 104 stack includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some embodiments, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, either of the first and second semiconductor layers 106, 108 can be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0065] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the layers of the semiconductor layer 104 stack can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0066] The first semiconductor layers 106, or portions thereof, can form nanosheet channels of the semiconductor device structure 100 at a subsequent fabrication stage. The term nanosheet is used herein to designate any material portion having a nanoscale, or even a microscale, dimension and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to both circular and substantially circular cross-sectional elongated material portions, as well as beam-like or strip-like material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channels of the semiconductor device structure 100 can be surrounded by gate electrodes. The semiconductor device structure 100 can include nanosheet transistors. The nanosheet transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode around a channel. The use of the first semiconductor layers 106 to define one or more channels of the semiconductor device structure 100 is discussed further below.

[0067] The thickness of each first semiconductor layer 106 can be in a range from about 5 nm to about 30 nm, such as about 15 nm. The thickness of each second semiconductor layer 108 can be equal to, less than, or greater than the thickness of the first semiconductor layers 106. In some embodiments, the thickness of each second semiconductor layer 108 is in a range from about 2 nm to about 50 nm. As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged in an alternating fashion, which is for illustrative purposes and is not intended to limit the specific description in the application scope. It can be appreciated that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer 104 stack, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. As shown, the first semiconductor layers 106 and the second semiconductor layers 108 are arranged in a stack. Figure 1 Figure 1 As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 can be silicon oxide and can have a different etch selectivity compared to the nitride layer 111. The nitride layer 111 can include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 can be a mask structure.

[0068] At Figure 2 ​In this embodiment, fin structures 112 are formed by stacking semiconductor layers 104. Each fin structure 112 has an upper portion including first and second semiconductor layers 106, 108 and a substrate portion 116 formed by a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer, such as an oxide layer 110 and a nitride layer 111, formed on the stack of semiconductor layers 104 using multiple patterning operations including lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) on the hard mask layer; exposing the photoresist layer on the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam lithography process can be used to pattern the photoresist layer to form the mask element. The etching process forms trenches 114 in unprotected areas, through a hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving multiple extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114.

[0069] exist Figure 3 In this process, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0070] exist Figure 4In some embodiments, the insulating material 118 is recessed to form isolation regions 120. The recessing of the insulating material 118 exposes portions of the fin structures 112, such as the semiconductor layer 104 stack. The recessing of the insulating material 118 exposes the trenches 114 between adjacent fin structures 112. The isolation regions 120 can be formed using a suitable process, such as a dry etch process, a wet etch process, or a combination thereof. In some embodiments, a dry etch process is performed to recess the insulating material 118. For example, the dry etch process utilizes an etchant, such as NH3, NF3, HBr, H2, or a combination thereof. In some embodiments, the dry etch process also utilizes a passivation gas to enhance selectivity, and the passivation gas includes N2, O2, or a combination thereof. With the addition of the passivation gas in the dry etch process, the dry etch process etches the dielectric material of the insulating material 118 without substantially affecting the semiconductor material of the first semiconductor layer 106 and the second semiconductor layer 108. The gas flow rate of the etchant and the passivation gas is in a range from about 20 standard cubic centimeters (seem) to about 3000 seem. The plasma power of the dry etch process is in a range from about 10 W to about 4000 W, and the processing pressure can be in a range from about 10 mTorr to about 3 Torr.

[0071] In some embodiments, a bias voltage is applied during the dry etch process to pull ions toward the substrate 101. As a result, the top surface of the insulating material 118 is substantially planar. In some embodiments, no bias voltage is applied during the dry etch process, and the top surface 119 of the insulating material 118 is sloped, as shown in FIG. 1C. The sloped top surface 119 can result in no residue for the subsequently formed sacrificial gate electrode layer 134 (described below), which can reduce gate electrode defects. In some embodiments, a native oxide layer 121 is formed on the semiconductor layer 104 stack. The native oxide layer 121 can be a result of the semiconductor layer 104 stack oxidizing when the semiconductor device structure 100 is exposed to the atmosphere, such as when the substrate is transferred from one processing chamber to another processing chamber. In some embodiments, the substrate is transferred within a cluster tool from one processing chamber to another processing chamber, and no native oxide layer is formed. In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recessing of the insulating material 118. Figure 4 Figure 5 In some embodiments, a native oxide layer 121 is formed on the semiconductor layer 104 stack. The native oxide layer 121 can be a result of the semiconductor layer 104 stack oxidizing when the semiconductor device structure 100 is exposed to the atmosphere, such as when the substrate is transferred from one processing chamber to another processing chamber. In some embodiments, the substrate is transferred within a cluster tool from one processing chamber to another processing chamber, and no native oxide layer is formed. In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recessing of the insulating material 118.

[0072] In some embodiments, a native oxide layer 121 is formed on the semiconductor layer 104 stack. The native oxide layer 121 can be a result of the semiconductor layer 104 stack oxidizing when the semiconductor device structure 100 is exposed to the atmosphere, such as when the substrate is transferred from one processing chamber to another processing chamber. In some embodiments, the substrate is transferred within a cluster tool from one processing chamber to another processing chamber, and no native oxide layer is formed. In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recessing of the insulating material 118. Figure 5 ​In this embodiment, a first sacrificial layer 103 is formed on the exposed surface of the semiconductor device structure 100, and a second sacrificial layer 105 is formed on the first sacrificial layer 103. In some embodiments, the first sacrificial layer 103 comprises a dielectric material, such as an oxide, for example, silicon oxide. The first sacrificial layer 103 can be formed by any suitable process, such as CVD or PECVD. In some embodiments, the first sacrificial layer 103 is a conformal layer formed by a conformal process, such as atomic layer deposition (ALD). In some embodiments, the second sacrificial layer 105 comprises a semiconductor material, such as polysilicon. The second sacrificial layer 105 can be formed by any suitable process, such as CVD, PECVD, ALD, or PVD. The second sacrificial layer 105 may first be deposited to embed the fin structure 112, and then subjected to a planarization process, such as a CMP process. Figure 5 As shown. In some embodiments, the thickness of the second sacrificial layer 105 in the Z direction ranges from about 100 nm to about 200 nm.

[0073] exist Figure 6 In this process, a mask structure 136 is formed on the second sacrificial layer 105, and the mask structure 136 is used to pattern the second sacrificial layer 105 to form one or more sacrificial gate electrode layers 134. In some embodiments, the mask structure 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The patterning process includes lithography (e.g., lithography or electron beam lithography), and may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., centrifugal dehydration and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, patterning further includes an etching process, which may include dry etching (e.g., RIE etching), wet etching, other etching methods and / or combinations thereof. In some embodiments, the etching process is an anisotropic dry etching process using a chlorine-based etchant. In some embodiments, other etchants, such as HBr and / or oxygen-containing etchants, may be used. In anisotropic dry etching processes, in addition to the etchant, a carrier gas or rarefied gas, such as Ar, N2, or He, can also be used. The first sacrificial layer 103 is also patterned to form the sacrificial gate dielectric layer 132, as shown below. Figure 6 As shown. The sacrificial gate dielectric layer 132 and the sacrificial gate electrode layer 134 can form a sacrificial gate structure 130.

[0074] In some embodiments, the top surface of the isolation region 120 is substantially flat. As a result, the residue of the second sacrificial layer 105 can form at the corners, such as on the top of the topmost first semiconductor layer 106 and the adjacent bottom second semiconductor layer 108. In other words, the side surface of the sacrificial gate electrode layer 134 includes protrusions. After the gate replacement process, the gate electrode layer will also include these protrusions. As a result, electrical shorting between the gate electrode layer and the source / drain regions can occur. To prevent the formation of protrusions, the sloped top surface 119 of the isolation region 120 is formed. It has been observed that when the top surface 119 of the isolation region 120 is sloped, as shown in Figure 6 , the sacrificial gate electrode layer 134 does not have protrusions. In other words, the side surface of the sacrificial gate electrode layer 134 is substantially flat.

[0075] Figure 7 A cross-sectional side view of the semiconductor device structure 100 taken along the A-A line of Figure 6 , according to some embodiments. As shown in Figure 7 , the top surface 119 of the isolation region 120 includes a substantially flat portion 113 and a sloped portion 115. The sloped portion 115 extends from a substrate portion 116. The sloped portion 115 forms an angle A with respect to the side surface of the substrate portion 116. In some embodiments, the angle A is an obtuse angle ranging from about 105 degrees to about 130 degrees. The portion of the isolation region 120 from the flat portion 113 of the top surface 119 to the sloped portion 115 defines a plane 139 having a height H in the Z direction and a width W in the Y direction. In some embodiments, the height H ranges from about 10 nm to about 15 nm, and the width W ranges from about 10 nm to about 15 nm. In some embodiments, the width W is greater than the height H. As shown in Figure 7 , the highest point of the isolation region 120 in the Z direction is a distance Dl from the bottom surface of the bottommost second semiconductor layer 108, a distance D2 from the bottom surface of the middle second semiconductor layer 108, and a distance D3 from the bottom surface of the topmost second semiconductor layer 108. In some embodiments, the distance Dl ranges from about 3 nm to about 6 nm, the distance D2 ranges from about 33 nm to about 36 nm, and the distance D3 ranges from about 63 nm to about 66 nm. In some embodiments, the distance Dl ranges from about 3 nm to about 6 nm, the distance D2 ranges from about 18 nm to about 21 nm, and the distance D3 ranges from about 33 nm to about 36 nm.

[0076] Figures 8 to 12 Perspective views of various stages of fabricating the semiconductor device structure 100, according to some embodiments. As shown in Figure 8As shown, a spacer layer 138 is formed to cover the exposed portions of the sacrificial gate structure 130, the fin structure 112, and the isolation region 120. The spacer layer 138 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiOCN, and / or combinations thereof. In some embodiments, the spacer layer 138 is formed by a conformal process, such as atomic layer deposition (ALD). In some embodiments, the thickness of the spacer layer 138 ranges from about 2 nm to about 10 nm.

[0077] like Figure 9 As shown, one or more etching processes are performed to recess portions of the fin structure 112 not covered by the sacrificial gate structure 130 and to remove portions of the spacer layer 138. In some embodiments, portions of the spacer layer 138 formed on top of portions of the fin structure 112 not covered by the sacrificial gate structure 130 are removed to expose portions of the fin structure 112 not covered by the sacrificial gate structure 130. Then, the exposed portions of the fin structure 112 not covered by the sacrificial gate structure 130 are recessed to expose the substrate portion 116, as shown. Figure 9 As shown. In some embodiments, a mask (not shown) may be used to protect a portion of the spacer layer 138 formed on the isolation region 120, so that the portion of the spacer layer 138 formed on the isolation region 120 is not removed. In some embodiments, the mask is absent, and the portion of the spacer layer 138 formed on the isolation region 120 is also removed. The portion of the spacer layer 138 formed on the mask structure 136 may also be removed. One or more etching processes may include dry etching, such as RIE, NBE, etc., and / or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH). One or more etching processes form the spacer 140, including a first portion 140a formed on the sidewall of the sacrificial gate electrode layer 134 and a second portion 140b formed on the isolation region 120 not covered by the sacrificial gate structure 130. As mentioned above, in some embodiments, the second portion 140b may not be present. In some embodiments, the spacer 140 comprises a single layer, such as Figure 9 As shown. In some embodiments, the spacer 140 comprises two or more layers, such as Figure 13 and Figure 17 As shown.

[0078] like Figure 10As shown, the edge portions of each second semiconductor layer 108 of the semiconductor layer 104 stack are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144, such as... Figure 10 As shown. The dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), and then anisotropically etching to remove a portion of the conformal dielectric layer outside the dielectric spacers 144. The dielectric spacers 144 are protected by a first semiconductor layer 106 during the anisotropic etching process. The remaining second semiconductor layer 108 covers the spacers 144 along the X direction.

[0079] like Figure 11 As shown, the source / drain (S / D) region 146 is formed from the substrate portion 116. The S / D region 146 can be grown vertically and horizontally to form facets that correspond to the crystal planes of the material used for the substrate portion 116. In this disclosure, the source region and drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain region can refer to the source / drain individually or collectively, depending on the context. The S / D region 146 can consist of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or one or more layers of Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, p-type dopants, such as boron (B), can also be included in the S / D region 146. The S / D region 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0080] Next, as Figure 12As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the second portion 140b of the spacer 140, and the S / D region 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on the CESL 162 of the semiconductor device structure 100. The material used for the ILD layer 163 may include compounds, including Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 163. The ILD layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 163 is formed, the semiconductor device structure 100 may be subjected to heat treatment to anneal the ILD layer 163.

[0081] After forming the ILD layer 163, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown below. Figure 12 As shown.

[0082] Figure 13 According to some embodiments along Figure 12 The top cross-sectional view of the semiconductor device structure 100 taken from the BB line. (See attached image.) Figure 13 As shown, the S / D region 146 and the sacrificial gate electrode layer 134 are separated by a first portion 140a of the spacer 140, and the S / D region 146 and the second semiconductor layer 108 are separated by the dielectric spacer 144. As described above, the sloping top surface 119 of the isolation region 120 can result in a substantially flat side surface of the sacrificial gate electrode layer 134. Therefore, no portion of the sacrificial gate electrode layer 134 extends between the first portion 140a of the spacer 140 and the dielectric spacer 144. In some embodiments, the sacrificial gate electrode layer 134 includes a protrusion extending between the first portion 140a of the spacer 140 and the dielectric spacer 144, thus the top surface of the isolation region 120 is substantially flat.

[0083] Figures 14 to 16 This is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 14As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The ILD layer 163 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 and the second semiconductor layer 108 can be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate structure 130 and the second semiconductor layer 108, but without removing the spacer 140, the isolation region 120, the ILD layer 163, and the CESL 162.

[0084] like Figure 14 As shown, in some embodiments, after removing the sacrificial gate structure 130 and the second semiconductor layer 108, the tilted top surface 119 of the isolation region 120 is retained. The tilted top surface 119 may cause an increase in resistance of the subsequently formed gate electrode layer 172. Figure 16 Therefore, in some embodiments, an additional etching process is performed after the sacrificial gate structure 130 and the second semiconductor layer 108 are removed to recess the isolation region 120. In some embodiments, the additional etching process is a dry etching process. For example, a dry etching process utilizes an etchant such as NH3, NF3, HBr, H2, or combinations thereof. In some embodiments, the dry etching process also utilizes a passivating gas to enhance selectivity, and the passivating gas includes N2, O2, or combinations thereof. By incorporating a passivating gas into the dry etching process, the dry etching process etches the dielectric material of the insulating material 118, while the semiconductor material of the first semiconductor layer 106 remains substantially unaffected. The gas flow rates of the etchant and passivating gas range from about 20 standard cubic centimeters (sccm) to about 3000 sccm. The plasma power of the dry etching process ranges from about 10 W to about 4000 W, and the processing pressure ranges from about 10 mTorr to about 3 Torr. In some embodiments, a bias voltage is applied in the additional etching process. Therefore, after the additional etching process, the top surface 119c is essentially flat, as... Figure 15 As shown.

[0085] Therefore, in some embodiments, the isolation region 120 includes a first top surface 119 located between the substrate portions 116. Figure 12 ) and the second top surface 119c in the channel region below the gate electrode layer 172. Figure 16 The first top surface 119 has a "smile" or U-shaped profile, while the second top surface 119c has a substantially flat profile. The "smile" profile of the first top surface 119 helps to ensure that the gate electrode layer 134 is free of protrusions or residues, while the flat profile of the second top surface 119c helps to reduce the resistance of the gate electrode layer 172. Figure 16 ).

[0086] like Figure 16 As shown, after the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106) is formed, a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the ILD layer 163. Then, the gate dielectric layer 170 and gate electrode layer 172 formed on the ILD layer 163 are removed by means of, for example, CMP, until the top surface of the ILD layer 163 is exposed.

[0087] Figure 17 According to some embodiments along Figure 16 A top-view cross-sectional view of the semiconductor device structure 100 taken by the CC line. (See attached image.) Figure 17 As shown, the gate dielectric layer 170 and the S / D region 146 are separated by a first portion 140a of spacer 140 and a dielectric spacer 144. In some embodiments, the thickness of the first portion 140a of spacer 140 ranges from about 5 nm to about 10 nm, and the thickness of the dielectric spacer 144 may be the same as the thickness of the first portion 140a of spacer 140. Using such a thick dielectric material between the gate dielectric layer 170 and the S / D region 146 reduces the risk of an electrical short circuit between the gate electrode layer 172 and the S / D region 146. Furthermore, because the first portion 140a of spacer 140 is in contact with the dielectric spacer 144, the process window for removing the sacrificial gate structure 130 can be expanded.

[0088] Embodiments of the present disclosure provide a semiconductor device structure 100 including an isolation region 120 having a sloped top surface 119 between substrate portions 116. Some embodiments can achieve advantages. For example, the risk of electrical short between gate electrode layers 172 and S / D regions 146 is reduced, and the process window for removing sacrificial gate structures 130 is enlarged.

[0089] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region and a second source / drain region disposed on a substrate, and an isolation region disposed between the first source / drain region and the second source / drain region. The isolation region includes a first top surface having a sloped portion and a flat portion, and a portion of the isolation region between the sloped portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height. The width is greater than the height. The semiconductor device structure further includes a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a spacer disposed between the gate electrode layer and the first source / drain region. In some embodiments, the semiconductor device structure further includes a dielectric spacer in contact with the spacer, wherein the dielectric spacer is disposed between the gate electrode layer and the first source / drain region. In some embodiments, the semiconductor device structure further includes a gate dielectric layer disposed between the gate electrode layer and the first source / drain region. In some embodiments, the width and the height are in a range from about 10 nm to about 15 nm. In some embodiments, the isolation region includes a second top surface underlying the gate electrode layer. In some embodiments, the second top surface has a different profile than the first top surface. In some embodiments, the second top surface is flat.

[0090] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed on a first substrate portion, a second source / drain region disposed on a second substrate portion, a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and an isolation region. The isolation region includes a first top surface between the first substrate portion and the second substrate portion and a second top surface below the gate electrode layer. The first top surface has a U-shaped profile and the second top surface has a flat profile. In some embodiments, the first top surface forms an angle relative to a side surface of the first substrate portion. In some embodiments, the angle ranges from about 105 degrees to about 130 degrees. In some embodiments, the semiconductor device structure further includes a spacer disposed between the gate electrode layer and the first source / drain region. In some embodiments, the semiconductor device structure further includes a dielectric spacer in contact with the spacer, wherein the dielectric spacer is disposed between the gate electrode layer and the first source / drain region. In some embodiments, the semiconductor device structure further includes a gate dielectric layer disposed between the gate electrode layer and the first source / drain region.

[0091] Some embodiments of the present disclosure are a method of forming a semiconductor device structure. The method includes forming a fin structure on a substrate, depositing an insulating material around the fin structure above the substrate, and recessing the insulating material to form an isolation region. A first top surface of the isolation region includes a sloped portion and a flat portion, and a portion of the isolation region between the sloped portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height. The width is greater than the height. The method of forming a semiconductor device structure further includes forming a sacrificial gate structure and forming a source / drain region on the substrate. In some embodiments, the insulating material is recessed by a first dry etching process. In some embodiments, the first dry etching process does not have a bias voltage. In some embodiments, the method further includes removing the sacrificial gate structure to expose the first top surface of the isolation region. In some embodiments, the method further includes removing portions of the first top surface to form a second top surface of the isolation region. In some embodiments, the second top surface of the isolation region has a flat profile. In some embodiments, a second dry etching process is performed to remove the portions of the first top surface, wherein the second dry etching process includes a bias voltage.

[0092] Yet other embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed on a first substrate portion, a second source / drain region disposed on a second substrate portion, a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and an isolation region. The isolation region includes a first top surface between the first substrate portion and the second substrate portion and a second top surface below the gate electrode layer. The first top surface has a U-shaped profile and the second top surface has a flat profile, wherein the first top surface forms an angle with respect to a side surface of the first substrate portion, the angle ranging from 105 degrees to 130 degrees.

[0093] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. The familiar skilled person will appreciate that the disclosure can be used as a basis for the design or modification of other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments presented herein. The familiar skilled person will also recognize that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can be made and used in various changes, substitutions, and alterations without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device structure, characterized by, Comprising: a first source / drain region and a second source / drain region disposed on a substrate; an isolation region disposed between the first source / drain region and the second source / drain region, wherein the isolation region includes a first top surface having a sloped portion and a flat portion, and a portion of the isolation region between the sloped portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height, wherein the width is greater than the height; a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; and a spacer disposed between the gate electrode layer and the first source / drain region. Further comprising a dielectric spacer in contact with the spacer, wherein the dielectric spacer is disposed between the gate electrode layer and the first source / drain region.

2. The semiconductor device structure of claim 1, wherein, Further comprising a gate dielectric layer disposed between the gate electrode layer and the first source / drain region.

3. The semiconductor device structure of claim 1, wherein, wherein the width and the height range from 10 nm to 15 nm.

4. The semiconductor device structure of claim 1, wherein, wherein the isolation region includes a second top surface located below the gate electrode layer.

5. The semiconductor device structure of claim 1, wherein, wherein the second top surface has a different profile than the first top surface.

6. The semiconductor device structure of claim 5, wherein, wherein the second top surface is flat.

7. The semiconductor device structure of claim 6, wherein Comprising:

8. A semiconductor device structure, characterized by, a first source / drain region disposed on a first substrate portion; a second source / drain region disposed on a second substrate portion; a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; and an isolation region, wherein the isolation region includes a first top surface located between the first substrate portion and the second substrate portion and a second top surface located below the gate electrode layer, the first top surface has a U-shaped profile, and the second top surface has a flat profile. Further comprising a spacer disposed between the gate electrode layer and the first source / drain region. Comprising:

9. The semiconductor device structure of claim 8, wherein, a first source / drain region disposed on a first substrate portion; 10. A semiconductor device structure, characterized by, a second source / drain region disposed on a second substrate portion; a plurality of semiconductor layers disposed adjacent to the first source / drain region and the second source / drain region; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; and an isolation region, wherein the isolation region includes a first top surface located between the first substrate portion and the second substrate portion and a second top surface located below the gate electrode layer, the first top surface has a U-shaped profile, and the second top surface has a flat profile, wherein the first top surface forms an angle relative to a side surface of the first substrate portion, the angle ranging from 105 degrees to 130 degrees. ​ ​ ​

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