Semiconductor device

Abstract

The utility model provides a semiconductor device, comprising a first source / drain region and a second source / drain region which are arranged on a substrate; the first source electrode / drain electrode region and the second source electrode / drain electrode region are located on the two sides of the gate structure; a source / drain contact over the first source / drain region and adjacent to the gate structure; a bottom contact etch stop layer (B-CESL) between the gate structure and the source / drain contact; a gate spacer between the B-CESL and the gate structure; and a source / drain contact liner between the B-CESL and the source / drain contact, where a first oxygen concentration of the first material of the source / drain contact liner is greater than a second oxygen concentration of the second material of the gate spacer, and where a third oxygen concentration of the third material of the B-CESL is greater than the second oxygen concentration of the second material of the gate spacer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to a semiconductor device with a liner. BACKGROUND

[0002] Fin-based transistors, such as fin field effect transistors (finFETs), and nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors) are three-dimensional structures that include a channel region in a fin (or a portion thereof) extending above a semiconductor substrate as a three-dimensional structure. A gate structure is configured to control the flow of charge carriers within the channel region, the gate structure wrapping around the fin of semiconductor material. For example, in a finFET, the gate structure wraps around three sides (and the channel region) of the fin, enabling increased control over the channel region (and over switching of the finFET). As another example, in a nanostructure transistor, the gate structure wraps around multiple channel regions in a fin structure, such that the gate structure wraps around each of the multiple channel regions. Source / drain regions (e.g., epitaxial regions) are located on opposing sides of the gate structure. SUMMARY

[0003] The present disclosure aims to provide a package and an optical structure to solve at least one of the above problems.

[0004] A semiconductor device is provided. The semiconductor device includes a first source / drain region and a second source / drain region over a substrate; a gate structure on opposing sides of the first source / drain region and the second source / drain region; a source / drain contact over the first source / drain region and adjacent to the gate structure; a bottom contact etch stop layer (B-CESL) between the gate structure and the source / drain contact; a gate spacer between the B-CESL and the gate structure; and a source / drain contact liner between the B-CESL and the source / drain contact, wherein a first oxygen concentration of a first material of the source / drain contact liner is greater than a second oxygen concentration of a second material of the gate spacer, and wherein a third oxygen concentration of a third material of the B-CESL is greater than the second oxygen concentration of the second material of the gate spacer.

[0005] According to an embodiment of the present application, a first dielectric constant of the source / drain contact liner is less than a second dielectric constant of the gate spacer.

[0006] According to an embodiment of the present application, a first dielectric constant of the bottom contact etch stop layer is less than a second dielectric constant of the gate spacer. According to an embodiment of the present application, the source / drain contact liner comprises a first source / drain contact liner; and wherein the semiconductor device further comprises: a second source / drain contact liner between the first source / drain contact liner and the source / drain contact.

[0007] According to an embodiment of the present application, a first thickness of the first source / drain contact liner is greater than a second thickness of the second source / drain contact liner.

[0008] According to an embodiment of the present application, the first thickness is in a range of 3 nanometers to 10 nanometers, and the second thickness is in a range of 2 nanometers to 9 nanometers.

[0009] According to an embodiment of the present application, a first dielectric constant of the first source / drain contact liner is less than a second dielectric constant of the second source / drain contact liner.

[0010] According to an embodiment of the present application, the first oxygen concentration of the first material of the first source / drain contact liner is greater than a fourth oxygen concentration of a fourth material of the second source / drain contact liner.

[0011] According to an embodiment of the present application, a distance between the gate structure and the source / drain contact is in a range of 5 nanometers to 20 nanometers.

[0012] According to an embodiment of the present application, further comprising a fin structure over the substrate, wherein the gate structure wraps around the fin structure on at least three sides of the fin structure. BRIEF DESCRIPTION OF DRAWINGS

[0013] Various aspects of the disclosure will be described in detail with reference to the drawings, wherein like reference numerals represent like parts. It should be noted that the various elements of the drawings are not drawn to scale and are only used to illustrate examples. In fact, the dimensions of the elements can be arbitrarily expanded or reduced for the sake of clarity in illustrating the components of the embodiments of the disclosure.

[0014] FIG. 1 is a schematic diagram of an example environment in which the systems and / or methods described herein can be implemented.

[0015] FIG. 2 is a schematic diagram of an example region of the semiconductor device described herein.

[0016] FIGS. 3A-3D is a schematic diagram of an exemplary embodiment of a semiconductor device described herein.

[0017] FIGS. 4A-4C is a schematic diagram of an exemplary embodiment of a source / drain region of a semiconductor device described herein.

[0018] FIGS. 5A-5D is a schematic diagram of an exemplary embodiment of a dummy gate replacement process of a semiconductor device described herein.

[0019] FIGS. 6A-6I is a schematic diagram of an exemplary embodiment of a source / drain contact of a semiconductor device described herein.

[0020] FIG. 7 is a schematic diagram of one or more exemplary dimensions of a semiconductor device described herein.

[0021] FIG. 8 is a schematic diagram of an exemplary embodiment of an elemental composition of a portion of a semiconductor device described herein.

[0022] FIG. 9 is a schematic diagram of an exemplary element of a device described herein.

[0023] FIG. 10 is a flowchart of an exemplary process associated with forming a semiconductor device described herein.

[0024] FIG. 11 is a flowchart of an exemplary process associated with forming a semiconductor device described herein.

[0025] wherein the following figure designations apply:

[0026] 100: exemplary environment

[0027] 102: deposition tool

[0028] 104: exposure tool

[0029] 106: development tool

[0030] 108: etching tool

[0031] 110: planarization tool

[0032] 112: electroplating tool

[0033] 114: wafer / die transport tool

[0034] 200: semiconductor device

[0035] 202: device region

[0036] 204: substrate

[0037] 206: fin structure

[0038] 208: shallow trench isolation (STI) region

[0039] 210: dummy gate structure

[0040] 212: gate dielectric layer

[0041] 214: gate electrode layer

[0042] 216: hardmask layer

[0043] 218: source / drain region

[0044] 300: exemplary embodiment

[0045] 302: shallow trench isolation (STI) layer

[0046] 400: exemplary embodiment

[0047] 402: sealing spacer layer

[0048] 404: gate spacer

[0049] 406: recess

[0050] 408: source / drain region

[0051] 500: exemplary embodiment

[0052] 502: bottom contact etch stop layer (B-CESL)

[0053] 504: interlayer dielectric (ILD) layer

[0054] 506: recess

[0055] 508: gate structure

[0056] 510: high-k dielectric layer

[0057] 512: work function adjustment layer

[0058] 514: metal electrode structure

[0059] 600: exemplary embodiment

[0060] 602: contact etch stop layer (CESL)

[0061] 604: interlayer dielectric (ILD) layer

[0062] 606: recess

[0063] 606a: bottom surface

[0064] 606b / 606c: sidewall

[0065] 608: source / drain contact liner

[0066] 610: oxidation treatment gas

[0067] 612: source / drain contact liner

[0068] 614: metal silicide layer

[0069] 616: material

[0070] 618: source / drain contact

[0071] 700: illustrative embodiment

[0072] 800: illustrative embodiment

[0073] 802: element concentration

[0074] 804: lateral position

[0075] 806: nitrogen

[0076] 808: oxygen

[0077] 900: apparatus

[0078] 910: bus

[0079] 920: processor

[0080] 930: memory

[0081] 940: input element

[0082] 950: output element

[0083] 960: communication element

[0084] 1000: process

[0085] 1010 / 1020 / 1030 / 1040 / 1050 / 1060 / 1070: block

[0086] 1100: process

[0087] 1110 / 1120 / 1130 / 1140 / 1150 / 1160 / 1170 / 1180: block

[0088] D1 / D2 / D3 / D4 / D5 / D6 / D7 / D8: illustrative dimensions. DETAILED DESCRIPTION

[0089] The following disclosure provides many different embodiments, or examples, for implementing different aspects of the provided subject matter. Each of the various embodiments and its configurations are described in detail in the following disclosure in order to provide a thorough understanding of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, when a first element is referred to as being formed on a second element, this can include embodiments where the first and second elements are in direct contact, and can also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, the present disclosure can refer to a number of units and / or letters repeatedly in various examples. Such repetition is for the sake of simplicity and clarity and does not indicate a relationship between the different embodiments and / or configurations discussed.

[0090] Furthermore, where spatially relative terms are used, such as "beneath", "below", "lower", "above", "upper", and the like, they are used for ease of describing the aspects of figures only and to illustrate the positional relationship of one (s) component(s) to another (s) component(s) or to another part(s) of a device. The spatially relative terms are used to encompass different orientations of the device in use or operation, and the orientations described in the figures. Where the device is turned over to different orientations (90 degrees or other orientations), the spatially relative terms used will also be interpreted accordingly.

[0091] Transistor structures (e.g., planar transistors, fin field effect transistors (finFETs), nanostructure transistors) in semiconductor devices can include various liner, barrier, and / or spacer layers. These film layers can be included to provide electrical isolation between conductive structures of the transistor structure, to promote adhesion between the conductive structures and surrounding dielectric regions, and / or to prevent migration of materials into the dielectric regions, among other things.

[0092] The semiconductor industry continues to strive to reduce process generation sizes in an effort to increase transistor density and / or reduce power consumption in fabricated semiconductor devices. While increased transistor density and / or reduced power consumption can increase efficiency and / or process capability of the semiconductor devices, reducing the size of structures and / or film layers in semiconductor devices can result in undesirable side effects that can compromise the performance of the semiconductor devices. For example, reducing the size of structures and / or film layers in semiconductor devices can result in a reduction of dielectric material between conductive structures in the semiconductor devices. This can result in the conductive structures being brought closer together, which can result in increased leakage current between the conductive structures and / or parasitic capacitance between the conductive structures, among other things.

[0093] Furthermore, parasitic capacitance in semiconductor devices can cause a decrease in performance of the semiconductor devices because the parasitic capacitance can cause residual charge to be stored in source / drain contacts and / or gate structures of transistors of the semiconductor devices. As the parasitic capacitance causes an increase in resistance-capacitance (RC) time constant, this can cause a longer switching time of the transistors (e.g., between on state and off state). Furthermore, the parasitic capacitance can cause electrical coupling between conductive structures of the transistors, which can increase processing errors in the semiconductor devices and / or decrease processing speed due to increased interference from the parasitic capacitance.

[0094] In some implementations described herein, a semiconductor device can include a plurality of transistor structures. Each transistor structure can include a plurality of source / drain regions, a semiconductor channel region between the source / drain regions, and a gate structure configured to selectively control a conductivity of the semiconductor channel region between the source / drain regions, thereby enabling the transistor structure to switch between an on state and an off state. The source / drain regions can individually or collectively refer to a source or a drain, depending on the context.

[0095] The semiconductor device can also include one or more layers of dielectric layers between source / drain contact structures (e.g., metal drain (MD)) and gate structures (e.g., metal gate (MG)) of one or more transistor structures. Fabrication of the one or more layers of dielectric layers can use an oxidation process to adjust a dielectric constant of the one or more layers of dielectric layers. The dielectric constant of the one or more layers of dielectric layers can be adjusted to reduce parasitic capacitance between the source / drain contact structures and the gate structures, which are conductive structures. In particular, the dielectric constant of the one or more layers of spacer dielectrics can be adjusted using the oxidation process to reduce an as-deposited dielectric constant of the one or more layers of dielectric layers.

[0096] As such, the dielectric constant of the one or more layers of dielectric layers can be reduced using the oxidation process after the one or more layers of dielectric layers are deposited. This enables the initially high dielectric constant to be maintained after the one or more layers of dielectric layers are deposited, which enables the one or more layers of dielectric layers to better withstand damage from one or more subsequent semiconductor process operations (e.g., etching operations, pre-cleaning operations) after the one or more layers of dielectric layers are deposited.

[0097] Furthermore, this allows the dielectric constant of one or more dielectric layers to be subsequently reduced. This reduces the parasitic capacitance between the source / drain contact structure and the gate structure during transistor operation, as the parasitic capacitance between the source / drain contact structure and the gate structure can be proportional to the dielectric constant of the one or more dielectric layers between them. Reduced parasitic capacitance can shorten the switching time of the transistor structure, which can improve the performance of the semiconductor device and / or reduce processing errors in the semiconductor device.

[0098] FIG. 1 This is a schematic diagram of an exemplary environment 100 in which the systems and / or methods described herein can be implemented. FIG. 1 As shown, the exemplary environment 100 may include a plurality of semiconductor process tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor process tools 102-112 may include deposition tools 102, exposure tools 104, developing tools 106, etching tools 108, planarization tools 110, electroplating tools 112, and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be found in semiconductor clean rooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities.

[0099] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced chemical vapor deposition (PECVD) tool, a high-density plasma chemical vapor deposition (HDP-CVD) tool, a sub-atmospheric chemical vapor deposition (SACVD) tool, a low-pressure chemical vapor deposition (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxy tool, where the epitaxy tool is configured to form film layers and / or regions of devices by epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0100] The exposure tool 104 is a semiconductor process tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV source, an extreme UV (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a reticle to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0101] The development tool 106 is a semiconductor process tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some implementations, the development tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the development tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the development tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0102] The etching tool 108 is a semiconductor process tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some implementations, the etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a particular period of time to remove a particular amount of one or more portions of the substrate. In some implementations, the etching tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions of a substrate, which can involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0103] The planarization tool 110 is a semiconductor process tool that is capable of polishing or planarizing various film layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a film layer or surface of a deposited or electroplated material. The planarization tool 110 can use a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize a surface of a semiconductor device. The planarization tool 110 can use abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can be rotated on different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

[0104] The electroplating tool 112 is a semiconductor process tool that is capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more another type of conductive material, metal, and / or the like.

[0105] The wafer / die transport tools 114 include mobile robots, robot arms, trams or rail cars, overhead hoist transport (OHT) systems, automated materially handling systems (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between the semiconductor process tools 102-112, between process chambers of the same semiconductor process tool, and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some embodiments, the wafer / die transport tools 114 can be programmed devices configured to travel a particular path and / or operate semi-autonomously or autonomously. In some embodiments, the semiconductor processing environment 100 includes multiple wafer / die transport tools 114.

[0106] For example, the wafer / die transport tool 114 can be included in a cluster tool or another type of tool that includes multiple process chambers, and the wafer / die transport tool 114 can be configured to transport substrates and / or semiconductor devices between the multiple process chambers, between a process chamber and a buffer area, between a process chamber and an interface tool such as an equipment front end module (EFEM), between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some implementations, the wafer / die transport tool 114 can be included in a multi-chamber (or cluster) deposition tool 102 that can include a pre-clean process chamber (e.g., a process chamber for cleaning or removing oxides, oxidation, and / or another type of contaminant or byproduct from a substrate and / or semiconductor device) and multiple deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition processes). In these implementations, the wafer / die transport tool 114 is configured to transport substrates and / or semiconductor devices between the process chambers of the deposition tool 102 without breaking or removing a vacuum (or at least a partial vacuum) between the process chambers and / or between process operations in the deposition tool 102, as described herein.

[0107] In some implementations, one or more of the semiconductor process tools 102-112 and / or the wafer / die transport tool 114 can perform one or more of the semiconductor process operations described herein. For example, one or more of the semiconductor process tools 102-112 and / or the wafer / die transport tool 114 can form a fin structure over a substrate, can form a gate structure that wraps around the fin structure on at least three sides of the fin structure, can form a first source / drain region and a second source / drain region on the fin structure with the gate structure between the first source / drain region and the second source / drain region, can form a recess over the first source / drain region adjacent to the gate structure, can form a liner on sidewalls of the recess, can perform an oxidation process operation to oxidize the liner, and / or can form a source / drain contact over the liner in the recess such that the source / drain contact is coupled with the first source / drain region, etc.

[0108] As another illustration, one or more of the semiconductor process tools 102-112 and / or the wafer / die transport tool 114 can form a fin structure over a substrate; can form a gate structure that wraps around the fin structure on at least three sides of the fin structure; can form a first source / drain region and a second source / drain region on the fin structure, with the gate structure between the first source / drain region and the second source / drain region; can form a recess over the first source / drain region, adjacent to the gate structure; can form a first liner on sidewalls of the recess; can perform an oxidation process operation to oxidize the first liner; after performing the oxidation process operation, can form a second liner on the first liner; and / or can form a source / drain contact over the second liner in the recess, such that the source / drain contact is coupled with the first source / drain region, etc.

[0109] One or more of the semiconductor process tools 102-112 and / or the wafer / die transport tool 114 can perform other semiconductor process operations described herein, such as those described in connection with FIGS. 3A-3D , FIGS. 4A-4C , FIGS. 5A-5D , FIGS. 6A-6I , FIG. 11 , etc.

[0110] FIG. 1 The number and arrangement of devices shown in FIG. 1 are provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. 1. Furthermore, two or more devices shown in FIG. 1 can be implemented within a single device, or a single device shown in FIG. 1 can be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of example environment 100 can perform one or more functions described as being performed by another set of devices of example environment 100. FIG. 1 FIG. 1 FIG. 1

[0111] FIG. 2 is a schematic diagram of an illustrative region of a semiconductor device 200 described herein. In particular, FIG. 2 ​​​An exemplary device region 202 of the semiconductor device 200 is shown, which includes one or more transistors or other devices. The transistors can include fin-based transistors, such as finFETs, nanostructure transistors, and / or another type of transistor. In some implementations, the device region 202 includes a p-type metal oxide semiconductor (PMOS) region, an n-type metal oxide semiconductor (NMOS) region, a complementary metal-oxide semiconductor (CMOS) region, and / or another type of device region. FIGS. 3A-6I is as FIG. 2 Schematic cross-sectional views of various portions of the device region 202 of the semiconductor device 200 are shown, and correspond to various process stages of forming fin-based transistors in the device region 202 of the semiconductor device 200.

[0112] The semiconductor device includes a substrate 204. The substrate 204 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or another type of semiconductor substrate. The substrate 204 can include a round / circular substrate having a diameter of about 200 millimeters, a diameter of about 300 millimeters, or other diameters such as 450 millimeters. The substrate 204 can alternatively be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0113] A fin structure 206 is included on (and / or extends above) the substrate 204 of the device region 202. The fin structure 206 provides an active region in which one or more devices (e.g., fin-based transistors) are formed. In some implementations, the fin structure 206 includes a silicon material or other elemental semiconductor material, such as germanium. In some implementations, the fin structure 206 includes an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), indium gallium arsenide phosphide (GaInAsP), or a combination of the foregoing. In some implementations, the fin structure 206 can be doped using n-type and / or p-type dopants.

[0114] The fin structures 206 are fabricated by suitable semiconductor processing techniques, such as masking, lithography, and / or etching processes. As an example, a portion of the substrate 204 can be removed by etching to form recesses in the substrate 204 to form the fin structures 206, and then the recesses can be filled with an isolation material that is recessed or etched back to form shallow trench isolation (STI) regions 208 over the substrate 204 and between the fin structures 206. Other fabrication techniques for the STI regions 208 and / or the fin structures 206 can be used. The STI regions 208 can electrically isolate active regions adjacent to the fin structures 206. The STI regions 208 can include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating material. The STI regions 208 can include a multi-layer structure, for example, with one or more liner layers.

[0115] The dummy gate structure 210 (or multiple dummy gate structures 210) is included in the device region 202 above the fin structures 206 (e.g., approximately perpendicular to the fin structures 206). The dummy gate structure 210 engages the fin structures 206 on three or more sides of the fin structures 206. In the example depicted in FIG. 2, the dummy gate structure 210 engages the fin structures 206 on four sides of the fin structures 206. FIG. 2 In the example depicted in FIG. 2, the dummy gate structure 210 includes a gate dielectric layer 212, a gate electrode layer 214, and a hardmask layer 216. In some embodiments, the dummy gate structure 210 also includes a cap layer, one or more spacer layers, and / or other suitable film layers. The various film layers in the dummy gate structure 210 can be formed by suitable deposition techniques and patterned by suitable lithography and etching techniques.

[0116] As described herein, the term "dummy" refers to a sacrificial structure that will be removed and replaced with another structure at a later stage, such as a high-k dielectric and metal gate structure in a replacement gate process. The replacement gate process refers to fabricating gate structures at a later stage in the overall gate fabrication process. Thus, the dummy gate structure 210 is a sacrificial structure that will be removed and replaced with another structure at a later stage in the overall gate fabrication process. FIG. 2 The configuration of the semiconductor device 200 shown can include an intermediate configuration, and additional semiconductor processing operations can be performed on the semiconductor device 200 to further fabricate the semiconductor device 200.

[0117] The gate dielectric layer 212 can include a dielectric oxide layer. The dielectric oxide layer can be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The gate electrode layer 214 can include polysilicon material or other suitable material. The gate electrode layer 214 can be formed by a suitable deposition process, such as LPCVD or PECVD, among others. The hardmask layer 216 can include any material suitable for patterning the gate electrode layer 214, and the material has a particular feature / dimension on the substrate 206.

[0118] In some embodiments, the various film layers of the dummy gate structure 210 are first deposited as a blanket layer, and then the blanket layer is patterned by a process including a lithography and etching process to remove a portion of the blanket layer and leave a remaining portion over the STI region 208 and the fin structure 206 to form the dummy gate structure 210.

[0119] The source / drain regions 218 are disposed in two opposing regions of the fin structure 206 with respect to the dummy gate structure 210. The source / drain regions 218 include regions in the device region 202 where source / drain regions are to be formed. The source / drain regions in the device region 202 include silicon (Si) doped with one or more dopants, such as p-type material (e.g., boron (B) or germanium (Ge), among others), n-type material (e.g., phosphorus (P) or arsenic (As), among others), and / or another type of dopant. As such, the device region 202 can include PMOS transistors including p-type source / drain regions, NMOS transistors including n-type source / drain regions, and / or other types of transistors.

[0120] Some source / drain regions can be shared among various transistors in the device region 202. In some embodiments, the various regions in the source / drain regions can be connected or coupled together such that the fin-based transistors in the device region 202 are implemented as two functional transistors. For example, if adjacent (e.g., as opposed to opposing) source / drain regions are electrically connected, such as by coalescing the regions (e.g., adjacent source / drain regions coalesce as opposed to the two sides of the dummy gate structure 210), two functional transistors can be implemented. Other configurations in other examples can implement other numbers of functional transistors.

[0121] FIG. 2 Further shown are reference cross-sections used in later figures, including FIGS. 3A-8A-A is in a plane along a channel in the fin structure 206 between the source / drain regions 218 on either side. The cross-section B-B is in a plane perpendicular to the plane of cross-section A-A and across the source / drain regions 218 in the fin structure 206. For clarity, the subsequent figures refer to these reference cross-sections. In some figures, some element designations for elements or components shown in the figures can be omitted for ease of drawing the figures to avoid obscuring other elements or components.

[0122] As described above, there is provided FIG. 2 as an example. Other examples can differ from what is described with respect to FIG. 2 what is described.

[0123] FIGS. 3A-3D is a schematic diagram of an exemplary embodiment 300 described herein. The exemplary embodiment 300 includes an example of forming a fin structure 206 of a transistor for a semiconductor device 200. FIGS. 3A-3D is a perspective view illustration of a cross-section B-B of the semiconductor device 200 from FIG. 2 .

[0124] In some embodiments, the one or more semiconductor process operations described in connection with FIG. 1 are performed by one or more semiconductor process tools 102-112 and / or wafer / die transport tools 114 described in connection with FIGS. 3A-3D In some embodiments, the one or more semiconductor process operations described in connection with FIG. 1 are performed by one or more semiconductor process tools not shown. FIGS. 3A-3D In some embodiments, the one or more semiconductor process operations described in connection with are performed by one or more semiconductor process tools not shown.

[0125] FIG. 3A Turning to , the exemplary embodiment 300 includes semiconductor process operations related to forming a transistor in the semiconductor device 200 and / or a substrate 204 on the semiconductor device 200.

[0126] FIG. 3BAs shown, a fin structure 206 is formed in a substrate 204 within a semiconductor device 200. In some embodiments, a pattern in a photoresist layer is used to form the fin structure 206. In these embodiments, a deposition tool 102 forms a photoresist layer on the substrate 204. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. An etching tool 108 etches into the substrate 204 to form the fin structure 206. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the fin structure 206.

[0127] like FIG. 3C As shown, an STI layer 302 is formed between the fin structures 206. The deposition tool 102 utilizes CVD, PVD, ALD, and a combination of the above techniques. FIG. 1 The described deposition techniques and / or other deposition techniques are used to deposit the STI layer 302. In some embodiments, the STI layer 302 is formed such that its height is greater than the height of the fin structure 206. In these embodiments, a planarization tool 110 performs a planarization (or grinding) operation to planarize the STI layer 302 such that the top surface of the STI layer 302 is substantially flat and smooth, and that the top surface of the STI layer 302 is approximately the same height as the top surface of the fin structure 206. The planarization process can increase the uniformity of the STI region 208 formed in the subsequent etching process.

[0128] like FIG. 3DAs shown, the STI layer 302 is etched in a back-etch process to expose a portion of the fin structures 206. The etching tool 108 etches a portion of the STI layer 302 by a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. The remaining portion of the STI layer 302 between the fin structures 206 comprises the STI regions 208. In some implementations, the STI layer 302 is etched such that the height of the exposed portions of the fin structures 206 (e.g., a portion of the fin structures 206 above the top surface of the STI regions 208) are the same in the semiconductor device 200. In some implementations, a first portion of the STI layer 302 in the semiconductor device 200 is etched and a second portion of the STI layer 302 in the semiconductor device 200 is etched such that the height of the exposed portions of a first subset of the fin structures 206 is different from the height of the exposed portions of a second subset of the fin structures 206, which enables adjustment of the fin height to achieve particular characteristics for the semiconductor device 200.

[0129] As described above, there is provided FIGS. 3A-3D as an example. Other examples can differ from what is described with respect to FIGS. 3A-3D what is described.

[0130] FIGS. 4A-4C is a schematic diagram of an exemplary implementation 400 of forming source / drain regions in the source / drain regions 218 of the semiconductor device 200 described herein. FIGS. 4A-4C is shown in a perspective view from the cross-section A-A in the semiconductor device 200 described with respect to FIG. 2 .

[0131] In some implementations, the operations described with respect to the fin formation process described with respect to FIGS. 3A-3D are performed after the fin formation process described with respect to FIG. 1 In some implementations, the one or more semiconductor process operations described with respect to FIGS. 4A-4C are performed by the one or more semiconductor process tools 102-112 and / or the wafer / die transport tool 114 described with respect to FIG. 1 In some implementations, the one or more semiconductor process operations described with respect to FIGS. 4A-4C are performed by the one or more semiconductor process tools not shown.

[0132] As described above, there is provided FIG. 4AAs shown, dummy gate structures 210 are formed in semiconductor device 200. Dummy gate structures 210 are formed and included above fin structures 206 and around sides of fin structures 206, such that dummy gate structures 210 wrap fin structures 206 on at least three sides of fin structures 206. Dummy gate structures 210 are formed as placeholders for actual gate structures (e.g., replacement high-k gates or metal gates) and are formed for transistors included in semiconductor device 200. Dummy gate structures 210 can be formed as part of a replacement gate process, which enables other film layers and / or structures to be formed prior to forming replacement gate structures.

[0133] Dummy gate structures 210 include gate dielectric layers 212, gate electrode layers 214, and hard mask layers 216. Gate dielectric layers 212 can each include a dielectric oxide layer. By way of illustration, gate dielectric layers 212 can each be formed (e.g., by deposition tool 102) by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. Gate electrode layers 214 can each include a polysilicon layer or other suitable film layer. By way of example, gate electrode layers 214 can be formed (e.g., by deposition tool 102) by a suitable deposition process such as LPCVD or PECVD. Hard mask layers 216 can each include any material suitable for patterning gate electrode layers 214 having particular dimensions and / or attributes. Illustrations include silicon nitride, silicon oxynitride, silicon carbon nitride, or combinations of the foregoing. Hard mask layers 216 can be deposited (e.g., by deposition tool 102) by CVD, PVD, ALD, or other deposition techniques.

[0134] As shown, dummy gate structures 210 are formed in semiconductor device 200. Dummy gate structures 210 are formed and included above fin structures 206 and around sides of fin structures 206, such that dummy gate structures 210 wrap fin structures 206 on at least three sides of fin structures 206. Dummy gate structures 210 are formed as placeholders for actual gate structures (e.g., replacement high-k gates or metal gates) and are formed for transistors included in semiconductor device 200. Dummy gate structures 210 can be formed as part of a replacement gate process, which enables other film layers and / or structures to be formed prior to forming replacement gate structures. FIG. 4A Further shown, seal spacer layers 402 are included on sidewalls of dummy gate structures 210. Seal spacer layers 402 can be conformally deposited (e.g., by deposition tool 102) and can include silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. In other illustrative deposition techniques, seal spacer layers 402 can be formed by an ALD process in which various types of precursor gases including silicon (Si) and carbon (C) are sequentially supplied in multiple alternating cycles to form seal spacer layers 402.

[0135] As shown, dummy gate structures 210 are formed in semiconductor device 200. Dummy gate structures 210 are formed and included above fin structures 206 and around sides of fin structures 206, such that dummy gate structures 210 wrap fin structures 206 on at least three sides of fin structures 206. Dummy gate structures 210 are formed as placeholders for actual gate structures (e.g., replacement high-k gates or metal gates) and are formed for transistors included in semiconductor device 200. Dummy gate structures 210 can be formed as part of a replacement gate process, which enables other film layers and / or structures to be formed prior to forming replacement gate structures. FIG. 4AAs further shown, the gate spacer 404 can be formed on the sealing spacer layer 402. The gate spacer 404 can be formed from a material similar to that of the sealing spacer layer 402. However, the gate spacer 404 can be formed without plasma surface treatment for the sealing spacer layer 402. Furthermore, the gate spacer 404 can be formed to a greater thickness relative to the thickness of the sealing spacer layer 402.

[0136] In some embodiments, a sealing spacer layer 402 and a gate spacer 404 are compliantly deposited (e.g., by deposition tool 102) on the dummy gate structure 210 and the fin structure 206. Then, the sealing spacer layer 402 and the gate spacer 404 are patterned (e.g., by deposition tool 102, exposure tool 104, and development tool 106) and etched (e.g., by etching tool 108) to remove the sealing spacer layer 402 and the gate spacer 404 from the top of the dummy gate structure 210 and from the fin structure 206.

[0137] like FIG. 4B As shown, during the etching operation, a recess 406 is formed in the fin structure 206 of the semiconductor device 200 between the dummy gate structures 210. The etching operation may be referred to as a strained source / drain (SSD) etching operation, and the recess 406 may be referred to as a strained source / drain region. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique.

[0138] In some implementations, multiple etch operations are performed to form the recess 406 for different types of transistors. For example, a photoresist layer may be formed over and / or on a first subset of the fin structure 206 and over and / or on a first subset of the dummy gate structure 210, such that a second subset of the fin structure 206 is located between the second subsets of the dummy gate structure 210, allowing the p-type source / drain regions and n-type source / drain regions to be formed in separate epitaxial operations.

[0139] like FIG. 4CAs shown, source / drain regions 408 are formed in recesses 406 over substrate 204 in semiconductor device 200. Deposition tool 102 forms source / drain regions 408 by an epitaxy operation in which an epitaxial material layer is deposited in recesses 406 such that a film layer of p-type source / drain regions or a film layer of n-type source / drain regions is formed by epitaxial growth in a particular crystalline direction. Source / drain regions 408 are included between and at least partially under and / or below dummy gate structures 210. Source / drain regions 408 extend at least partially over a top surface of fin structures 206.

[0140] The material used to form source / drain regions 408 (e.g., silicon (Si), germanium (Ge), gallium (Ga), or another type of semiconductor material) can be doped with p-type dopants (e.g., a type of dopant that includes electron acceptor atoms that create holes in the material), n-type dopants (e.g., a type of dopant that includes electron donor atoms that create mobile electrons in the material), and / or another type of dopant. The material can be doped by adding dopants (e.g., p-type dopants, n-type dopants) to a source gas used during the epitaxy operation. Examples of p-type dopants that can be used in the epitaxy operation include boron (B) and / or germanium (Ge), among others. The resulting material of p-type source / drain regions includes silicon germanium (SixGei_x, where x can range from about 0 to about 100) or another type of p-type doped semiconductor material. Examples of n-type dopants that can be used in the epitaxy operation include phosphorus (P), antimony (Sb), and / or arsenic (As), among others. The resulting material of n-type source / drain regions includes silicon phosphide (SixPy) or another type of n-type doped semiconductor material.

[0141] As described above, providing FIGS. 4A-4C is an example. Other examples can differ from what is described FIGS. 4A-4C above.

[0142] FIGS. 5A-5D is a schematic diagram of an example embodiment 500 of a dummy gate replacement process for semiconductor device 200 described herein. The dummy gate replacement process can be performed such that dummy gate structures 210 are replaced with high-k gate structures and / or metal gate structures (e.g., metal gates (MGs)). FIGS. 5A-5D is shown in a perspective view from section A-A in FIG. 2 dummy gate replacement process for semiconductor device 200.

[0143] In some embodiments, in conjunction with FIGS. 4A-4CAfter the described source / drain formation process, the operations described in conjunction with exemplary embodiment 500 are performed. In some embodiments, by combining FIG. 1 The described one or more semiconductor process tools 102-112 and / or wafer / die transport tool 114 are used to perform the bonding. FIGS. 5A-5D Describes one or more semiconductor process operations. In some implementations, through... FIG. 1 One or more semiconductor process tools not shown are used to perform the bonding. FIGS. 5A-5D Describes one or more semiconductor process operations.

[0144] like FIG. 5A As shown, a bottom contact etch stop layer (B-CESL) 502 is compliantly deposited (e.g., via deposition tool 102) over the source / drain region 408, over the dummy gate structure 210, and on the sidewalls of the gate spacer 404. The B-CESL 502 provides a mechanism for stopping the etch process when forming contacts or vias for the semiconductor device 200. The B-CESL 502 can be formed of a dielectric material with a relatively high dielectric constant to provide etch selectivity for adjacent layers or elements. For example, the material of the B-CESL 502 can have a newly deposited dielectric constant greater than that of silicon oxide (SiO2). As another example, the material of the B-CESL 502 can have a newly deposited dielectric constant greater than about 3.9, such as between about 7.5 and about 10.0 or greater. The B-CESL 502 can include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, B-CESL 502 may include or may be silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or combinations thereof. B-CESL 502 can be deposited using deposition techniques such as ALD, CVD, or other deposition technologies.

[0145] like FIG. 5B As shown, an interlayer dielectric (ILD) layer 504 is formed (e.g., via deposition tool 102) above and / or on B-CESL 502. The ILD layer 504 is filled in the region between the dummy gate structures 210 above the source / drain regions 408. The ILD layer 504 is formed to allow a gate replacement process to be performed in the semiconductor device 200, wherein a metal gate structure is formed to replace the dummy gate structure 210. The ILD layer 504 may be referred to as the ILD zero (ILD0) layer.

[0146] In some embodiments, an ILD layer 504 is formed to have a height (or thickness) such that the ILD layer 504 covers the dummy gate structure 210. In these embodiments, a subsequent CMP process (e.g., performed by a planarization tool 110) is performed to planarize the ILD layer 504 such that the top surface of the ILD layer 504 is substantially at the same height as the top surface of the dummy gate structure 210. This increases the uniformity of the ILD layer 504.

[0147] like FIG. 5C As shown, a gate replacement process (e.g., using one or more of semiconductor process tools 102-112) is performed to remove the dummy gate structure 210 from the semiconductor device 200. The removal of the dummy gate structure 210 leaves a recess 506 between the gate spacers 404 and between the source / drain regions 408. The dummy gate structure 210 may be removed in one or more etching operations, including plasma etching techniques, which may include wet chemical etching techniques and / or another type of etching technique.

[0148] like FIG. 5D As shown, the gate replacement process continues, wherein the deposition tool 102 and / or the plating tool 112 form a gate structure (e.g., a gate replacement structure, a high-dielectric-constant metal gate structure) 508 in the recesses 506 between the metal spacers 404 and between the source / drain regions 408. The gate structure 508 may include a metal gate structure, a high-dielectric-constant gate structure, or another type of gate structure. The gate structure 508 may include an interface layer (not shown), a high-dielectric-constant dielectric layer 510, a work function adjustment layer 512, and a metal electrode structure 514 formed therein to form the gate structure 508. In some embodiments, the gate structure 508 may include other components of the material and / or film layers.

[0149] As mentioned above, providing FIGS. 5A-5D As an example. Other examples may be related to... FIGS. 5A-5D The descriptions are different.

[0150] FIGS. 6A-6I This is a schematic diagram of an exemplary embodiment 600 of the source / drain contacts (e.g., metal drains or MDs) of the semiconductor device 200 described herein. FIGS. 6A-6I This is from semiconductor device 200. FIG. 2 The perspective view of section AA is shown in the figure.

[0151] In some implementations, in combination FIGS. 5A-5D Following the described dummy gate replacement process, the operations described in conjunction with exemplary embodiment 600 are performed. In some embodiments, by combining FIG. 1The described one or more semiconductor process tools 102-112 and / or wafer / die transport tool 114 are used to perform the bonding. FIGS. 6A-6I Describes one or more semiconductor process operations. In some implementations, through... FIG. 1 One or more semiconductor process tools not shown are used to perform the bonding. FIGS. 6A-6I Describes one or more semiconductor process operations.

[0152] like FIG. 6A As shown, one or more dielectric layers can be formed on the semiconductor device 200. For example, a contact etch stop layer (CESL) 602 can be formed above and / or on the ILD layer 504, and an ILD layer 604 (e.g., an ILD1 layer) can be formed above and / or on the CESL 602. The deposition tool 102 can be used for bonding FIG. 1 CESL 602 is deposited in the described PVD, ALD, CVD, oxidation, another type of deposition operation, and / or other suitable deposition operations. In some embodiments, planarization tool 110 planarizes CESL 602 after deposition by deposition tool 102. Deposition tool 102 can be combined with... FIG. 1 The ILD layer 604 is deposited in the described PVD operation, ALD operation, CVD operation, epitaxial operation, oxidation operation, another type of deposition operation, and / or other suitable deposition operation. In some embodiments, the planarization tool 110 planarizes the ILD layer 604 after the deposition tool 102 has deposited the ILD layer 604.

[0153] like FIG. 6B As shown, the recess 606 is formed through one or more dielectric layers and reaches the source / drain region 408. Specifically, the ILD layer 604, CESL 602, ILD layer 504, and B-CESL 502 between the gate structures 508 in the semiconductor device 200 may be etched to form the recess 606 between the gate structures 508 and reach the source / drain region 408. The top surface of the source / drain region 408 is exposed through the recess 606. The recess 606 includes a bottom surface 606a corresponding to the top surface of the associated source / drain region 408, and a plurality of sidewalls 606b and 606c corresponding to the sides of the B-CESL 502, CESL 602, and / or ILD layer 604.

[0154] In some embodiments, a pattern in the photoresist layer is used to form the recess 606. In these embodiments, a deposition tool 102 forms a photoresist layer on the ILD layer 504 and on the gate structure 508. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. An etching tool 108 etches into the ILD layer 604, CESL 602, ILD layer 504, and / or B-CESL 502 to form the recess 606. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the recess 606.

[0155] In some embodiments, sidewalls 606b and 606c may be angled (e.g., at an angle greater than about 90 degrees) such that the sidewalls 606b and 606c on both sides of the recess 606 gradually taper between the top of the opening of the recess 606 and the bottom surface 606a of the recess 606. In these embodiments, the width of the recess 606 at the top may be greater than the width of the recess 606 at the bottom surface 606a. In some embodiments, the angle of sidewall 606c may be greater than the angle of sidewall 606b. Additionally and / or alternatively, some recesses 606 may have approximately vertical (e.g., 90 degrees) sidewalls 606b and 606c.

[0156] like FIG. 6C As shown, a source / drain contact liner 608 may be formed in a recess 606 (e.g., above the bottom surface 606a and on the sidewalls 606b and 606c). For example, the source / drain contact liner 608 may be formed on the top surface of the exposed source / drain region 408 in the recess 606. As another example, the source / drain contact liner 608 may be formed on a portion of the exposed B-CESL 502 in the recess 606. As another example, the source / drain contact liner 608 may be formed on a portion of the exposed CESL 602 in the recess 606. As another example, the source / drain contact liner 608 may be formed on a portion of the exposed ILD layer 604 in the recess 606. In some embodiments, the source / drain contact liner 608 may be formed on the top surface of the ILD layer 604.

[0157] Deposition tool 102 can be used in combination FIG. 1The material of the source / drain contact liner 608 is deposited in a PVD operation, an ALD operation, a CVD operation, an epitaxy operation, an oxidation operation, another type of deposition operation, and / or another suitable deposition operation as described. The deposition tool 102 can conformally deposit the material of the source / drain contact liner 608 such that the source / drain contact liner 608 conforms to the shape or profile of the recess 606. The material of the source / drain contact liner 608 can include silicon nitride (SixNy), silicon carbon nitride (SiCN), silicon carbide (SiC), another high-k material having a dielectric constant greater than about 3.9, a combination of the foregoing, or the like.

[0158] As shown in FIG. 6D An oxidation process operation can be performed using an oxidation process gas 610 to oxidize the source / drain contact liner 608 and / or the B-CESL 502 adjacent to the source / drain contact liner 608. The oxidation process operation can be performed to reduce the dielectric constant (e.g., k-value) of the source / drain contact liner 608 and / or the B-CESL 502 adjacent to the source / drain contact liner 608. After the oxidation process operation, the source / drain contact liner 608 and / or the B-CESL 502 adjacent to the source / drain contact liner 608 can include silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or another oxidized dielectric material.

[0159] Reducing the dielectric constant of the source / drain contact liner 608 and / or the B-CESL 502 can reduce the likelihood of and / or the amount of parasitic capacitance between the gate structure 508 and the adjacent source / drain contact to be formed in the recess 606. The amount of parasitic capacitance (CP) between the gate structure 508 and the adjacent source / drain contact can be represented as:

[0160]

[0161] where k represents a dielectric constant (e.g., k-value) of a dielectric layer (e.g., gate spacer 404, B-CESL 502, source / drain contact liner 608) between gate structure 508 and an adjacent source / drain contact; A represents an interfacial surface area between gate structure 508 and the adjacent source / drain contact; and d represents a distance between gate structure 508 and the adjacent source / drain contact. Accordingly, the parasitic capacitance CP between gate structure 508 and the adjacent source / drain contact can be proportional to the dielectric constant of the dielectric layer between gate structure 508 and the adjacent source / drain contact. Accordingly, performing an oxidation process operation to reduce the dielectric constant of source / drain contact liner 608 and / or B-CESL 502 can reduce the parasitic capacitance CP between gate structure 508 and the adjacent source / drain contact.

[0162] The oxidation process operation can include providing an oxidation process gas 610 into recess 606 such that oxygen atoms in oxidation process gas 610 diffuse into source / drain contact liner 608 and / or B-CESL 502, thereby increasing an oxygen concentration (and reducing a dielectric constant) of a material of source / drain contact liner 608 and / or a material of B-CESL 502. Oxidation process gas 610 can include ozone (O3), oxygen (O2), and / or other oxygen-containing gas. Oxidation process gas 610 can include one or more additional gases (e.g., carrier gas, plasma reaction gas), such as hydrogen (H2), nitrogen (N2), and / or argon (Ar), among others.

[0163] In some implementations, deposition tool 102 can provide oxidation process gas 610 into recess 606 in the oxidation process operation. Deposition tool 102 can control the flow of oxidation process gas 610 into recess 606 and / or use a plasma to facilitate a reaction between oxidation process gas 610 and source / drain contact liner 608 and / or B-CESL 502. The plasma can include an argon- based plasma, a hydrogen-based plasma, a nitrogen-based plasma, and / or another type of plasma. Deposition tool 102 can generate the plasma remotely (e.g., outside of a process chamber in which semiconductor device 200 is located), can generate the plasma using inductively coupled plasma (ICP) techniques, and / or can generate the plasma using capacitively coupled plasma (CCP) techniques, among others.

[0164] In some implementations, the deposition tool 102 can increase the temperature of the semiconductor device 200 such that the temperature of the semiconductor device 200 is included in a range from about 50 degrees Celsius to about 100 degrees Celsius. If the temperature is less than about 50 degrees Celsius, a reaction can not occur between the oxidation process gas 610 and the source / drain contact liner 608 and / or the B-CESL 502. If the temperature is greater than about 450 degrees Celsius, the high temperature can cause damage to other structures of the semiconductor device 200, such as the gate structure 508. However, other values of the range are also within the scope of the present disclosure.

[0165] In some implementations, the deposition tool 102 can perform the oxidation process operation at a pressure in the process chamber included in a range from about 1 millitorr to about 10 torr. If the pressure is less than about 1 millitorr or greater than about 10 torr, the deposition tool 102 can not be able to effectively control the flow of the oxidation process gas 610 into the recess 606 using a plasma. However, other values of the range are also within the scope of the present disclosure.

[0166] In some implementations, the deposition tool 102 can perform the oxidation process operation using a plasma bias power included in a range from about 200 watts to about 4000 watts. If the plasma bias power is less than about 200 watts, a reaction can not occur between the oxidation process gas 610 and the source / drain contact liner 608 and / or the B-CESL 502. If the plasma bias power is greater than about 4000 watts, the bombardment energy of the plasma can cause ions to penetrate the source / drain contact liner 608, which can cause damage to the source / drain regions 408 below the source / drain contact liner 608. However, other values of the range are also within the scope of the present disclosure.

[0167] In some implementations, the deposition tool 102 can perform the oxidation process operation for a duration included in a range from about 5 seconds to about 600 seconds. If the duration is less than about 5 seconds, the duration can be too short to sufficiently increase the oxygen concentration in the B-CESL 502 and / or the source / drain contact liner 608. If the duration is greater than about 600 seconds, oxidation can occur in the source / drain regions 408, which can cause damage to the source / drain regions 408. However, other values of the range are also within the scope of the present disclosure.

[0168] As FIG. 6EAs shown, the source / drain contact liner 612 can be formed in a recess 606 on the source / drain contact liner 608 (e.g., above the bottom surface 606a and on the sidewalls 606b and 606c). Specifically, the source / drain contact liner 612 can be formed in the recess 606 after an oxidation process. The material of the source / drain contact liner 612 can include a high dielectric constant material to provide etch selectivity and / or withstand subsequent semiconductor processing operations. Forming the source / drain contact liner 612 after an oxidation process allows the source / drain contact liner 612 to retain the high dielectric constant characteristics of the newly deposited material used for the source / drain contact liner 612.

[0169] Deposition tool 102 can be used in combination FIG. 1 The material for depositing the source / drain contact liner 612 in the described PVD, ALD, CVD, epitaxial, oxidation, other types of deposition operations, and / or other suitable deposition operations. The deposition tool 102 can conformally deposit the material of the source / drain contact liner 612 such that the source / drain contact liner 612 conforms to the shape or contour of the recess 606. The material of the source / drain contact liner 612 may include silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbide (SiOC), other high dielectric constant materials having a dielectric constant greater than about 3.9, or combinations thereof.

[0170] like FIG. 6F As shown, an etching (or punch-through) operation can be performed to remove multiple portions of the source / drain contact liner 608 and multiple portions of the source / drain contact liner 612 (e.g., corresponding to the top surface of the source / drain region 408) from the bottom surface 606a of the recess 606. In some embodiments, multiple portions of the source / drain contact liner 608 and multiple portions of the source / drain contact liner 612 may also be removed from the sidewalls 606c of the recess 606 during the etching operation. Removing multiple portions of the source / drain contact liner 608 and multiple portions of the source / drain contact liner 612 from the bottom surface 606a of the recess 606 again exposes the top surface of the source / drain region 408 in the recess 606. The materials included in the source / drain contact liner 612 and the source / drain contact liner 608 include dielectric materials and therefore have relatively high resistivity. Therefore, multiple portions of the source / drain contact liner 608 and multiple portions of the source / drain contact liner 612 are located away from the bottom surface 606a of the recess 606, so that sufficiently low sheet resistance and / or contact resistance can be achieved between the source / drain region 408 and the source / drain contact to be formed on the source / drain region 408.

[0171] In some embodiments, a recess 606 is formed in a portion of the source / drain region 408 (e.g., by over-etching), such that the recess 606 extends into the portion of the source / drain region 408. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique.

[0172] like FIG. 6G As shown, a metal silicide layer 614 can be formed on the source / drain contact liner 612 in the recess 606 and on the top surface of the source / drain region 408. The metal silicide layer 614 may include titanium silicide (TiSix), cobalt silicide (CoSix), or other metal silicide layers. The deposition tool 102 can deposit a thin layer of metal material on the top surface of the source / drain region 408 and on the source / drain contact liner 612. The deposition tool 102 can also deposit a thin layer of metal material on the bonding... FIG. 1 The described CVD operation, PVD operation, ALD operation, another type of deposition technique, and / or in addition to the combination FIG. 1 Other deposition techniques described are used to deposit metallic materials and then perform an annealing operation, wherein the temperature of the semiconductor device 200 is rapidly increased to allow atoms from the metal layer to diffuse into the top surface of the source / drain region 408, thereby forming a metal silicide layer 614.

[0173] In some embodiments, a pre-cleaning operation is performed to clean the surfaces in the recess 606 prior to the formation of the metal silicide layer 614. Specifically, the semiconductor device 200 may be located in a process chamber (e.g., a pre-cleaning process chamber) of the deposition tool 102, which may be pumped down to at least a partial vacuum (e.g., pressurized to a pressure ranging from about 5 to about 10 Torr, or to another pressure), and the bottom surface 602a and sidewalls 602b in the recess 606 are cleaned using plasma-based and / or chemical-based pre-cleaning agents. The pre-cleaning operation cleans (e.g., removes) oxides and other contaminants or byproducts from the top surface of the source / drain region 408, which may be formed after the formation of the recess 606. The reduction in the amount of oxides and other contaminants on the top surface of the source / drain region 408 due to the pre-cleaning operation allows for a sufficiently low contact resistance between the metal silicide layer 614 and the source / drain region 408.

[0174] The source / drain contact liner 612 on the source / drain contact liner 608 (both on the sidewalls 602b and 602c of the recess 606) protects the source / drain contact liner 608 from damage and / or removal from the sidewalls 602b and 602c during pre-cleaning operations. As described above... FIG. 6DThe oxidation process results in an increase in oxygen concentration (e.g., an increase in oxide concentration) in the material of the source / drain contact liner 608. Since a pre-cleaning agent is used in the pre-cleaning process to remove oxides from the semiconductor device 200, the increased oxygen concentration increases the likelihood of removal and / or damage to the source / drain contact liner 608. Therefore, the source / drain contact liner 612 serves as a protective or sacrificial layer, protecting the high oxygen concentration material of the source / drain contact liner 608 from the effects of the pre-cleaning agent.

[0175] like FIG. 6H and FIG. 6I As shown, source / drain contacts 618 are formed in semiconductor device 200. Specifically, source / drain contacts 618 are formed in recesses 606 between gate structures 508, such that source / drain contacts 618 are located above and electrically coupled to source / drain regions 408.

[0176] like FIG. 6H As shown, the deposition tool 102 and / or electroplating tool 112 can be used in combination with FIG. 1 The described CVD operation, PVD operation, ALD operation, another type of deposition technique, and / or in addition to the combination FIG. 1 Other deposition techniques are described to deposit material 616 of source / drain contact 618. Material 616 of source / drain contact 618 may include one or more conductive materials (such as titanium (Ti), cobalt (Co), copper (Cu), ruthenium (Ru), tungsten (W), molybdenum (Mo)), conductive metal materials, conductive ceramic materials, metal alloy materials, another conductive material, or a combination thereof.

[0177] like FIG. 6I As shown, planarization tool 110 can perform CMP operation or another type of planarization to planarize the material 616 of the source / drain contact 618. Planarization tool 110 can planarize the source / drain contact 618 to remove excess material 616 from the source / drain contact 618, such that the top surface of the source / drain contact 618 is substantially coplanar with the top surface of the ILD layer 604.

[0178] like FIG. 6IFurther shown, the semiconductor device 200 can include a fin structure 206 extending over a substrate 204 of the semiconductor device 200, a gate structure 508 wrapping at least three sides of the fin structure 206, and a first source / drain region 408 and a second source / drain region 408 on the fin structure 206. The first source / drain region 408 and the second source / drain region 408 can be located on either side of the gate structure 508. The semiconductor device 200 can also include a source / drain contact 618 over the first source / drain region 408 and adjacent to the gate structure 508, a B-CESL 502 between the gate structure 508 and the source / drain contact 618, a gate spacer 404 between the B-CESL 502 and the gate structure 508, and a source / drain contact liner 608 between the B-CESL 502 and the source / drain contact 618. The dielectric constant of the source / drain contact liner 608 can be less than the dielectric constant of the gate spacer 404, and the dielectric constant of the B-CESL 502 can be less than the dielectric constant of the gate spacer 404. The oxygen concentration of the material of the source / drain contact liner 608 can be greater than the oxygen concentration of the material of the gate spacer 404, and the oxygen concentration of the material of the B-CESL 502 can be greater than the oxygen concentration of the material of the gate spacer 404.

[0179] The semiconductor device 200 can also include a source / drain contact liner 612 between the source / drain contact liner 608 and the source / drain contact 618. The thickness of the source / drain contact liner 608 can be greater than the thickness of the source / drain contact liner 612. The dielectric constant of the source / drain contact liner 608 can be less than the dielectric constant of the source / drain contact liner 612. The oxygen concentration of the material of the source / drain contact liner 608 can be greater than the oxygen concentration of the material of the source / drain contact liner 612. The semiconductor device 200 can also include a metal silicide layer 614 between the source / drain contact liner 612 and the source / drain contact 618.

[0180] As described above, there is provided FIGS. 6A-6I by way of illustration. Other FIGS. 6A-6I may differ from those described with respect to the described embodiments.

[0181] FIG. 7 is a schematic diagram of an exemplary implementation 700 of one or more exemplary dimensions of the semiconductor device 200 described herein.

[0182] As FIG. 7As shown, exemplary dimension Dl can include a height or thickness of the source / drain contact 618 of the semiconductor device 200. In some embodiments, exemplary dimension Dl can be in a range from about 10 nanometers to about 100 nanometers. If exemplary dimension Dl is less than about 10 nanometers, a top surface of the source / drain contact 618 can be at a lower height than the gate structure 508 in the semiconductor device 200, which can result in the inability to planarize the source / drain contact 618. If exemplary dimension Dl is greater than about 100 nanometers, the source / drain contact 618 can not be reliably etched to the recess 606 located therein, and / or voids and other discontinuities can be formed in the source / drain contact 618. However, other values of the range are within the scope of the present disclosure.

[0183] Another exemplary dimension D2 can include a height or thickness of a bottom portion of the metal silicide layer 614 between the source / drain contact 618 and the underlying source / drain region 408 of the semiconductor device 200. In some embodiments, exemplary dimension D2 can be in a range from about 3 nanometers to about 10 nanometers. Exemplary dimension D2 less than about 3 nanometers can result in poor electrical contact and, thus, high contact resistance between the source / drain contact 618 and the underlying source / drain region 408. If exemplary dimension D2 is greater than about 10 nanometers, a remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap-filling performance in the recess 606. However, other values of the range are within the scope of the present disclosure.

[0184] Another exemplary dimension D3 can include a thickness of the source / drain contact liner 608 on a sidewall of the source / drain contact 618. In some embodiments, exemplary dimension D3 can be in a range from about 3 nanometers to about 10 nanometers. Exemplary dimension D3 less than about 3 nanometers can result in a large amount of leakage current between the source / drain contact 618 and the gate structure 508. If exemplary dimension D3 is greater than about 10 nanometers, a remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap-filling performance in the recess 606. However, other values of the range are within the scope of the present disclosure.

[0185] Another illustrative dimension D4 can include a thickness of the source / drain contact liner 612 on the sidewall of the source / drain contact 618. In some embodiments, the illustrative dimension D4 can include a range of about 2 nanometers to about 9 nanometers. An illustrative dimension D4 less than about 2 nanometers can result in a substantial amount of leakage current between the source / drain contact 618 and the gate structure 508. If the illustrative dimension D4 is greater than about 9 nanometers, then the remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap fill performance in the recess 606. However, other values of the range are also within the scope of the present disclosure. The illustrative dimension D3 (e.g., thickness of the source / drain contact liner 608) can be greater than the illustrative dimension D4 (e.g., thickness of the source / drain contact liner 612) due to the etching of the source / drain contact liner 612 on the sidewall 606b of the recess 606 during the operations to remove the source / drain contact liner 608 from the bottom surface 606a of the recess 606 and the source / drain contact liner 612.

[0186] Another illustrative dimension D5 can include a thickness of the metal silicide layer 614 on the sidewall of the source / drain contact 618. In some embodiments, the illustrative dimension D5 can include a range of about 1 nanometer to about 8 nanometers. An illustrative dimension D5 less than about 1 nanometer can result in discontinuities in the metal silicide layer 614. If the illustrative dimension D5 is greater than about 8 nanometers, then the remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap fill performance in the recess 606. However, other values of the range are also within the scope of the present disclosure.

[0187] Another illustrative dimension D6 can include a thickness of the B-CESL 502. In some embodiments, the illustrative dimension D6 can include a range of about 3 nanometers to about 10 nanometers. An illustrative dimension D6 less than about 3 nanometers can result in a substantial amount of leakage current between the source / drain contact 618 and the gate structure 508. If the illustrative dimension D6 is greater than about 10 nanometers, then the remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap fill performance in the recess 606. In addition, the gap fill performance of the gate structure 508 can also be reduced due to the reduced volume in the recess 506 forming the gate structure 508. However, other values of the range are also within the scope of the present disclosure.

[0188] Another example dimension D7 can include a thickness of the gate spacer 404. In some implementations, example dimension D7 can be included in a range from about 3 nanometers to about 10 nanometers. An example dimension D7 less than about 3 nanometers can result in a substantial amount of leakage current between the source / drain contact 618 and the gate structure 508. If the example dimension D7 is greater than about 10 nanometers, then the remaining amount of unfilled volume in the recess 606 can be insufficient for the source / drain contact 618, which can result in reduced gap fill performance in the recess 606. In addition, the gap fill performance of the gate structure 508 can also be reduced due to the reduced volume in the recess 506 in which the gate structure 508 is formed. However, other values of the range are also within the scope of the present disclosure.

[0189] Another example dimension D8 can include a distance or spacing between the gate structure 508 and the adjacent source / drain contact 618. In some implementations, example dimension D8 can be included in a range from about 5 nanometers to about 20 nanometers. An example dimension D8 less than about 5 nanometers can result in a substantial amount of leakage current between the source / drain contact 618 and the gate structure 508. If the example dimension D8 is greater than about 20 nanometers, then a sufficiently high transistor density in the semiconductor device 200 can not be achieved. However, other values of the range are also within the scope of the present disclosure.

[0190] As described above, providing FIG. 7 is illustrative. Other examples can differ from what is described with respect to FIG. 7 what is described.

[0191] FIG. 8 is a schematic diagram of an example implementation 800 of a group of elements that make up a portion of the semiconductor device 200 described herein. FIG. 8 is a schematic diagram of a group of elements that make up a portion of the semiconductor device 200 after the oxidation treatment operation described in connection with FIG. 6D.

[0192] As FIG. 8 shown, the portion of the semiconductor device 200 can include a lateral portion that spans the source / drain contact 618, and can include a portion of the gate structure 508, a portion of the gate spacer 404 on both sides of the gate structure 508, a portion of the B-CESL 502 on the gate spacer 404, a portion of the source / drain contact liner 608 on the B-CESL 502, a portion of the source / drain contact liner 612 on the source / drain contact liner 608, a portion of the metal silicide layer 614 on the source / drain contact liner 612, and a portion of the source / drain contact 618. FIG. 8The illustrated element composition can include an element concentration 802 of nitrogen 806 and oxygen 808 as a function of lateral position 804 in the semiconductor device 200. The element concentration 802 can include a number of atoms (e.g., oxygen atoms) per cubic centimeter or another concentration or density parameter.

[0193] As FIG. 8 illustrated, as a result of the oxidation treatment operation, the element concentration 802 of oxygen 808 in the B-CESL 502 and the source / drain contact liner 608 can be greater than the element concentration 802 of nitrogen 806. As described above, the oxidation treatment operation can be performed to increase the element concentration 802 of oxygen 808 in the material of the B-CESL 502 and / or in the material of the source / drain contact liner 608, thereby reducing the dielectric constant in the B-CESL 502 and / or the source / drain contact liner 608. The reduction in the dielectric constant of the B-CESL 502 and / or the reduction in the dielectric constant of the source / drain contact liner 608 can reduce the likelihood of and / or the amount of parasitic capacitance that occurs between the source / drain contacts 618 and the gate structure 508 adjacent to the source / drain contacts 618. Forming the B-CESL 502 and / or the source / drain contact liner 608 can include depositing a nitrogen-containing material, and the oxidation treatment operation can result in the element concentration 802 of oxygen 808 in the nitrogen-containing material being greater than the relative element concentration 802 of nitrogen 806 in the nitrogen-containing material.

[0194] As FIG. 8 further illustrated, the element concentration 802 of oxygen 808 in the material of the B-CESL 502 can be greater than the element concentration 802 of oxygen 808 in the material of the gate spacers 404 and can be greater than the element concentration 802 of oxygen 808 in the material of the source / drain contact liner 612. Similarly, the element concentration 802 of oxygen 808 in the material of the source / drain contact liner 608 can be greater than the element concentration 802 of oxygen 808 in the material of the gate spacers 404 and can be greater than the element concentration 802 of oxygen 808 in the material of the source / drain contact liner 612. This occurs as a result of depositing the high dielectric constant material of the source / drain contact liner 612 after the oxidation treatment operation described in connection with FIG. 6D. Thus, the source / drain contact liner 612 can retain high dielectric constant properties compared to the source / drain contact liner pad 612, which is also treated in the oxidation treatment operation, which enables the source / drain contact liner 612 to better protect the source / drain contact liner 608 during the pre-clean operation described above.

[0195] As described above, providing FIG. 8 as an example. Other examples can differ from what is described with regard to what is described in connection with FIG. 8 FIGS. 6A-6D.

[0196] FIG. 9is a schematic diagram of exemplary elements of the apparatus 900 described herein. In some implementations, one or more semiconductor processing tools 102-112 and / or wafer / die transport tools 114 can include one or more apparatuses 900 and / or elements of one or more apparatuses 900. As shown, the apparatus 900 can include a bus 910, a processor 920, a memory 930, input elements 940, output elements 950, and / or communication elements 960. FIG. 9

[0197] The bus 910 includes one or more elements that enable wired and / or wireless communication between elements in the apparatus 900. The bus 910 can couple two or more elements of the apparatus 900 together, such as by operative coupling, communicative coupling, electronic coupling, and / or electric coupling. The processor 920 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or other processing elements. The processor 920 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, the processor 920 includes one or more processors and can be programmed to perform one or more operations or processes described elsewhere herein. FIG. 9

[0198] ​​The memory 930 includes volatile and / or nonvolatile memory. For example, the memory 930 can include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 930 can include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable through a universal serial bus connection). The memory 930 can be a non-transitory computer-readable medium. The memory 930 stores information related to the operation of the device 900, one or more instructions, and / or software (e.g., software applications). In some implementations, the memory 930 includes one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., the processor 920) by the bus 910. The communicative coupling between the processor 920 and the memory 930 can enable the processor 920 to read and / or process information stored in the memory 930 and / or store information in the memory 930.

[0199] Input elements 940 enable the device 900 to receive input, such as user input and / or sensed input. For example, the input elements 940 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and / or an actuator. Output elements 950 enable the device 900 to provide output, such as through a display, a speaker, and / or a light-emitting diode. Communication elements 960 enable the device 900 to communicate with other devices over wired and / or wireless connections. For example, the communication elements 960 can include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0200] The device 900 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., the memory 930) can store a set of instructions (e.g., one or more instructions or code) for execution by the processor 920. The processor 920 can execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions by the one or more processors 920 causes the one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry can be used in place of or in combination with software instructions to perform one or more operations or processes described herein. Additionally, or alternatively, the processor 920 can be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

[0201] FIG. 9 The number and arrangement of elements shown in FIG. 9 are provided as an example. Device 900 can include additional elements, such as one or more sensors, processors, or memories, or can have a different number or arrangement of elements than those shown in FIG. 9. FIG. 9The elements of the device 900 are, optionally, combined with additional elements, fewer elements, different elements, or differently arranged elements as desired. Additionally or alternatively, a set of one or more elements of the device 900 can perform one or more functions described as being performed by another set of one or more elements of the device 900.

[0202] FIG. 10 is a flow diagram of an exemplary process 1000 related to semiconductor device formation. In some embodiments, one or more process blocks of FIG. 10 may be performed by one or more of the semiconductor process tools, e.g., one or more of the semiconductor process tools 102-112. Additionally or alternatively, one or more process blocks of FIG. 10 may be performed by one or more elements of the device 900, such as the processor 920, the memory 930, the input element 940, the output element 950, and / or the communication element 960.

[0203] As shown in FIG. 10 , the process 1000 can include forming a fin structure over a substrate (block 1010). For example, as described above, one or more of the semiconductor process tools 102-112 can form the fin structure 206 over the substrate 204.

[0204] As further shown in FIG. 10 , the process 1000 can include forming a gate structure that wraps around the fin structure on at least three sides of the fin structure (block 1020). For example, as described above, one or more of the semiconductor process tools 102-112 can form the gate structure 508 that wraps around the fin structure 206 on at least three sides of the fin structure 206.

[0205] As further shown in FIG. 10 , the process 1000 can include forming a first source / drain region and a second source / drain region on the fin structure (block 1030). For example, as described above, one or more of the semiconductor process tools 102-112 can form the first source / drain region 408 and the second source / drain region 408 on the fin structure 206. In some embodiments, the gate structure 508 is between the first source / drain region 408 and the second source / drain region 408.

[0206] As further shown in FIG. 10 , the process 1000 can include forming a recess over the first source / drain region (block 1040). For example, as described above, one or more of the semiconductor process tools 102-112 can form the recess 606 over the first source / drain region 408. In some embodiments, the recess 606 is adjacent to the gate structure 508.

[0207] As FIG. 10 Further, process 1000 can include forming a liner on the recessed sidewalls (block 1050). For example, as described above, one or more of semiconductor process tools 102-112 can form a liner (e.g., source / drain contact liner 608) on sidewalls 606b and / or 606c of recess 606.

[0208] As FIG. 10 Further, process 1000 can include performing an oxidation process operation to oxidize the liner (block 1060). For example, as described above, one or more of semiconductor process tools 102-112 can perform an oxidation process operation to oxidize the liner (e.g., source / drain contact liner 608).

[0209] As FIG. 10 Further, process 1000 can include forming a source / drain contact over the liner in the recess such that the source / drain contact is coupled with the first source / drain region (block 1070). For example, as described above, one or more of semiconductor process tools 102-112 can form source / drain contact 618 over the liner (e.g., source / drain contact liner 608) in recess 606 such that source / drain contact 618 is coupled with first source / drain region 408.

[0210] Process 1000 can include additional implementations, such as those described below and / or any single implementation or any combination of implementations of one or more other processes described elsewhere herein.

[0211] In a first implementation, a dielectric constant of a material of the liner (e.g., source / drain contact liner 608) is reduced as a result of the oxidation process operation.

[0212] In a second implementation, alone or in combination with the first implementation, forming the liner (e.g., source / drain contact liner 608) includes depositing a nitrogen-containing material to form the liner (e.g., source / drain contact liner 608), wherein the oxidation process operation results in an oxygen concentration in the nitrogen-containing material being greater than a nitrogen concentration in the nitrogen-containing material.

[0213] In a third implementation, alone or in combination with one or more of the first and second implementations, performing the oxidation process operation includes performing the oxidation process operation to achieve a dielectric constant of a material of the liner that satisfies a critical dielectric constant.

[0214] In a fourth implementation, alone or in combination with one or more of the first through third implementations, the process 1000 includes forming a bottom contact etch stop layer (B-CESL) (502) after forming the first source / drain region and the second source / drain region, wherein forming the liner includes forming a portion of the liner on the B-CESL in the recess, and wherein performing the oxidation treatment operation includes performing the oxidation treatment operation to oxidize the B-CESL.

[0215] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, forming the B-CESL includes depositing a nitride-containing material to form the B-CESL, wherein the oxidation treatment operation results in an oxygen concentration in the nitride-containing material being greater than a nitride concentration in the nitride-containing material.

[0216] In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, a dielectric constant of a material of the B-CESL 502 is reduced as a result of the oxidation treatment operation.

[0217] Although FIG. 10 exemplary blocks of the process 1000 are shown, in some implementations, the process 1000 can include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 10 Additionally or alternatively, two or more of the blocks of the process 1000 can be performed in parallel.

[0218] FIG. 10 is a flow diagram of an exemplary process 1100 related to semiconductor device formation. In some implementations, one or more of the process blocks of FIG. 11 may be performed by one or more of the semiconductor process tools, e.g., one or more of the semiconductor process tools 102-112. Additionally or alternatively, one or more of the process blocks of FIG. 11 may be performed by one or more elements of the apparatus 900, such as the processor 920, the memory 930, the input element 940, the output element 950, and / or the communication element 960.

[0219] As shown in FIG. 10 , the process 1100 can include forming a fin structure over a substrate (block 1110). For example, as described above, one or more of the semiconductor process tools 102-112 can form the fin structure 206 over the substrate 204.

[0220] As shown in FIG. 11Further, process 1100 can include forming a gate structure that wraps around the fin structure on at least three sides of the fin structure (block 1120). For example, as described above, one or more of semiconductor process tools 102-112 can form gate structure 508 that wraps around fin structure 206 on at least three sides of fin structure 206.

[0221] As FIG. 11 Further, process 1100 can include forming a first source / drain region and a second source / drain region on the fin structure (block 1130). For example, as described above, one or more of semiconductor process tools 102-112 can form first source / drain region 408 and second source / drain region 408 on fin structure 206. In some embodiments, gate structure 508 is between first source / drain region 408 and second source / drain region 408.

[0222] As FIG. 11 Further, process 1100 can include forming a recess over the first source / drain region (block 1140). For example, as described above, one or more of semiconductor process tools 102-112 can form recess 606 over first source / drain region 408. In some embodiments, recess 606 is adjacent to gate structure 508.

[0223] As FIG. 11 Further, process 1100 can include forming a first liner on sidewalls of the recess (block 1150). For example, as described above, one or more of semiconductor process tools 102-112 can form a first liner (e.g., source / drain contact liner 608) on sidewalls 606b and / or 606c of recess 606.

[0224] As FIG. 11 Further, process 1100 can include performing an oxidation process operation to oxidize the first liner (block 1160). For example, as described above, one or more of semiconductor process tools 102-112 can perform an oxidation process operation to oxidize the first liner (e.g., source / drain contact liner 608).

[0225] As FIG. 11 Further, process 1100 can include forming a second liner on the first liner after performing the oxidation process operation (block 1170). For example, as described above, one or more of semiconductor process tools 102-112 can form a second liner (e.g., source / drain contact liner 612) on the first liner (e.g., source / drain contact liner 608) after performing the oxidation process operation.

[0226] As FIG. 11 Further shown, process 1100 can include forming a source / drain contact over the second liner in the recess such that the source / drain contact is coupled with the first source / drain region (block 1180). For example, as described above, one or more of semiconductor process tools 102-112 can form source / drain contact 618 over second liner (e.g., source / drain contact liner 612) in recess 606 such that source / drain contact 618 is coupled with first source / drain region 408.

[0227] Process 1100 can include additional implementations, such as any single implementation or any combination of implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0228] In a first implementation, forming the first liner (e.g., source / drain contact liner 608) includes depositing the first liner on a bottom surface 606a of recess 606, wherein forming the second liner (e.g., source / drain contact liner 612) includes depositing the second liner on the first liner, and process 1100 includes removing a portion of the first liner and a portion of the second liner over the bottom surface 606a of recess 606 such that a top surface of the first source / drain region 408 is exposed in recess 606, wherein a remaining portion of the first liner and a remaining portion of the second liner remain on sidewalls (e.g., sidewall 606b, sidewall 606c) of recess 606.

[0229] In a second implementation, alone or in combination with the first implementation, process 1100 includes performing a pre-clean operation in recess 606 to remove native oxide from a top surface of first source / drain region 408, wherein the second liner (e.g., source / drain contact liner 612) protects the first liner (e.g., source / drain contact liner 608) during the pre-clean operation, and forming a metal silicide layer 614 on the top surface of first source / drain region 408, wherein forming source / drain contact 618 includes forming source / drain contact 618 on metal silicide layer 614.

[0230] In a third implementation, alone or in combination with one or more of the first and second implementations, a first dielectric constant of the first liner (e.g., source / drain contact liner 608) is less than a second dielectric constant of the second liner (e.g., source / drain contact liner 612) after the oxidation treatment operation.

[0231] In a fourth implementation, alone or in combination with one or more of the first and third implementations, a first oxygen concentration of a first nitrogen-containing material of a first liner (e.g., source / drain contact liner 608) is greater than a second oxygen concentration of a second nitrogen-containing material of a second liner (e.g., source / drain contact liner 612) after the oxidizing process operation.

[0232] In a fifth implementation, alone or in combination with one or more of the first and fourth implementations, the process 1100 includes forming the B-CESL 502 after forming the first source / drain region and the second source / drain region, wherein forming the first liner (e.g., source / drain contact liner 608) includes forming a portion of the first liner on the B-CESL 502 in the recess 606, and wherein performing the oxidizing process operation includes performing the oxidizing process operation to oxidize the B-CESL 502.

[0233] Although FIG. 11 Exemplary blocks of the process 1100 are shown, but in some implementations, the process 1100 can include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 11. Additionally or alternatively, two or more of the blocks of the process 1100 can be performed in parallel. FIG. 11 Exemplary blocks of the process 1100 are shown, but in some implementations, the process 1100 can include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 11. Additionally or alternatively, two or more of the blocks of the process 1100 can be performed in parallel.

[0234] As such, a semiconductor device can include a plurality of transistor structures. The transistor structures can include a plurality of source / drain regions, a semiconductor channel region between the source / drain regions, and a gate structure configured to selectively control a conductivity of the semiconductor channel region between the source / drain regions, thereby enabling the transistor structure to switch between an on state and an off state. The semiconductor device can also include one or more layers of dielectric layers between a source / drain contact structure (e.g., a metal drain (MD)) and a gate structure (e.g., a metal gate (MG)) of one or more of the transistor structures. The one or more layers of dielectric layers can be fabricated using an oxidizing process to adjust a dielectric constant of the one or more layers of dielectric layers. The dielectric constant of the one or more layers of dielectric layers can be adjusted to reduce a parasitic capacitance between the source / drain contact structure and the gate structure, which is a conductive structure. In particular, the dielectric constant of the one or more layers of spacer dielectrics can be adjusted using the oxidizing process to reduce an as-deposited dielectric constant of the one or more layers of dielectric layers.

[0235] As such, after depositing the one or more dielectric layers, an oxidation process can be used to reduce the dielectric constant of the one or more dielectric layers. This enables the high dielectric constant to be maintained after depositing the one or more dielectric layers, which enables the one or more dielectric layers to better withstand damage from one or more subsequent semiconductor process operations (e.g., etching operations, pre-cleaning operations) after depositing the one or more dielectric layers.

[0236] Further, this enables the dielectric constant of the one or more dielectric layers to be subsequently reduced, which can reduce the parasitic capacitance between the source / drain contact structure and the gate structure as the transistor structure operates, since the parasitic capacitance between the source / drain contact structure and the gate structure can be directly proportional to the dielectric constant of the one or more dielectric layers between the source / drain contact structure and the gate structure. The reduced parasitic capacitance can shorten the switching time of the transistor structure, which can improve the performance of the semiconductor device and / or can reduce processing errors in the semiconductor device.

[0237] As described in greater detail above, some embodiments described herein provide a method of manufacturing a semiconductor device. The method includes forming a fin structure over a substrate. The method includes forming a gate structure that wraps around the fin structure on at least three sides of the fin structure. The method includes forming a first source / drain region and a second source / drain region on the fin structure, with the gate structure between the first source / drain region and the second source / drain region. The method includes forming a recess over the first source / drain region, with the recess adjacent to the gate structure. The method includes forming a liner on sidewalls of the recess. The method includes performing an oxidation process to oxidize the liner. The method includes forming a source / drain contact over the liner in the recess, such that the source / drain contact is coupled with the first source / drain region.

[0238] As described in greater detail above, some embodiments described herein provide a semiconductor device; a first source / drain region and a second source / drain region over a substrate; a gate structure, the first source / drain region and the second source / drain region on two sides of the gate structure; a source / drain contact over the first source / drain region and adjacent to the gate structure; a B-CESL between the gate structure and the source / drain contact; a gate spacer between the B-CESL and the gate structure; a source / drain contact liner between the B-CESL and the source / drain contact, wherein a first oxygen concentration of a first material of the source / drain contact liner is greater than a second oxygen concentration of a second material of the gate spacer, and wherein a third oxygen concentration of a third material of the B-CESL is greater than the second oxygen concentration of the second material of the gate spacer.

[0239] As described in more detail above, some embodiments described herein provide a method of manufacturing a semiconductor device. The method includes forming a fin structure over a substrate. The method includes forming a gate structure that wraps around the fin structure on at least three sides of the fin structure. The method includes forming a first source / drain region and a second source / drain region on the fin structure, with the gate structure between the first source / drain region and the second source / drain region. The method includes forming a recess over the first source / drain region, the recess adjacent to the gate structure. The method includes forming a first liner on sidewalls of the recess. The method includes performing an oxidation process operation to oxidize the first liner. The method includes forming a second liner on the first liner after performing the oxidation process operation. The method includes forming a source / drain contact over the second liner in the recess, such that the source / drain contact is coupled with the first source / drain region.

[0240] As used herein, "satisfies a threshold value" can refer to greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, etc., depending on the context.

[0241] The components of the above summary outline several embodiments in order to provide a clearer view of the present disclosure to those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures according to the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a first source / drain region and a second source / drain region over a substrate; a gate structure, the first source / drain region and the second source / drain region being on two sides of the gate structure; a source / drain contact over the first source / drain region and adjacent to the gate structure; a bottom contact etch stop layer between the gate structure and the source / drain contact; a gate spacer between the bottom contact etch stop layer and the gate structure; and a source / drain contact liner between the bottom contact etch stop layer and the source / drain contact, wherein a first oxygen concentration of a first material of the source / drain contact liner is greater than a second oxygen concentration of a second material of the gate spacer; and wherein a third oxygen concentration of a third material of the bottom contact etch stop layer is greater than the second oxygen concentration of the second material of the gate spacer. wherein a first dielectric constant of the source / drain contact liner is less than a second dielectric constant of the gate spacer.

2. The semiconductor device according to claim 1, wherein wherein a first dielectric constant of the bottom contact etch stop layer is less than a second dielectric constant of the gate spacer.

3. The semiconductor device according to claim 1, wherein wherein the source / drain contact liner comprises a first source / drain contact liner; and 4. The semiconductor device according to claim 1, wherein wherein the semiconductor device further comprises: a second source / drain contact liner between the first source / drain contact liner and the source / drain contact. wherein a first thickness of the first source / drain contact liner is greater than a second thickness of the second source / drain contact liner. wherein the first thickness is in a range of 3 nanometers to 10 nanometers and the second thickness is in a range of 2 nanometers to 9 nanometers.

5. The semiconductor device according to claim 4, wherein wherein a first dielectric constant of the first source / drain contact liner is less than a second dielectric constant of the second source / drain contact liner.

6. The semiconductor device according to claim 5, wherein wherein the first oxygen concentration of the first material of the first source / drain contact liner is greater than a fourth oxygen concentration of a fourth material of the second source / drain contact liner.

7. The semiconductor device according to claim 4, wherein wherein a distance between the gate structure and the source / drain contact is in a range of 5 nanometers to 20 nanometers.

8. The semiconductor device according to claim 4, wherein further comprising a fin structure over the substrate, wherein the gate structure wraps around the fin structure on at least three sides of the fin structure.

9. The semiconductor device according to claim 1, wherein ​ 10. The semiconductor device according to any one of Claims 1-9, wherein ​

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