Semiconductor device

Abstract

A semiconductor device includes a first fin and a second fin protruding from a substrate and extending lengthwise in a first direction; the first gate stack and the second gate stack are arranged on the first fin and the second fin and extend in the length direction, and the second direction is perpendicular to the first direction; the first gate spacer layer and the second gate spacer layer are arranged on the side walls of the first gate stack and the second gate stack respectively; a first epitaxial member and a second epitaxial member on the first fin and the second fin, respectively, and sandwiched between the first gate stack and the second gate stack; a first silicide layer and a first contact member on the first epitaxial member in sequence; a second silicide layer and a second contact member on the second epitaxial member in sequence; and an isolation member disposed between the first fin and the second fin. An isolation feature extends continuously from the first gate spacer layer to the second gate spacer layer and separates the first contact feature from the second contact feature.

Description

TECHNICAL FIELD

[0001] The utility model relates to semiconductor device and its formation method, especially relate to double silicide structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. A steady progress in the materials, design, and manufacturing of the integrated circuits has resulted in generations of integrated circuits having smaller and more complex circuitry. In the pursuit of smaller and more complex circuitry, periodic increases in performance and complexity have been facilitated by advances in semiconductor technology, which have provided smaller features and greater functionality. In addition, the complexity of such manufacturing processes has increased because of the need to form a larger number of interconnects, while at the same time, the dimensions of the interconnects themselves have become smaller.

[0003] To implement these evolutions, similar developments in the integrated circuit fabrication process are required. For example, silicide structures are used to reduce contact resistance between source / drain epitaxial components and source / drain contacts in semiconductor devices. Generally, the same silicide structure is used in both N-type transistors and P-type transistors. However, such an approach is challenging for improving device performance in modern technology nodes. Differences between N-type transistors and P-type transistors require individual optimization. Thus, while existing silicide structures are generally adequate for their intended purposes, they are not entirely satisfactory in every respect. SUMMARY

[0004] The utility model discloses a semiconductor device to solve at least one of the above problems.

[0005] A semiconductor device includes: a first fin protruding from a substrate, the first fin extending in a first direction; a second fin protruding from the substrate, the second fin extending in the first direction; a first gate stack on the first fin and the second fin, the first gate stack extending in a second direction perpendicular to the first direction; a second gate stack on the first fin and the second fin, the second gate stack extending in the second direction; a first gate spacer layer disposed on sidewalls of the first gate stack; a second gate spacer layer disposed on sidewalls of the second gate stack; a first epitaxial component on the first fin and sandwiched between the first gate stack and the second gate stack; a first silicide layer on the first epitaxial component, the first silicide layer comprising a first type of work function metal; a first contact component on the first silicide layer; a second epitaxial component on the second fin and sandwiched between the first gate stack and the second gate stack; a second silicide layer on the second epitaxial component, the second silicide layer comprising a second type of work function metal different from the first type of work function metal; a second contact component on the second silicide layer; and an isolation component disposed between the first fin and the second fin. In a top view of the semiconductor device, the isolation component continuously extends from the first gate spacer layer to the second gate spacer layer along the first direction. In a cross-sectional view of the semiconductor device perpendicular to the first direction, the isolation component separates the first contact component from the second contact component.

[0006] According to one of the embodiments of the present application, a top surface of the first silicide layer is below a top surface of the second silicide layer.

[0007] According to one of the embodiments of the present application, the first contact component directly contacts the first gate spacer layer, and the second contact component directly contacts the second gate spacer layer.

[0008] According to one of the embodiments of the present application, further comprising: an isolation structure disposed on sidewalls of the first fin and the second fin, wherein the first contact component and the second contact component directly contact the isolation structure.

[0009] According to one of the embodiments of the present application, further comprising: an etch stop layer disposed between the isolation component and the isolation structure.

[0010] According to one of the embodiments of the present application, the isolation component has an inclined sidewall.

[0011] According to one of the embodiments of the present application, a top surface of the first epitaxial component is lower than a top surface of the second epitaxial component.

[0012] According to one of the embodiments of the present application, each of the first gate stack and the second gate stack further comprises: a gate dielectric layer; and a gate electrode layer on the gate dielectric layer.

[0013] According to one of the embodiments of the present application, further comprising: a dielectric layer covering the first epitaxial component and the second epitaxial component, wherein the first contact component and the second contact component are disposed through the dielectric layer to contact the first silicide layer and the second silicide layer, respectively.

[0014] According to one of the embodiments of the present application, the first contact component is separated from the dielectric layer by a dielectric liner, and the second contact component is separated from the dielectric layer by the dielectric liner. BRIEF DESCRIPTION OF DRAWINGS

[0015] The following detailed description of the embodiments of the present application will be made with reference to the accompanying drawings. It should be noted that various features are not drawn to scale, but are merely intended for illustrative purposes. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present application.

[0016] Figure 1 is a flowchart showing a method of forming a semiconductor device according to one or more aspects of the present application.

[0017] Figure 2 is a perspective view showing a workpiece during fabrication of a method according to one or more aspects of the present application. Figure 1 is a perspective view showing a workpiece during fabrication of a method according to one or more aspects of the present application.

[0018] Figures 3-27 is a perspective view showing a workpiece during fabrication of a method according to one or more aspects of the present application. Figure 1 is a perspective view showing a workpiece during fabrication of a method according to one or more aspects of the present application.

[0019] Figure 28 is a flowchart showing another method of forming a semiconductor device according to one or more aspects of the present application.

[0020] Figures 29-46 is a perspective view showing a workpiece during fabrication of another method according to one or more aspects of the present application. Figure 28 is a perspective view showing a workpiece during fabrication of another method according to one or more aspects of the present application.

[0021] The reference signs are as follows:

[0022] 100: method

[0023] 100': method

[0024] 102: block

[0025] 104: block

[0026] 106: block

[0027] 107: block

[0028] 108: block

[0029] 109: block

[0030] 110: block

[0031] 112: block

[0032] 113: block

[0033] 114: block

[0034] 116: block

[0035] 118: block

[0036] 120: block

[0037] 122: block

[0038] 124: block

[0039] 125: block

[0040] 126: block

[0041] 128: block

[0042] 130: block

[0043] 132: block

[0044] 134: block

[0045] 136: block

[0046] 138: block

[0047] 200: workpiece

[0048] 202: substrate

[0049] 202N: N-type element region

[0050] 202P: P-type element region

[0051] 204: dashed line

[0052] 206: active region

[0053] 208: isolation structure

[0054] 210: dummy gate stack

[0055] 216: dummy dielectric layer

[0056] 218: dummy electrode layer

[0057] 220: gate spacer layer

[0058] 230: source / drain feature

[0059] 230N: N-type source / drain feature

[0060] 230P: P-type source / drain feature

[0061] 232: contact etch stop layer

[0062] 234: interlayer dielectric layer

[0063] 240: metal gate stack

[0064] 242: gate dielectric layer

[0065] 246: gate electrode layer

[0066] 248: nanosheet

[0067] 250: inner spacer

[0068] 252: patterned mask

[0069] 254: opening

[0070] 255: dielectric liner

[0071] 256: isolation feature

[0072] 257: trench

[0073] 258: patterned photoresist layer

[0074] 260N: metal layer

[0075] 260P: metal layer

[0076] 262: dashed line

[0077] 264: patterned photoresist layer

[0078] 266: island

[0079] 270N: silicide layer

[0080] 270P: silicide layer

[0081] 278: source / drain contact

[0082] 300: implantation process

[0083] 310: cleaning process

[0084] 320: implantation process

[0085] 330: cleaning process

[0086] A-A: line segment

[0087] B-B: line segment

[0088] C-C: line segment DETAILED DESCRIPTION

[0089] The following disclosure provides many different embodiments, or examples, for implementing different components of the provided technology. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present technology. For example, the making of first and second parts mentioned in the description can include embodiments where the first and second parts are formed in direct contact with each other, or where additional parts are formed between the first and second parts such that the first and second parts are not in direct contact. Further, the present technology can be repeated with reference to a single reference numeral and / or letter in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to impose relationships between the various embodiments and / or configurations discussed.

[0090] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component, or portion as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0091] Further, when a number or a range of numbers is used to describe a quantity, such as a dimension, a thickness, a length, a width, a size, a value, or the like, unless otherwise specified, the quantity is intended to encompass a reasonable range of values around the stated value, in keeping with manufacturing variations and tolerances that are known to those of skill in the art. For example, based on known manufacturing tolerances for components having a dimension related to the stated value, a number or a range of numbers can encompass a reasonable range of values around the stated value, such as within ±10% of the stated value. For example, if a layer of material having a thickness of "about 5 nanometers" is known to those of skill in the art to have a manufacturing tolerance of ±15%, then a layer of material having a thickness of 4.25 nanometers to 5.75 nanometers can be encompassed.

[0092] The present application relates generally to integrated circuits and semiconductor devices and methods of forming the same. More particularly, the present application relates to integrated circuits and semiconductor devices having a dual silicide structure. In integrated circuits and semiconductor devices, a silicide structure is used to reduce contact resistance between a contact component developed in a source / drain region (also referred to as a source / drain epitaxial component or a source / drain component) and an epitaxial component. The source / drain region can individually or collectively represent a source or a drain, depending on the context.

[0093] In a typical fabrication flow, the same silicide structure can be used in both N-type transistors and P-type transistors. However, since the source / drain components in the N-type transistors and the P-type transistors are implanted with different dopants, such a difference ensures that one silicide structure is developed for the N-type transistors, and another different silicide structure is developed for the P-type transistors, which is referred to as a dual silicide structure. The dual silicide structure allows the silicide structure for the N-type transistors and the silicide structure for the P-type transistors to be optimized separately, to further enhance transistor performance. For example, different work function metals (such as a P-type work function metal and an N-type work function metal) can be used for the P-type transistors and the N-type transistors, respectively. These work function metals interact with the individual materials of the source / drain components to form silicide components with different compositions for different types of transistors. In this way, the Schottky barrier height is reduced, and the contact resistance is correspondingly reduced.

[0094] According to some embodiments, details of structures and fabrication methods of the present application are described below with reference to the accompanying drawings, which show a fabrication of a multiple gate device. As integrated circuit technology evolves to smaller technology nodes, multiple gate metal-oxide semiconductor field effect transistors (MOSFETs) (or multiple gate devices) are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Multiple gate devices generally represent devices having gate structures or portions thereof disposed on more than one side of a channel region. Fin field effect transistors (finFETs) and multi-bridge channel (MBC) transistors are examples of multiple gate devices that are popular and promising choices for high performance and low leakage current applications. Fin field effect transistors have a raised channel that is wrapped on more than one side by a gate (e.g., a gate wraps around the top and sidewalls of a "fin" of semiconductor material that extends from a base). Multi-bridge channel transistors have gate structures that can extend partially or completely around a channel region to provide connections to the channel region on two or more sides. Because of the gate structure around the channel region, multi-bridge channel transistors can also be referred to as surrounding gate transistors (SGTs) or gate all around (GAA) transistors. It should be understood that although some embodiments of the present application illustrate forming fin field effect transistors as examples of multiple gate transistors, these examples are provided for illustrative purposes only, and one of skill in the art will recognize that the present application contemplates forming multi-bridge channel transistors (e.g., surrounding gate transistors or gate all around transistors) as well.

[0095] Various aspects of the present application will be described in detail with reference to the accompanying drawings. Figure 1 is a flowchart illustrating a method 100 of forming a semiconductor device from a workpiece according to embodiments of the present application. The method 100 is merely an example and is not intended to limit embodiments of the present application to what is described in method 100 explicitly. Additional steps can be provided before, during, or after method 100, and some steps of method 100 could be replaced, eliminated, or moved to a different position. For the sake of clarity, not every step of method 100 is described in detail. Method 100 will be described in conjunction with Figures 2-27 described in detail below, Figures 2-27 is a flowchart illustrating a method 100 of forming a semiconductor device from a workpiece according to embodiments of the present application. The method 100 is merely an example and is not intended to limit embodiments of the present application to what is described in method 100 explicitly. Additional steps can be provided before, during, or after method 100, and some steps of method 100 could be replaced, eliminated, or moved to a different position. For the sake of clarity, not every step of method 100 is described in detail. Method 100 will be described in conjunction with Figure 1The embodiments of method 100 are shown in perspective or cross-sectional views of workpiece 200 at different manufacturing stages. Since workpiece 200 will be manufactured into a semiconductor device, it may be referred to as a semiconductor device for the purposes of this text. The X, Y, and Z directions in the figures are perpendicular to each other. Throughout this invention, identical components may be designated by the same symbols unless otherwise specified.

[0096] Reference Figure 1 and Figures 2-4 Method 100 includes block 102, wherein a workpiece 200 is received (or provided). Figure 2 A perspective view of one embodiment of the workpiece 200. Figure 3 For along Figure 2 A cross-sectional diagram of line segment BB, and Figure 4 For along Figure 2 A cross-sectional view of line segment AA. In particular, line segment AA cuts into the source / drain region of the transistor of the working part 200, while line segment BB cuts into the channel region of the transistor of the working part 200 along its length.

[0097] The workpiece 200 includes a substrate 202. The substrate 202 can include elemental (single element) semiconductors such as silicon (Si), germanium (Ge), and / or other suitable materials; compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and / or other suitable materials; alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and / or other suitable materials. The substrate 202 can be a single layer of material having a uniform composition. Alternatively, the substrate 202 can include multiple layers of material having similar or different compositions suitable for integrated circuit device fabrication. In one example, the substrate 202 can be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 202 can include a conductive layer, a semiconductor layer, a dielectric layer, other film layers, or combinations thereof. In one example, the substrate 202 is a silicon substrate such as a silicon wafer.

[0098] The substrate 202 can include various doping configurations, depending on known design requirements. In embodiments where the semiconductor device is P-type, an N-type doping profile (e.g., an N-type well) can be formed on the substrate 202. In some embodiments, the N-type dopant forming the N-type well can include phosphor (P) or arsenic (As). In embodiments where the semiconductor device is N-type, a P-type doping profile (e.g., a P-type well) can be formed on the substrate 202. In some embodiments, the P-type dopant forming the P-type well can include boron (B) or gallium (Ga). Suitable doping can include ion implantation and / or diffusion processes of the dopant. In the illustrated embodiment, the substrate 202 includes a P-type device region 202P (in which P-type devices, such as P-type transistors, are formed) and an N-type device region 202N (in which N-type devices, such as N-type transistors, are formed). The dashed line 204 represents a boundary in the substrate 202 between the P-type device region 202P and the N-type device region 202N (e.g., a boundary in the substrate 202 between the N-type well and the P-type well).

[0099] The P-type device region 202P and the N-type device region 202N each include a three-dimensional active region 206 on the substrate 202. The active region 206 is an elongated fin-like structure that protrudes upward (e.g., along the Z-direction) out of the substrate 202. As such, the active region 206 can hereafter be interchangeably referred to as a fin active region, a fin, or a fin-like structure. In some embodiments, the fin is formed from patterning the substrate 202. The fin can be patterned from the substrate 202 using a lithography process and an etching process. The lithography process can include photoresist coating (e.g., spin-on coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinse, bake-out (e.g., spin dry and / or hard bake), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. The etching process forms a trench that defines the fin. In some embodiments, a double patterning or multiple patterning process can be used to define the fin-like structure, which has, for example, a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a layer of material is formed over the substrate and is patterned using a lithography process. Spacers are formed next to the patterned layer of material using a self-alignment process. The layer of material is then removed, and the remaining spacers or mandrels can then be used as a mask and the fin is patterned by etching the top portion of the substrate 202.

[0100] The workpiece 200 further includes isolation structures 208 on the substrate 202. The isolation structures 208 electrically isolate various components (e.g., fins) of the workpiece 200. The isolation structures 208 can include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable isolation materials (e.g., including silicon, oxygen (O), nitrogen (N), carbon (C), or other suitable isolation constituents), or combinations thereof. The isolation structures 208 can include different components, such as shallow trench isolation (STI) components and / or deep trench isolation (DTI) components. In one embodiment, the isolation structures 208 can be formed by filling trenches between fins with an insulating material (e.g., by using a chemical vapor deposition (CVD) process or a spin-on glass process), performing a chemical mechanical polish (CMP) process to remove excess insulating material and / or to planarize a top surface of the insulating material layer, and etching back the insulating material layer to form the isolation structures 208. In some embodiments, the isolation structures 208 can include multiple dielectric film layers, such as a silicon nitride layer disposed on a thermal oxide liner.

[0101] The workpiece 200 also includes forming dummy gate stacks 210 on the channel regions of the fins. In some embodiments, a gate replacement process (or gate-last process) is employed in which the dummy gate stacks 210 serve as placeholders to undergo various processes and will be removed and replaced with functional metal gate structures. Other processes and configurations are possible. In some embodiments, the dummy gate stacks 210 are formed on the fins, and the fins can be divided into channel regions that are under the dummy gate stacks 210 and source / drain regions that are not under the dummy gate stacks 210. The channel regions are adjacent to the source / drain regions. In the illustrated embodiment, the fins are oriented along a length in the X-direction, the dummy gate stacks 210 are oriented along a length in the Y-direction, and each channel region is disposed between two source / drain regions along the X-direction.

[0102] The dummy gate stack 210 can include a dummy dielectric layer 216 and a dummy electrode layer 218. In some embodiments, the dummy dielectric layer 216 can be formed on the fin using a chemical vapor deposition process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or other suitable process. In some cases, the dummy dielectric layer 216 can include silicon oxide. Thereafter, the dummy electrode layer 218 can be deposited on the dummy dielectric layer 216 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable process. In some cases, the dummy electrode layer 218 can include polysilicon. The dummy electrode layer 218 and the dummy dielectric layer 216 can then be patterned to form the dummy gate stack 210. For example, the patterning process can include a photolithography process (e.g., photolithography or e-beam lithography), which can further include photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, drying (e.g., spin drying and / or hard bake), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods.

[0103] The workpiece 200 also includes depositing a gate spacer layer 220 on the dummy gate stack 210. In some embodiments, the gate spacer layer 220 is conformally deposited on the workpiece 200, including on the top surface and sidewalls of the dummy gate stack 210. The term "conformally" can be used herein to facilitate description of a film layer having substantially uniform thickness across various regions. The gate spacer layer 220 can be a single layer or multiple layers. At least one of the layers of the gate spacer layer 220 can include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon nitride. The gate spacer layer 220 can be deposited on the dummy gate stack 210 using a process such as a chemical vapor deposition process, a sub-atmospheric chemical vapor deposition (SACVD) process, an atomic layer deposition process, or other suitable process. In one embodiment, the gate spacer layer 220 includes a first layer and a second layer disposed on the first layer. The first layer can include silicon oxynitride, and the second layer can include silicon nitride.

[0104] The P-type element region 202P and the N-type element region 202N also each include source / drain features 230 formed on the fin. For example, the P-type element region 202P includes P-type source / drain features 230P on both sides of the dummy gate stack 210, such as in or on source / drain recesses, and the N-type element region 202N includes N-type source / drain features 230N on both sides of the dummy gate stack 210, such as in or on source / drain recesses. The source / drain recesses can be formed by recessing the source / drain regions of the fin. In some embodiments, the source / drain regions not covered by the dummy gate stack 210 and the gate spacer layer 220 are etched by a dry etch or suitable etching process to form the source / drain recesses. In the illustrated embodiment, the fin is recessed in the source / drain regions below the top surface of the isolation structure 208. In some embodiments, the source / drain features 230 can include epitaxial layers grown epitaxially on the fin. In some embodiments, the source / drain features 230 each include a semiconductor material. For example, the P-type source / drain features 230P can include silicon germanium, and the N-type source / drain features 230N can include silicon and / or silicon carbide. In some embodiments, the P-type source / drain features 230P can include germanium at a concentration equal to or less than 50% atomic percent. In some embodiments, the P-type source / drain features 230P can include germanium at a concentration equal to or less than 40% atomic percent.

[0105] Referring to Figure 1 , Figure 5 , and Figure 6The method 100 includes block 104, in which a contact etch stop layer (CESL) 232 and an interlayer dielectric (ILD) layer 234 are formed on the workpiece 200. The contact etch stop layer 232 is formed prior to the formation of the interlayer dielectric layer 234. The contact etch stop layer 232 is interposed between the isolation structure 208 and the interlayer dielectric layer 234. The contact etch stop layer 232 comprises a different material than the interlayer dielectric layer 234, and protects the components below the contact etch stop layer 232 during subsequent etching operations. In some examples, the contact etch stop layer 232 comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and / or other known materials. The contact etch stop layer 232 can be conformally deposited by atomic layer deposition, plasma enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition processes. The interlayer dielectric layer 234 is then deposited on the contact etch stop layer 232. In some embodiments, the interlayer dielectric layer 234 comprises tetraethyl ortho silicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). The interlayer dielectric layer 234 can be deposited by a plasma enhanced chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after the interlayer dielectric layer 234 is formed, the workpiece 200 can be annealed to improve the integrity of the interlayer dielectric layer 234. As shown in FIG. 2C, the contact etch stop layer 232 is directly conformally disposed on the top and sidewall surfaces of the N-type source / drain components 230N and the P-type source / drain components 230P. Figure 6

[0106] After the contact etch stop layer 232 and the interlayer dielectric layer 234 are deposited, the workpiece 200 can be planarized by a planarization process to expose the dummy gate stack 210, as shown in FIG. 2D. For example, the planarization process can comprise a chemical mechanical polishing process. Exposing the dummy gate stack 210 allows for the removal of the dummy gate stack 210, and the deposition of a functional metal gate stack. Figure 5

[0107] Referring to​​Figure 1 and Figure 7 Method 100 includes block 106, in which dummy gate stack 210 is removed and replaced by metal gate stack 240. In some embodiments, removing dummy gate stack 210 results in a gate trench over the channel region. Removing dummy gate stack 210 can include one or more etch processes selective to the materials of dummy gate stack 210. For example, the removal of dummy gate stack 210 can be performed using a selective wet etch, a selective dry etch, or a combination thereof, which is selective to dummy gate stack 210. Method 100 can include further operations of forming metal gate stack 240 within the gate trench.

[0108] Metal gate stack 240 includes a gate dielectric layer 242, and a gate electrode layer 246 over gate dielectric layer 242. In some embodiments, although not explicitly shown in the figures, gate dielectric layer 242 includes an interface layer and a high-k gate dielectric layer. High-k dielectric materials, as used and described herein, include dielectric materials having a high dielectric constant, e.g., greater than the dielectric constant of thermal silicon oxide (~3.9). The interface layer can include a dielectric material, such as silicon oxide, hafnium silicate (HfSiO), or silicon oxynitride. The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The high-k gate dielectric layer can include hafnium oxide. Alternatively, the high-k gate dielectric layer can include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO x), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide, yttrium oxide (Y2O3), strontium titanate (STO), SrTiO3, barium titanate (BTO), BaTiO3, barium zirconate (BZO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate (BST), (Ba,Sr)TiO3, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. The high-k gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0109] The gate electrode layer 246 of the metal gate stack 240 may include a single layer or alternatively a multilayer structure, such as various combinations of metal layers with selected work functions to improve device performance (work function metal layers), a liner, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. For example, the gate electrode layer 246 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer 246 may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical planarization process may be performed to remove excess metal, thereby providing a substantially flat top surface for the metal gate stack 240. Upon completion of the operation of block 106, P-type transistors in the P-type device region 202P and N-type transistors in the N-type device region 202N are substantially formed.

[0110] In some embodiments, such as Figure 8 As shown, the working component 200 includes a fully wound gate transistor. Figure 7 and Figure 8 Most of the features are the same or similar, and the same parts are labeled with the same reference numerals in the accompanying drawings. (Refer to...) Figure 8In this embodiment, the workpiece 200 further includes multiple nanosheets 248 (or nanowire-like, pillar-like, strip-like, or other suitable shapes) of a semiconductor material (e.g., silicon) that are vertically stacked (along the Z direction) on the substrate 202 and horizontally connected to the source / drain features 230. The nanosheets 248 are channel layers of the transistors and can be considered as part of the fins. The partial metal gate stacks 240 surround each channel layer. The workpiece 200 further includes inner spacers 250 that are horizontally between the source / drain features 230 and the portions of the metal gate stacks 240 and vertically between the channel layers. The inner spacers 250 can include metal oxide, silicon oxide, silicon oxycarbide, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide can include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide. Although not explicitly shown, the inner spacers 250 can be single-layered or multi-layered.

[0111] Referring to Figure 1 , Figure 9 , and Figure 10Method 100 includes block 108, in which a patterned mask 252 is formed over the interlayer dielectric layer 234, and subsequently the interlayer dielectric layer 234 is etched through openings 254 defined in the patterned mask 252. The patterned mask 252 can be a patterned hard mask formed by photolithography. For example, the patterning process can include a photolithography process (e.g., photolithography or e-beam lithography), which can further include photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinse, bake-out (e.g., spin dry and / or hard bake), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the patterned mask 252 includes silicon oxide or silicon nitride. In some other embodiments, the patterned mask 252 is a patterned photoresist layer. The patterned mask 252 includes openings 254. The openings 254 can be located between the P-type device region 202P and the N-type device region 202N. In the illustrated embodiment, the dashed line 204 is directly below the openings 254. Subsequently, an etching process is performed with the patterned mask 252 as an etching mask. The etching process etches the interlayer dielectric layer 234 through the openings 254 defined in the patterned mask 252. The contact etch stop layer 232 acts as an etch stop layer. The etching process extends the openings 254 downward to form trenches until the contact etch stop layer 232 is exposed. The trenches are also numbered 254. To ensure that the interlayer dielectric layer 234 is divided into two halves, the etching process can over-etch the contact etch stop layer 232 such that the top surface of the contact etch stop layer 232 is recessed and the trenches partially extend into the contact etch stop layer 232. The trenches have a larger width at the top and a smaller width at the bottom, thus having sloped sidewalls.

[0112] Referring to Figure 1 and Figure 11 Method 100 includes block 110, in which an isolation component 256 is formed in the trenches 254. The isolation component 256 can include silicon, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, or other suitable materials. In one embodiment, the isolation component 256 can be formed by filling the trenches 254 between the interlayer dielectric layer 234 with an insulating material (e.g., using a chemical vapor deposition process or a spin-on glass process). After the insulating material is deposited, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove excess insulating material. The patterned mask 252 can also be removed by the planarization process. The isolation component 256 follows the shape of the trenches 254, which have a larger width at the top and a smaller width at the bottom. The bottom of the isolation component 256 can be partially embedded in the contact etch stop layer 232. In the illustrated embodiment, the isolation component 256 is located directly above the dashed line 204.

[0113] Referring to Figure 1 and Figure 12The method 100 includes block 112, in which the interlayer dielectric layer 234 is removed in an etching process. The removal of the interlayer dielectric layer 234 creates two trenches 257 separated by the isolation feature 256. In some embodiments, an isotropic etch is performed to remove the interlayer dielectric layer 234. The isotropic etch is more effective to remove portions of the interlayer dielectric layer 234 under the sloped sidewalls of the isolation feature 256, as well as under the facet sidewall surfaces of the source / drain feature 230. The isotropic etch can be a dry etch, in which the etching gas can be selected from carbontetrafluoride (CF4), chlorine (CI2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and combinations thereof. Then, in alternative embodiments, a wet etch is performed to remove the interlayer dielectric layer 234. For example, the wet etch can be performed using tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) solution, or other similar chemicals. In some example embodiments, the concentration of the tetramethylammonium hydroxide solution is in a range between about 1% and about 30%. After the isotropic etch, the contact etch stop layer 232 is exposed.

[0114] Referring to Figure 1 and Figure 13At block 114, a patterned photoresist layer 258 is formed to cover and protect the N-type device region 202N and to remove the contact etch stop layer 232 from the P-type device region 202P. The P-type device region 202P is exposed in the openings of the patterned photoresist layer 258. The patterned photoresist layer 258 can be formed by a photolithography process. An exemplary photolithography process can include the process steps of photoresist coating, soft bake, mask alignment, exposure, post-exposure bake, photoresist development, and hard bake. The photolithography exposure process can also be implemented or replaced by other suitable techniques, such as maskless lithography, e-beam writing, ion beam writing, or molecular imprinting. In some embodiments, the patterned photoresist layer 258 is a bottom antireflective coating (BARC) layer. Subsequently, an etching process is performed to remove the contact etch stop layer 232 from the P-type device region 202P. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. The etching process is selective to the dielectric material of the contact etch stop layer 232, while the isolation component 256, the isolation structure 208, and the P-type source / drain component 230P are substantially maintained intact. The removal of the contact etch stop layer 232 from the P-type device region 202P exposes the P-type source / drain component 230P.

[0115] Referring to Figure 1 and Figure 14 At block 116, a P-type dopant is implanted into the P-type source / drain component 230P in an implantation process 300. The patterned photoresist layer 258 acts as an implantation mask to substantially prevent the P-type dopant from being implanted into the N-type device region 202N. The P-type dopant can be boron, boron fluoride (BF2), indium (In), germanium, or a combination thereof. In some embodiments, the P-type source / drain component 230P can be doped in situ with the P-type dopant during an epitaxy process, and then the implantation process 300 can be skipped. If the P-type source / drain component 230P is not doped in situ, the implantation process 300 (e.g., an ion implantation process) is performed to dope the P-type source / drain component 230P with the appropriate P-type dopant. In some embodiments, the P-type source / drain component 230P can have a P-type dopant concentration of about 10 19 cm -3 and about 10 21 cm -3dopant implantation. In an exemplary embodiment, the P-type source / drain features 230P after the P-type dopant implantation include silicon germanium boron (SiGeB). After the implantation process 300, the patterned photoresist layer 258 can be removed in a suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques.

[0116] Referring to Figure 1 and Figure 15 Method 100 includes block 118, in which a cleaning process 310 is performed. Cleaning process 310 can include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning can include using standard clean 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2)), standard clean 2 (RCA SC-2, a mixture of DI water, hydrochloric acid (HC1), and hydrogen peroxide), sulfuric acid-hydrogen peroxide mixture (SPM), and / or hydrofluoric acid (HF) for oxide removal. Dry cleaning processes can include helium (He) and hydrogen gas treatment at temperatures between about 250 °C and about 550 °C, and pressures between about 75 mTorr and about 155 mTorr. Hydrogen gas treatment can convert silicon on the surface to silane (SiH4), which can be pumped out for removal. Cleaning process 310 can remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of silicide structures in subsequent processes.

[0117] Referring to Figure 1 and Figure 16The method 100 includes block 120, in which a metal layer 260P is formed on the P-type element region 202P and on the N-type element region 202N. The metal layer 260P directly contacts the P-type source / drain feature 230P and directly contacts the contact etch stop layer 232 on the N-type source / drain feature 230N. In other words, the metal layer 260P does not directly contact (or interface with) the N-type source / drain feature 230N. In some embodiments, the metal layer 260P includes a P-type work function metal. The metal layer 260P can also be referred to as a P-type work function metal layer. A P-type work function metal is a metal that has a work function value (e.g., the energy by which a metal removes an electron) that is greater than (or more positive than) the Fermi level of a semiconductor. In some embodiments, the metal layer 260P includes nickel, platinum, palladium (Pd), vanadium (V), ruthenium, tantalum (Ta), titanium nitride, titanium silicon nitride (TiSiN), tantalum nitride, tungsten carbonitride (WCN), tungsten nitride (WN), molybdenum (Mo), other suitable metals, or combinations thereof. In an exemplary embodiment, the metal layer 260P includes nickel platinum (NiPt). The metal layer 260P can include multiple film layers, and can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. In some embodiments, the metal layer 260P is a conformal film layer on the workpiece 200. That is, although not shown in FIG. 1, the metal layer 260P can also be deposited on the top surface and sidewall surfaces of the isolation feature 256. In some embodiments, the metal layer 260P has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuities can cause the subsequently formed silicide layer to be non-uniform, thereby reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied that could be used by other important features of the transistor. Figure 16 The metal layer 260P can also be deposited on the top surface and sidewall surfaces of the isolation feature 256. In some embodiments, the metal layer 260P has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuities can cause the subsequently formed silicide layer to be non-uniform, thereby reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied that could be used by other important features of the transistor.

[0118] Referring to FIG. 2, the method 100 includes block 130, in which a metal layer 260N is formed on the N-type element region 202N. The metal layer 260N directly contacts the N-type source / drain feature 230N and directly contacts the contact etch stop layer 232 on the P-type source / drain feature 230P. In other words, the metal layer 260N does not directly contact (or interface with) the P-type source / drain feature 230P. In some embodiments, the metal layer 260N includes an N-type work function metal. The metal layer 260N can also be referred to as an N-type work function metal layer. An N-type work function metal is a metal that has a work function value (e.g., the energy by which a metal removes an electron) that is less than (or more negative than) the Fermi level of a semiconductor. In some embodiments, the metal layer 260N includes aluminum, aluminum-copper (AlCu), aluminum-silicon (AlSi), aluminum-copper-silicon (AlCuSi), titanium, titanium nitride, tantalum nitride, tungsten nitride, molybdenum, other suitable metals, or combinations thereof. In an exemplary embodiment, the metal layer 260N includes aluminum copper (AlCu). The metal layer 260N can include multiple film layers, and can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. In some embodiments, the metal layer 260N is a conformal film layer on the workpiece 200. That is, although not shown in FIG. 2, the metal layer 260N can also be deposited on the top surface and sidewall surfaces of the isolation feature 256. In some embodiments, the metal layer 260N has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuities can cause the subsequently formed silicide layer to be non-uniform, thereby reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied that could be used by other important features of the transistor. Figure 1 and Figure 17In some embodiments, the method 100 includes a block 122 in which the workpiece 200 is subjected to a thermal treatment, such as an anneal. In some embodiments, the thermal treatment includes annealing the workpiece 200 at a temperature of about 300 °C to about 600 °C. In some embodiments, the composition of the ambient gas, the composition of the purge gas, the flow rate of the ambient gas, the flow rate of the purge gas, the pressure of the gas in the chamber, the temperature ramp rate, the temperature hold time, and the temperature range can be adjusted in order to promote the chemical reaction that forms the silicide layer on the P-type source / drain feature 230P. Thus, the thermal treatment initiates a chemical reaction between the P-type source / drain feature 230P and the metal layer 260P. For example, the P-type work function metal of the metal layer 260P reacts with the semiconductor atoms in the P-type source / drain feature 230P to form the silicide layer 270P. In an exemplary embodiment, the metal layer 260P includes nickel platinum, and the nickel platinum diffuses into the outer layer of the P-type source / drain feature 230P to react with the silicon in the P-type source / drain feature 230P. The reaction between the nickel platinum and the silicon creates a film layer of nickel platinum silicide (NiPtSi) as the silicide layer 270P. As a result, the thickness of the P-type source / drain feature 230P (e.g., along the Z direction) is reduced compared to before the thermal treatment. The dashed line 262 represents the profile of the P-type source / drain feature 230P before the thermal treatment, showing that the outer layer of the P-type source / drain feature 230P is converted into a portion of the silicide layer 270P. In some embodiments, the top surface of the P-type source / drain feature 230P is flush with the top surface of the N-type source / drain feature 230N before the thermal treatment, and the top surface of the P-type source / drain feature 230P is lower than the top surface of the N-type source / drain feature 230N after the thermal treatment.

[0119] In some embodiments, the silicide layer 270P includes nickel silicide (NiSi), nickel platinum silicide, other silicide materials, or combinations thereof. In some embodiments, the silicide layer 270P has a thickness of about 5 nm to about 10 nm. If the silicide layer is too thin (e.g., less than 5 nm), the silicide layer can have limited efficacy in reducing contact resistance. Furthermore, the silicide can become non-uniform when thermal agglomeration and islanding occur. If the silicide layer is too thick (e.g., greater than 10 nm), a large portion of the source / drain material is consumed, and issues such as speed reduction and leakage current can occur. After the thermal treatment, the portion of the metal layer 260P that is in direct contact with the P-type source / drain feature 230P is consumed and converted into the silicide layer 270P, while the other portions of the metal layer 260P that are in direct contact with the dielectric surfaces of the isolation structure 208 and the contact etch stop layer 232 do not participate in the chemical reaction. Thus, the difference in material composition between the silicide layer 270P and the remaining portions of the metal layer 260P allows the remaining portions of the metal layer 260P to be removed in subsequent processes.

[0120] Referring Figure 1 and Figure 18 , the method 100 includes block 124, in which an etching process is performed to remove the remaining portion of the metal layer 260P from both the P-type device region 202P and the N-type device region 202N. The etching process is configured to remove the metal layer 260P without substantially etching the silicide layer 270P. In other words, this etching process is a selective etching process. As described above, this result is achieved because of the different material composition between the silicide layer 270P and the metal layer 260P. Any suitable etching method can be performed, such as a wet etching method. Moreover, any suitable etching chemistry can be used. In some embodiments, the etch rate of the metal layer 260P in the etching chemistry is at least 10 times greater than the etch rate of the silicide layer 270P in the same etching chemistry. As a result, the silicide layer 270P is only minimally affected by the etching process. The result of the etching process is that the contact etch stop layer 232 is exposed in the N-type device region 202N, while the top surface of the P-type source / drain feature 230P remains covered under the silicide layer 270P. Further, the silicide layer 270P is exposed in the P-type device region 202P.

[0121] Referring Figure 1 and Figure 19 , the method 100 includes block 126, in which a patterned photoresist layer 264 is formed to cover and protect the P-type device region 202P, and the contact etch stop layer 232 is removed from the N-type device region 202N. The N-type device region 202N is exposed in the openings of the patterned photoresist layer 264. The patterned photoresist layer 264 can be formed by a photolithography process. An exemplary photolithography process can include the process steps of photoresist coating, soft bake, mask alignment, exposure, post-exposure bake, photoresist development, and hard bake. The photolithography exposure process can also be performed or replaced by other suitable techniques, such as maskless lithography, e-beam writing, ion beam writing, or molecular imprinting. In some embodiments, the patterned photoresist layer 264 is a bottom anti-reflective coating. Subsequently, an etching process is performed to remove the contact etch stop layer 232 from the N-type device region 202N. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. The etching process is selective to the dielectric material of the contact etch stop layer 232, while the isolation feature 256, the isolation structure 208, and the N-type source / drain feature 230N remain substantially intact. The removal of the contact etch stop layer 232 from the N-type device region 202N exposes the N-type source / drain feature 230N. Further, the isolation feature 256 can protect a small portion of the contact etch stop layer 232 directly underneath from being removed.

[0122] Referring Figure 1 and Figure 20, method 100 includes block 128, in which an N-type dopant is implanted into the N-type source / drain features 230N in an implantation process 320. The patterned photoresist layer 264 acts as an implantation mask to substantially prevent the N-type dopant from being implanted into the P-type element region 202P. The N-type dopant can be phosphorous, arsenic, antimony (Sb), or a combination thereof. In some embodiments, the N-type source / drain features 230N can be doped in situ with an N-type dopant during an epitaxy process, and then the implantation process 320 can be skipped. If the N-type source / drain features 230N are not doped in situ, the implantation process 320 (e.g., an ion implantation process) is performed to dope the N-type source / drain features 230N with a suitable N-type dopant. In some embodiments, the N-type source / drain features 230N can have a doping concentration between about 10 19 cm -3 and about 10 21 cm -3 In an exemplary embodiment, the N-type source / drain features 230N after the N-type dopant implantation include silicon phosphide (SiP). After the implantation process 320, the patterned photoresist layer 264 can be removed in a suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques.

[0123] Referring to Figure 1 and Figure 21 , method 100 includes block 130, in which a cleaning process 330 is performed. The cleaning process 330 can include dry cleaning, wet cleaning, or a combination thereof. In some examples, the wet cleaning can include using standard clean 1 (RCASC-1, a mixture of deionized water, ammonium hydroxide, and hydrogen peroxide), standard clean 2 (RCASC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), a sulfuric acid-hydrogen peroxide mixture, and / or hydrofluoric acid for oxide removal. The dry cleaning process can include a helium and hydrogen treatment at a temperature between about 250 °C and about 550 °C, and a pressure between about 75 mTorr and about 155 mTorr. The hydrogen treatment can convert silicon on the surface to silane, which can be pumped out for removal. The cleaning process 330 can remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of silicide structures in subsequent processes.

[0124] Referring to Figure 1 and Figure 22The method 100 includes block 132, in which a metal layer 260N is formed on the N-type element region 202N and on the P-type element region 202P. The metal layer 260N directly contacts the N-type source / drain feature 230N and directly contacts the silicide layer 270P on the P-type source / drain feature 230P. In other words, the metal layer 260N does not directly contact (or interface with) the P-type source / drain feature 230P. In some embodiments, the metal layer 260N includes an N-type work function metal. The metal layer 260N can also be referred to as an N-type work function metal layer. An N-type work function metal is a metal that has a work function value less than (or lower than) the Fermi level of the semiconductor. In some embodiments, the metal layer 260N includes titanium, aluminum, ytterbium (Yb), silver (Ag), tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese (Mn), zirconium (Zr), other suitable metals, or combinations thereof. In an exemplary embodiment, the metal layer 260N includes titanium. The metal layer 260N can include multiple film layers, and can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. In some embodiments, the metal layer 260N is a conformal film layer on the workpiece 200. That is, although not shown in the cross-sectional view, the metal layer 260N can also be deposited on the top surface and sidewall surfaces of the isolation feature 256. In some embodiments, the metal layer 260N has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuity can cause the subsequently formed silicide layer to be non-uniform, thereby reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied, which can be used by other important features of the transistor. Figure 22 The metal layer 260N can also be deposited on the top surface and sidewall surfaces of the isolation feature 256. In some embodiments, the metal layer 260N has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuity can cause the subsequently formed silicide layer to be non-uniform, thereby reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied, which can be used by other important features of the transistor.

[0125] Referring to Figure 1 and Figure 23In some embodiments, the method 100 includes a block 134, in which the workpiece 200 is subjected to a thermal treatment, such as an annealing process. In some embodiments, the thermal treatment includes annealing the workpiece 200 at a temperature of about 300 °C to about 600 °C. In some embodiments, the composition of the ambient gas, the composition of the purge gas, the flow rate of the ambient gas, the flow rate of the purge gas, the pressure of the gas in the chamber, the temperature ramp rate, the temperature hold time, and the temperature range can be adjusted in order to promote the chemical reaction to form the silicide layer on the N-type source / drain feature 230N. Thus, the thermal treatment initiates a chemical reaction between the N-type source / drain feature 230N and the metal layer 260N. For example, the N-type work function metal of the metal layer 260N reacts with the semiconductor atoms in the N-type source / drain feature 230N to form the silicide layer 270N. In exemplary embodiments, the metal layer 260N includes titanium, and silicon atoms diffuse from the N-type source / drain feature 230N into the metal layer 260N to react with the titanium of the metal layer 260N. The reaction between titanium and silicon creates a film layer of titanium silicide (TiSi) as the silicide layer 270N. As the silicon atoms diffuse upward into the metal layer 260N, the thickness of the N-type source / drain feature 230N (e.g., along the Z direction) can be substantially maintained as compared to before the thermal treatment. That is, after the thermal treatment, the top surface of the P-type source / drain feature 230P can be lower than the top surface of the N-type source / drain feature 230N, and the top surface of the silicide layer 270P can be lower than the top surface of the silicide layer 270N.

[0126] In some embodiments, the silicide layer 270N includes titanium silicide, titanium aluminum silicide (TiAlSi), other silicide materials, or combinations thereof. In some embodiments, the silicide layer 270N has a thickness of about 5 nm to about 10 nm. If the silicide layer is too thin (e.g., less than 5 nm), the silicide layer can have limited efficacy in reducing contact resistance. Furthermore, the silicide can become non-uniform when thermal agglomeration and islanding occur. If the silicide layer is too thick (e.g., greater than 10 nm), a large portion of the source / drain material is consumed, and can cause issues such as reduced speed and leakage current. After the thermal treatment, the portion of the metal layer 260N in direct contact with the N-type source / drain feature 230N is consumed and converted to the silicide layer 270N, while the other portions of the metal layer 260N in direct contact with the dielectric surface of the isolation structure 208 and the silicide surface of the silicide layer 270P do not participate in the chemical reaction. Thus, the difference in material composition between the silicide layer 270N and the remaining portion of the metal layer 260N allows the remaining portion of the metal layer 260N to be removed in subsequent processes.

[0127] Referring to Figure 1 and Figure 24Method 100 includes block 136, wherein an etching process is used to remove the remainder of metal layer 260N from both N-type element region 202N and P-type element region 202P. The etching process is configured to remove metal layer 260N without substantially etching silicide layers 270N and silicide layers 270P. In other words, this etching process is a selective etching process. As described above, this result is achieved because of the different material composition between silicide layers 270N and silicide layers 270P and metal layer 260N. Any suitable etching method can be implemented, such as a wet etching method. Moreover, any suitable etching chemicals can be used. In some embodiments, the etching rate of metal layer 260N in the etching chemical is at least 10 times greater than the etching rate of silicide layers 270N and silicide layers 270P in the same etching chemical. Therefore, silicide layers 270N and silicide layers 270P are only slightly affected by the etching process. The etching process results in the exposure of silicide layers 270N and 270P in the N-type device region 202N and P-type device region 202P, respectively. Furthermore, some residues of the metal layer 260N may remain on the top and sidewall surfaces of the silicide layer 270P. For example, in some embodiments, the metal layer 260N comprises titanium, and titanium-containing residues may remain as sporadic islands 266 on the top and sidewall surfaces of the silicide layer 270P.

[0128] Reference Figure 1 and Figures 25-27 Method 100 includes block 138, wherein source / drain contacts 278 are formed on silicide layers 270N and silicide layers 270P. Figure 26 For along Figure 25 A cross-sectional diagram of line segment BB, and Figure 27 For along Figure 25A cross-sectional schematic view of line segment C-C is shown in FIG. 2B. Specifically, line segment B-B is taken along the length of the fin in N-type element region 202N, while line segment C-C is taken along the length of the fin in P-type element region 202P. Source / drain contacts 278 are formed in the remaining space of trench 257, such that trench 257 is completely filled. Thus, the formation of source / drain contacts is a self-aligned method that uses fewer lithography steps and / or fewer hard mask layers. Source / drain contacts 278 can include a conductive barrier layer, and a metal fill layer on the conductive barrier layer. The conductive barrier layer can include titanium, tantalum, tungsten, cobalt, ruthenium, or a conductive nitride (such as titanium nitride, titanium aluminum nitride, tungsten nitride, tantalum nitride, or a combination thereof), and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or other suitable process. The metal fill layer can include tungsten, cobalt, molybdenum, ruthenium, nickel, copper, or other metal, and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or other suitable process. In some embodiments, the conductive barrier layer is omitted in source / drain contacts 278. In some embodiments, a planarization process (such as a chemical mechanical polishing process) is performed to planarize the top surface of workpiece 200 and expose metal gate stack 240. In the illustrated embodiment, contact etch stop layer 232 (except for the portion covered by isolation feature 256) can be removed by trench 257, while source / drain contacts 278 are in direct contact with gate spacer layer 220. Furthermore, as described above, the top surface of silicide layer 270N can be above the top surface of silicide layer 270P, and the top surface of N-type source / drain feature 230N can be above the top surface of P-type source / drain feature 230P. Moreover, in a top view of workpiece 200, isolation feature 256 continuously extends along the X-direction from the gate spacer layer 220 of the first metal gate stack 240 to the gate spacer layer 220 of the second metal gate stack 240. Isolation feature 256 separates source / drain contacts 278 in N-type element region 202N from source / drain contacts 278 in P-type element region 202P.

[0129] Reference will now be made to Figure 28 which is a flowchart illustrating a method 100' of forming a semiconductor device from a workpiece, according to some alternative embodiments of the present disclosure. The method 100' is merely an example, and is not intended to limit the present embodiments to what is described in the method 100'. Additional steps can be provided before, during, and after the method 100', and some steps described can be replaced, eliminated, or moved to a different location. Some aspects of the method 100' are the same as those of the method 100, and will be discussed briefly below for simplicity. Other aspects of the method 100' are different from the method 100, and will be discussed in more detail below. The method 100' will be described in conjunction with Figures 29-46are described in detail below, Figures 29-46 is according to Figure 28 FIG. 6 is a cross-sectional view of an embodiment of the method 100' of FIG. 5, showing the workpiece 200 at a different stage of fabrication.

[0130] The aspects of the operations of the blocks 102, 104, and 106 of the method 100' are substantially the same as the aspects of the operations of the blocks 102, 104, and 106 of the method 100 described above with reference to Figures 2-8 The aspects of the operations of the blocks 102, 104, and 106 of the method 100' are substantially the same as the aspects of the operations of the blocks 102, 104, and 106 of the method 100 described above with reference to

[0131] Referring to Figure 28 , Figure 29 , and Figure 30 , the method 100' includes a block 107 in which a patterned mask 252 is formed over the interlayer dielectric layer 234, and subsequently the interlayer dielectric layer 234 is etched through openings 254 defined in the patterned mask 252. The patterned mask 252 can be a patterned hard mask formed by photolithography. For example, the patterning process can include a photolithography process (e.g., photolithography or e-beam lithography), which can further include photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, drying (e.g., spin drying and / or hard bake), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the patterned mask 252 includes silicon oxide or silicon nitride. In some other embodiments, the patterned mask 252 is a patterned photoresist layer. The patterned mask 252 defines an opening 254 directly over the N-type source / drain component 230N and an opening 254 directly over the P-type source / drain component 230P. Subsequently, an etching process is performed with the patterned mask 252 as an etching mask. The etching process etches the interlayer dielectric layer 234 through the openings 254 defined in the patterned mask 252. The etching process extends the openings 254 downward to form trenches through the contact etch stop layer 232 such that the source / drain components 230 are exposed in the trenches. The trenches are also numbered 254. The etching process can over-etch the source / drain components 230 such that the top surface of each source / drain component 230 is slightly recessed and the trenches partially extend into the source / drain components 230. The trenches have a larger width at the opening and a smaller width at the bottom, thus having sloped sidewalls. Subsequently, the patterned mask 252 can be removed in a suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques.

[0132] Referring to Figure 28 and Figure 31The method 100' includes a block 109 in which a dielectric liner 255 is deposited on the workpiece 200. The dielectric liner 255 comprises a different material than the ILD layer 234 and protects the ILD layer 234 from subsequent etch operations. Thus, the dielectric liner 255 acts as an etch stop layer. In some examples, the dielectric liner 255 comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and / or other known materials. The dielectric liner 255 can be conformally deposited by atomic layer deposition, plasma- assisted chemical vapor deposition processes, and / or other suitable deposition processes. In the illustrated embodiment, the dielectric liner 255 covers the top surface of the ILD layer 234 and covers the sidewall surfaces and the bottom surface of the trench. In some embodiments, the dielectric liner 255 has a thickness of about 4 nm to about 8 nm. If the thickness is too small (e.g., less than 4 nm), the subsequent etch process can etch through the dielectric liner 255 and cause etch loss to the ILD layer 234. If the thickness is too large (e.g., greater than 8 nm), valuable space can be unnecessarily occupied that could be used by other important components of the transistor.

[0133] Referring to Figure 28 and Figure 32, method 100' includes block 113, in which a patterned photoresist layer 258 is formed covering and protecting the N-type device region 202N, and horizontal portions of the dielectric liner 255 are removed from the P-type device region 202P. The P-type device region 202P is exposed in openings of the patterned photoresist layer 258. The patterned photoresist layer 258 can be formed by a photolithography process. An exemplary photolithography process can include process steps of photoresist coating, soft bake, mask alignment, exposure, post-exposure bake, photoresist development, and hard bake. The photolithography exposure process can also be implemented or replaced by other suitable techniques, such as maskless lithography, electron beam writing, ion beam writing, or molecular imprinting. In some embodiments, the patterned photoresist layer 258 is a bottom anti-reflective coating. Subsequently, an etching process is performed to break through and remove most of the horizontal portions of the dielectric liner 255. The etching process is also referred to as a break through etching process. In some embodiments, the break through etching process can include an anisotropic dry etching process or other similar methods. In some embodiments in which the dielectric liner 255 is formed of an oxide compound, the break through etching process is a reactive ion etching process, with an etching process gas including trifluoromethane (CHF3), argon (Ar), carbon tetrafluoride (CF4), nitrogen (N2), oxygen (O2), difluoromethane (CH2F2), sulfur trifluoride (SF3), other similar gases, or a combination thereof. In the illustrated embodiment, the result of the break through etching process is that portions of the dielectric liner 255 remain on sidewalls of the trenches in the P-type device region 202P. Further, the recessed top surfaces of the P-type source / drain features 230P are exposed in the trenches.

[0134] Referring to Figure 28 and Figure 33 , method 100' includes block 116, in which a P-type dopant is implanted into the P-type source / drain features 230P in an implantation process 300. The patterned photoresist layer 258 acts as an implantation mask to substantially prevent the P-type dopant from being implanted into the N-type device region 202N. The P-type dopant can be boron, boron fluoride, indium, germanium, or a combination thereof. In some embodiments, the P-type source / drain features 230P can be in-situ doped with the P-type dopant during an epitaxy process, and then the implantation process 300 can be skipped. If the P-type source / drain features 230P are not in-situ doped, the implantation process 300 (e.g., an ion implantation process) is performed to dope the P-type source / drain features 230P with the appropriate P-type dopant. In some embodiments, the P-type source / drain features 230P can have a P-type doping concentration of about 10 19 cm -3 and about 1021 cm -3 between the dopant concentrations. In an exemplary embodiment, the P-type source / drain features 230P after the P-type dopant implantation include silicon germanium boron. After the implantation process 300, the patterned photoresist layer 258 can be removed in a suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques.

[0135] Referring to Figure 28 and Figure 34 , the method 100' includes block 118, in which a cleaning process 310 is performed. The cleaning process 310 can include dry cleaning, wet cleaning, or a combination thereof. In some examples, the wet cleaning can include using standard clean 1 (RCA SC-1, a mixture of deionized water, ammonium hydroxide, and hydrogen peroxide), standard clean 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), a sulfuric acid-hydrogen peroxide mixture, and / or hydrofluoric acid for oxide removal. The dry cleaning process can include a helium and hydrogen treatment at a temperature between about 250 °C and about 550 °C, and a pressure between about 75 mTorr and about 155 mTorr. The hydrogen treatment can convert silicon on the surface to silane, which can be pumped out for removal. The cleaning process 310 can remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of silicide structures in subsequent processes.

[0136] Referring to Figure 28 and Figure 35In some embodiments, the method 100' includes block 120, in which a metal layer 260P is formed on the P-type element region 202P and on the N-type element region 202N. The metal layer 260P directly contacts the P-type source / drain features 230P, and directly contacts the dielectric liner 255 on the N-type source / drain features 230N. In other words, the metal layer 260P does not directly contact (or interface with) the N-type source / drain features 230N. In some embodiments, the metal layer 260P includes a P-type work function metal. The metal layer 260P can also be referred to as a P-type work function metal layer. A P-type work function metal is a metal that has a work function value (e.g., the energy by which a metal removes an electron) that is greater than (or more positive than) the Fermi level of a semiconductor. In some embodiments, the metal layer 260P includes nickel, platinum, palladium, vanadium, ruthenium, tantalum, titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbon nitride, tungsten nitride, molybdenum, other suitable metals, or combinations thereof. In an exemplary embodiment, the metal layer 260P includes nickel platinum. The metal layer 260P can include multiple film layers, and can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. In some embodiments, the metal layer 260P is a conformal film layer on the workpiece 200. In some embodiments, the metal layer 260P has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuities can cause the subsequently formed silicide layer to be non-uniform, reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied that could be used by other important features of the transistor.

[0137] Referring to Figure 28 and Figure 36In some embodiments, the heat treatment includes annealing the workpiece 200 at a temperature of about 300 °C to about 600 °C. In some embodiments, the composition of the ambient gas, the composition of the purge gas, the flow rate of the ambient gas, the flow rate of the purge gas, the pressure of the gas in the chamber, the temperature ramp rate, the temperature hold time, and the temperature range can be adjusted to facilitate the chemical reaction to form the silicide layer on the P-type source / drain feature 230P. Thus, the heat treatment initiates a chemical reaction between the P-type source / drain feature 230P and the metal layer 260P. For example, the P-type work function metal of the metal layer 260P reacts with the semiconductor atoms in the P-type source / drain feature 230P to form the silicide layer 270P. In an exemplary embodiment, the metal layer 260P includes nickel platinum, and the nickel platinum diffuses into the outer layer of the P-type source / drain feature 230P to react with the silicon in the P-type source / drain feature 230P. The reaction between the nickel platinum and the silicon creates a film layer of nickel platinum silicide as the silicide layer 270P. As a result, the thickness of the P-type source / drain feature 230P (e.g., along the Z direction) is reduced compared to before the heat treatment. The dashed line 262 represents the profile of the P-type source / drain feature 230P before the heat treatment, showing that the outer layer of the P-type source / drain feature 230P is converted to part of the silicide layer 270P. In some embodiments, before the heat treatment, the top surface of the P-type source / drain feature 230P is flush with the top surface of the N-type source / drain feature 230N, and after the heat treatment, the top surface of the P-type source / drain feature 230P is lower than the top surface of the N-type source / drain feature 230N.

[0138] In some embodiments, the silicide layer 270P includes nickel silicide, nickel platinum silicide, other silicide materials, or combinations thereof. In some embodiments, the silicide layer 270P has a thickness of about 5 nm to about 10 nm. If the silicide layer is too thin (e.g., less than 5 nm), the silicide layer can have limited efficacy in reducing contact resistance. In addition, the silicide can become non-uniform when thermal agglomeration and islanding occur. If the silicide layer is too thick (e.g., greater than 10 nm), a large portion of the source / drain material is consumed, and can cause issues such as speed reduction and leakage current. After the heat treatment, the portion of the metal layer 260P that is in direct contact with the P-type source / drain feature 230P is consumed and converted to the silicide layer 270P, while the other portion of the metal layer 260P that is in direct contact with the dielectric surfaces of the isolation structure 208 and the contact etch stop layer 232 does not participate in the chemical reaction. Thus, the difference in material composition between the silicide layer 270P and the remaining portion of the metal layer 260P allows the remaining portion of the metal layer 260P to be removed in subsequent processes.

[0139] Referring to Figure 28 and Figure 37The method 100' includes block 124 in which an etching process is performed to remove the remaining portion of the metal layer 260P from both the P-type device region 202P and the N-type device region 202N. The etching process is configured to remove the metal layer 260P without substantially etching the silicide layer 270P. In other words, this etching process is a selective etching process. As described above, this result is achieved because of the different material composition between the silicide layer 270P and the metal layer 260P. Any suitable etching method can be performed, such as a wet etching method. Also, any suitable etching chemistry can be used. In some embodiments, the etch rate of the metal layer 260P in the etching chemistry is at least 10 times greater than the etch rate of the silicide layer 270P in the same etching chemistry. As a result, the silicide layer 270P is only minimally affected by the etching process. The result of the etching process is that the dielectric liner 255 is exposed in the N-type device region 202N, while the top surface of the P-type source / drain feature 230P remains covered under the silicide layer 270P. Further, the silicide layer 270P is exposed in the P-type device region 202P.

[0140] Referring to Figure 28 and Figure 38 The method 100' includes block 125 in which a patterned photoresist layer 264 is formed to cover and protect the P-type device region 202P, and to remove the horizontal portion of the dielectric liner 255 from the N-type device region 202N. The N-type device region 202N is exposed in the openings of the patterned photoresist layer 264. The patterned photoresist layer 264 can be formed by a photolithography process. An exemplary photolithography process can include the process steps of photoresist coating, soft bake, mask alignment, exposure, post-exposure bake, photoresist development, and hard bake. The photolithography exposure process can also be performed or replaced by other suitable techniques, such as maskless lithography, e-beam writing, ion beam writing, or molecular imprinting. In some embodiments, the patterned photoresist layer 264 is a bottom anti-reflective coating. Subsequently, an etching process is performed to gouge through and remove the majority of the horizontal portion of the dielectric liner 255. The etching process is also referred to as a gouging etching process. In some embodiments, the gouging etching process can include an anisotropic dry etching process or other similar methods. In some embodiments in which the dielectric liner 255 is formed of an oxide compound, the gouging etching process is a reactive ion etching process with an etching process gas including trifluoromethane, argon, carbon tetrafluoride, nitrogen, oxygen, difluoromethane, sulfur trifluoride, other similar gases, or combinations thereof. In the illustrated embodiment, the result of the gouging etching process is that portions of the dielectric liner 255 remain on the sidewalls of the trench in the N-type device region 202N. Further, the recessed top surface of the N-type source / drain feature 230N is exposed in the trench.

[0141] Referring to Figure 28 and Figure 39N-type dopant into the N-type source / drain features 230N in an implantation process 320. The patterned photoresist layer 264 acts as an implantation mask to substantially prevent the N-type dopant from being implanted into the P-type element region 202P. The N-type dopant can be phosphorous, arsenic, antimony, or a combination thereof. In some embodiments, the N-type source / drain features 230N can be doped in situ with the N-type dopant during the epitaxial process, and then the implantation process 320 can be skipped. If the N-type source / drain features 230N are not doped in situ, the implantation process 320 (e.g., an ion implantation process) is performed to dope the N-type source / drain features 230N with the appropriate N-type dopant. In some embodiments, the N-type source / drain features 230N can have a doping concentration between about 10 19 cm -3 and about 10 21 cm -3 In an exemplary embodiment, the N-type source / drain features 230N after the N-type dopant implantation include silicon phosphide. After the implantation process 320, the patterned photoresist layer 264 can be removed in an appropriate etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other appropriate techniques.

[0142] Referring to Figure 28 and Figure 40 , the method 100' includes block 130, in which a cleaning process 330 is performed. The cleaning process 330 can include dry cleaning, wet cleaning, or a combination thereof. In some examples, the wet cleaning can include using standard clean 1 (RCA SC-1, a mixture of deionized water, ammonium hydroxide, and hydrogen peroxide), standard clean 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), a sulfuric acid-hydrogen peroxide mixture, and / or hydrofluoric acid for removing oxides. The dry cleaning process can include a helium and hydrogen treatment at a temperature between about 250 °C and about 550 °C, and a pressure between about 75 mTorr and about 155 mTorr. The hydrogen treatment can convert silicon on the surface to silane, which can be pumped out for removal. The cleaning process 330 can remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of silicide structures in subsequent processes.

[0143] Referring to Figure 28 and Figure 41In some embodiments, the method 100' includes block 132, in which a metal layer 260N is formed on the N-type element region 202N and on the P-type element region 202P. The metal layer 260N directly contacts the N-type source / drain feature 230N and directly contacts the silicide layer 270P on the P-type source / drain feature 230P. In other words, the metal layer 260N does not directly contact (or interface with) the P-type source / drain feature 230P. In some embodiments, the metal layer 260N includes an N-type work function metal. The metal layer 260N can also be referred to as an N-type work function metal layer. An N-type work function metal is a metal that has a work function value less than (or lower than) the Fermi level of a semiconductor. In some embodiments, the metal layer 260N includes titanium, aluminum, ytterbium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable metals, or combinations thereof. In an exemplary embodiment, the metal layer 260N includes titanium. The metal layer 260N can include multiple film layers, and can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. In some embodiments, the metal layer 260N is a conformal film layer on the workpiece 200. In some embodiments, the metal layer 260N has a thickness of about 5 nm to about 10 nm. If the thickness is too small (e.g., less than 5 nm), thermal agglomeration and / or islanding of discontinuity can cause the subsequently formed silicide layer to be non-uniform, reducing the effectiveness in reducing contact resistance. If the thickness is too large (e.g., greater than 10 nm), valuable space can be unnecessarily occupied, which can be used by other important features of the transistor.

[0144] Referring to Figure 28 and Figure 42In some embodiments, the method 100' includes a block 134 in which the workpiece 200 is subjected to a thermal treatment, such as an anneal. In some embodiments, the thermal treatment includes annealing the workpiece 200 at a temperature of about 300 °C to about 600 °C. In some embodiments, the composition of the ambient gas, the composition of the purge gas, the flow rate of the ambient gas, the flow rate of the purge gas, the pressure of the gas in the chamber, the temperature ramp rate, the temperature hold time, and the temperature range can be adjusted in order to promote the chemical reaction that forms the silicide layer on the N-type source / drain feature 230N. Thus, the thermal treatment initiates a chemical reaction between the N-type source / drain feature 230N and the metal layer 260N. For example, the N-type work function metal of the metal layer 260N reacts with the semiconductor atoms in the N-type source / drain feature 230N to form the silicide layer 270N. In exemplary embodiments, the metal layer 260N includes titanium, and silicon atoms diffuse from the N-type source / drain feature 230N into the metal layer 260N to react with the titanium of the metal layer 260N. The reaction between titanium and silicon creates a film layer of titanium silicide as the silicide layer 270N. As the silicon atoms diffuse upward into the metal layer 260N, the thickness of the N-type source / drain feature 230N (e.g., along the Z direction) can be substantially maintained as compared to before the thermal treatment. That is, after the thermal treatment, the top surface of the P-type source / drain feature 230P can be lower than the top surface of the N-type source / drain feature 230N, and the top surface of the silicide layer 270P can be lower than the top surface of the silicide layer 270N.

[0145] In some embodiments, the silicide layer 270N includes titanium silicide, titanium aluminum silicide, other silicide materials, or combinations thereof. In some embodiments, the silicide layer 270N has a thickness of about 5 nm to about 10 nm. If the silicide layer is too thin (e.g., less than 5 nm), the silicide layer can have limited efficacy in reducing contact resistance. Furthermore, the silicide can become non-uniform as thermal agglomeration and islanding occur. If the silicide layer is too thick (e.g., greater than 10 nm), a large portion of the source / drain material is consumed, and can cause problems such as reduced speed and leakage current. After the thermal treatment, the portion of the metal layer 260N that is in direct contact with the N-type source / drain feature 230N is consumed and converted to the silicide layer 270N, while the other portions of the metal layer 260N that are in direct contact with the dielectric surface of the isolation structure 208 and the silicide surface of the silicide layer 270P do not participate in the chemical reaction. Thus, the difference in material composition between the silicide layer 270N and the remaining portion of the metal layer 260N allows the remaining portion of the metal layer 260N to be removed in subsequent processes.

[0146] Referring to Figure 28 and Figure 43The method 100' includes a block 136 in which an etching process is employed to remove the remaining portions of the metal layer 260N from both the N-type device region 202N and the P-type device region 202P. The etching process is configured to remove the metal layer 260N without substantially etching the silicide layer 270N and the silicide layer 270P. In other words, this etching process is a selective etching process. As described above, this result is achieved because of the different material compositions between the metal layer 260N and the silicide layer 270N and the silicide layer 270P. Any suitable etching method can be implemented, such as a wet etching method. Moreover, any suitable etching chemistry can be used. In some embodiments, the etch rate of the metal layer 260N in the etching chemistry is at least 10 times greater than the etch rate of the silicide layer 270N and the silicide layer 270P in the same etching chemistry. As a result, the silicide layer 270N and the silicide layer 270P are only minimally affected by the etching process. The result of the etching process is that the silicide layer 270N and the silicide layer 270P are exposed in the N-type device region 202N and the P-type device region 202P, respectively. In addition, some residue of the metal layer 260N can remain on the top surface and the sidewall surfaces of the silicide layer 270P. For example, in some embodiments, the metal layer 260N includes titanium, and titanium-containing residue can remain as the sporadic islands 266 on the top surface of the silicide layer 270P.

[0147] Referring to Figure 28 and Figures 44-46 The method 100' includes a block 138 in which source / drain contacts 278 are formed on the silicide layer 270N and the silicide layer 270P. Figure 45 is a cross-sectional view along the line segment B-B of Figure 44 is a cross-sectional view along the line segment B-B of Figure 46 is a cross-sectional view along the line segment B-B of Figure 44A cross-sectional view of line segment C-C is shown in FIG. 2B. In particular, line segment B-B is taken along the length of the fin in the N-type element region 202N, while line segment C-C is taken along the length of the fin in the P-type element region 202P. Source / drain contacts 278 are formed in the remaining space of the trench 257, such that the trench 257 is completely filled. The source / drain contacts 278 can include a conductive barrier layer, and a metal fill layer on the conductive barrier layer. The conductive barrier layer can include titanium, tantalum, tungsten, cobalt, ruthenium, or a conductive nitride (such as titanium nitride, titanium aluminum nitride, tungsten nitride, tantalum nitride, or a combination thereof), and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable processes. The metal fill layer can include tungsten, cobalt, molybdenum, ruthenium, nickel, copper, or other metals, and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the source / drain contacts 278. In some embodiments, a planarization process (such as a chemical mechanical polishing process) is performed to planarize the top surface of the workpiece 200 and expose the metal gate stack 240. In the illustrated embodiment, the dielectric liner 255 separates the source / drain contacts 278 from the interlayer dielectric layer 234, such that they are not in direct contact. Further, as described above, the top surface of the silicide layer 270N can be above the top surface of the silicide layer 270P, and the top surface of the N-type source / drain component 230N can be above the top surface of the P-type source / drain component 230P.

[0148] Based on the above discussion, it can be seen that embodiments of the present application provide advantages over conventional techniques for making double silicide structures. However, it should be understood that particular advantages need not be present for other embodiments to provide different advantages, and not all advantages need be present in every embodiment. One advantage is that the double silicide structure allows the respective source / drain contact resistance in the N-type element region and the P-type element region to be individually optimized. Further, the process of the present application is compatible with existing manufacturing flows, and can be easily and cost-effectively implemented.

[0149] In one illustrative aspect, a method of forming a semiconductor device is directed. The method includes forming a first fin in a first element region of a first conductivity type and a second fin in a second element region of a second conductivity type, wherein the first conductivity type is different than the second conductivity type; forming a first epitaxial member on the first fin and a second epitaxial member on the second fin; depositing an etch stop layer covering the first epitaxial member and the second epitaxial member; removing the etch stop layer from the first element region; depositing a first metal layer on the etch stop layer in the second element region and on the first epitaxial member and in direct contact with the first epitaxial member; forming a first silicide layer from the first metal layer and the first epitaxial member; selectively removing the first metal layer; removing the etch stop layer from the second element region; depositing a second metal layer on the first silicide layer in the first element region and on the second epitaxial member and in direct contact with the second epitaxial member; forming a second silicide layer from the second metal layer and the second epitaxial member; selectively removing the second metal layer; and forming a first contact member on the first silicide layer and in direct contact with the first silicide layer and a second contact member on the second silicide layer and in direct contact with the second silicide layer.

[0150] In some embodiments, the method of forming a semiconductor device further includes forming an isolation component between the first epitaxial component and the second epitaxial component, wherein the isolation component has a first sidewall facing the first epitaxial component and a second sidewall facing the second epitaxial component, the first contact component is in direct contact with the first sidewall of the isolation component, and the second contact component is in direct contact with the second sidewall of the isolation component. In some embodiments, the method of forming a semiconductor device further includes forming a first mask component on the second element region before removing the etch stop layer from the first element region, wherein the first mask component is in direct contact with the second sidewall of the isolation component, and the first sidewall of the isolation component is exposed. In some embodiments, the method of forming a semiconductor device further includes forming a second mask component on the first element region before removing the etch stop layer from the second element region, wherein the second mask component is in direct contact with the first sidewall of the isolation component, and the second sidewall of the isolation component is exposed. In some embodiments, the method of forming a semiconductor device further includes implanting a first type of dopant into the first epitaxial component after removing the etch stop layer from the first element region, and implanting a second type of dopant into the second epitaxial component after removing the etch stop layer from the second element region, wherein the first type of dopant is different from the second type of dopant. In some embodiments, the first metal layer includes a P-type work function metal, and the second metal layer includes an N-type work function metal. In some embodiments, the method of forming a semiconductor device further includes, before depositing the etch stop layer, depositing an interlayer dielectric layer on the first epitaxial component and the second epitaxial component, etching the interlayer dielectric layer to form a first trench exposing a top surface of the first epitaxial component, and etching the interlayer dielectric layer to form a second trench exposing a top surface of the second epitaxial component, wherein the etch stop layer is deposited in the first trench in direct contact with the top surface of the first epitaxial component, and in the second trench in direct contact with the top surface of the second epitaxial component. In some embodiments, the method of forming a semiconductor device further includes removing a horizontal portion of the etch stop layer from the first element region, wherein a vertical portion of the etch stop layer remains on a sidewall of the first trench, and removing a horizontal portion of the etch stop layer from the second element region, wherein a vertical portion of the etch stop layer remains on a sidewall of the second trench. In some embodiments, the etch stop layer separates the first contact component and the second contact component from the interlayer dielectric layer, and is not in direct contact with the interlayer dielectric layer. In some embodiments, a residue of the second metal layer is inserted between the first silicide layer and the first contact component.

[0151] In another illustrative aspect, a method of forming a semiconductor device is disclosed. The method includes forming an isolation structure on a substrate; forming a first epitaxial component in a first element region and a second epitaxial component in a second element region, wherein the first epitaxial component and the second epitaxial component are over the isolation structure; depositing an etch stop layer on and in direct contact with the isolation structure, the first epitaxial component, and the second epitaxial component; depositing a dielectric layer on the etch stop layer; etching the dielectric layer to form a trench; depositing an isolation component in the trench, wherein the isolation component is between the first epitaxial component and the second epitaxial component; removing the dielectric layer; removing the etch stop layer from the first element region to expose the first epitaxial component; depositing a first metal layer on and in direct contact with the first epitaxial component on the etch stop layer in the second element region, wherein the first metal layer comprises a first type work function metal; forming a first silicide layer from the first metal layer and the first epitaxial component; removing the etch stop layer from the second element region to expose the second epitaxial component; depositing a second metal layer on and in direct contact with the second epitaxial component on the first silicide layer in the first element region, wherein the second metal layer comprises a second type work function metal, the second type work function metal being different from the first type work function metal; forming a second silicide layer from the second metal layer and the second epitaxial component; and forming a first contact component on and in direct contact with the first silicide layer and a second contact component on and in direct contact with the second silicide layer.

[0152] In some embodiments, the method of forming a semiconductor device further includes, after forming the first silicide layer, selectively removing the first metal layer; and, after forming the second silicide layer, selectively removing the second metal layer. In some embodiments, the first metal layer and the second metal layer are in direct contact with the isolation structure. In some embodiments, the first contact component and the second contact component are in direct contact with the isolation component. In some embodiments, the method of forming a semiconductor device further includes, after removing the etch stop layer from the first element region, implanting a first type dopant into the first epitaxial component; and, after removing the etch stop layer from the second element region, implanting a second type dopant into the second epitaxial component, wherein the first type dopant is different from the second type dopant. In some embodiments, the first silicide layer comprises nickel platinum silicide and the second silicide layer comprises titanium silicide.

[0153] In yet another illustrative aspect, a semiconductor device is directed. The semiconductor device includes: a first fin protruding from a substrate, the first fin extending in length in a first direction; a second fin protruding from the substrate, the second fin extending in length in the first direction; a first gate stack on the first fin and the second fin, the first gate stack extending in length in a second direction, the second direction being perpendicular to the first direction; a second gate stack on the first fin and the second fin, the second gate stack extending in length in the second direction; a first gate spacer layer disposed on sidewalls of the first gate stack; a second gate spacer layer disposed on sidewalls of the second gate stack; a first epitaxial component on the first fin, the first epitaxial component being sandwiched between the first gate stack and the second gate stack; a first silicide layer on the first epitaxial component, the first silicide layer including a first type of work function metal; a first contact component on the first silicide layer; a second epitaxial component on the second fin, the second epitaxial component being sandwiched between the first gate stack and the second gate stack; a second silicide layer on the second epitaxial component, the second silicide layer including a second type of work function metal, the second type of work function metal being different from the first type of work function metal; a second contact component on the second silicide layer; and an isolation component disposed between the first fin and the second fin. In a top view of the semiconductor device, the isolation component continuously extends from the first gate spacer layer to the second gate spacer layer along the first direction. In a cross-sectional view of the semiconductor device perpendicular to the first direction, the isolation component separates the first contact component from the second contact component.

[0154] In some embodiments, a top surface of the first silicide layer is below a top surface of the second silicide layer. In some embodiments, the first contact component is in direct contact with the first gate spacer layer, and the second contact component is in direct contact with the second gate spacer layer. In some embodiments, the semiconductor device further includes an isolation structure disposed on sidewalls of the first fin and the second fin, wherein the first contact component and the second contact component are in direct contact with the isolation structure.

[0155] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present embodiments and their context. Those skilled in the art should appreciate that they can readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such other embodiments with any number of variations and modifications or equivalent structures and processes can be used according to the teachings of the present embodiments without departing from the spirit of the present embodiments. Accordingly, the present embodiments are not limited by what has been presented in the description above.

Claims

1. A semiconductor device, comprising: a first fin protruding from a substrate, the first fin extending in length in a first direction; a second fin protruding from the substrate, the second fin extending in length in the first direction; a first gate stack on the first fin and the second fin, the first gate stack extending in length in a second direction perpendicular to the first direction; a second gate stack on the first fin and the second fin, the second gate stack extending in length in the second direction; a first gate spacer layer disposed on sidewalls of the first gate stack; a second gate spacer layer disposed on sidewalls of the second gate stack; a first epitaxial component on the first fin and sandwiched between the first gate stack and the second gate stack; a first silicide layer on the first epitaxial component; a first contact component on the first silicide layer; a second epitaxial component on the second fin and sandwiched between the first gate stack and the second gate stack; a second silicide layer on the second epitaxial component; a second contact component on the second silicide layer; and an isolation component disposed between the first fin and the second fin, wherein in a top view of the semiconductor device, the isolation component continuously extends from the first gate spacer layer to the second gate spacer layer along the first direction, and wherein in a cross-sectional view of the semiconductor device perpendicular to the first direction, the isolation component separates the first contact component from the second contact component. A top surface of the first silicide layer is below a top surface of the second silicide layer.

2. The semiconductor device according to claim 1, wherein The first contact component is in direct contact with the first gate spacer layer, and the second contact component is in direct contact with the second gate spacer layer.

3. The semiconductor device according to claim 1, wherein Further comprising:

4. The semiconductor device according to claim 1, wherein an isolation structure disposed on sidewalls of the first fin and the second fin, wherein the first contact component and the second contact component are in direct contact with the isolation structure. Further comprising:

5. The semiconductor device according to claim 4, wherein an etch stop layer disposed between the isolation component and the isolation structure. The isolation component has sloped sidewalls.

6. The semiconductor device according to claim 1, wherein A top surface of the first epitaxial component is lower than a top surface of the second epitaxial component.

7. The semiconductor device according to claim 1, wherein Each of the first gate stack and the second gate stack further comprises:

8. The semiconductor device according to claim 1, wherein a gate dielectric layer; and a gate electrode layer on the gate dielectric layer. Further comprising:

9. The semiconductor device according to claim 1, wherein a dielectric layer covering the first epitaxial component and the second epitaxial component, wherein the first contact component and the second contact component are disposed through the dielectric layer to contact the first silicide layer and the second silicide layer, respectively. The first contact component is separated from the dielectric layer by a dielectric liner, and the second contact component is separated from the dielectric layer by the dielectric liner.

10. The semiconductor device according to claim 9, wherein ​

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