Semiconductor structure

Abstract

The semiconductor structure comprises a P-type metal oxide field effect transistor (PMOS) region; an N-type metal oxide field effect transistor (NMOS) region; oxidation diffusion layer (OD) structures are located in the P-type metal oxide field effect transistor region and the N-type metal oxide field effect transistor region, and one of the oxidation diffusion layer structures and the other oxidation diffusion layer structure are evenly separated by a distance smaller than 20 nanometers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure. BACKGROUND

[0002] Semiconductor devices are commonly used in a wide range of electronic devices, such as computers, cell phones, and others. Semiconductor devices are formed from a semiconductor wafer through processes that include depositing many types of material films over the semiconductor wafer, and patterning the material films to form integrated circuits. The integrated circuits include field effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors.

[0003] One goal of the semiconductor industry is to continue to scale down the size and increase the speed of individual field effect transistors. To achieve these goals, fin-type field effect transistors (FinFETs) or multi-gate devices, such as gate-all-around (GAA) field effect transistors, are applied to nanosheets. Fin-type field effect transistors and multi-gate devices not only improve the area density, but also enhance the control of the channel gate. SUMMARY

[0004] Some embodiments of the present disclosure provide a semiconductor structure to solve the problem of the prior art about the consumption of metal gate boundary material.

[0005] In some embodiments, a semiconductor structure includes a p-channel metal oxide semiconductor region. A n-channel metal oxide semiconductor region. A plurality of oxide diffusion layer structures are located in the p-channel metal oxide semiconductor region and the n-channel metal oxide semiconductor region, wherein one and another of the oxide diffusion layer structures are uniformly spaced apart by a distance of less than 20 nanometers.

[0006] In some embodiments, a semiconductor structure includes a first gate-all-around field effect transistor structure including at least one nanosheet in a first transistor region, and a second gate-all-around field effect transistor structure including at least one nanosheet in a second transistor region, wherein the second gate-all-around field effect transistor structure is located at a distance of less than 20 nanometers from the first gate-all-around field effect transistor structure.

[0007] In some embodiments, a semiconductor structure includes a first gate-all-around field effect transistor structure including at least one nanosheet in a first transistor region, a second gate-all-around field effect transistor structure including at least one nanosheet in a second transistor region, wherein the second gate-all-around field effect transistor structure is located at a distance of less than 20 nanometers from the first gate-all-around field effect transistor structure, and a work function adjustment layer covering the at least one nanosheet of the first gate-all-around field effect transistor structure.

[0008] By the semiconductor structure described above, the consumption of the metal gate border material can be reduced, and thus the transistor density of the semiconductor structure can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] The nature of the disclosure is best understood from the following detailed description, when read in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. It is understood that the drawings are not limiting of the various aspects of the disclosure.

[0010] Figure 1 A flowchart of a method according to some embodiments;

[0011] Figures 2 to 13 A method according to some embodiments Figure 1 of manufacturing a semiconductor structure, wherein Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 is a Y-direction cross-sectional schematic view, Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 is an X-direction cross-sectional schematic view;

[0012] Figure 14 is an X-direction cross-sectional schematic view of the NFET region and the PFET region in a further process according to some embodiments;

[0013] Figure 15 is a top view illustrating the distance between the dimensions and the oxidized diffusion regions according to some embodiments.

[0014] SYMBOLS

[0015] 100: method

[0016] S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, S111: operation

[0017] 130: trench

[0018] 200: fin

[0019] 201: NFET region

[0020] 202: PFET region

[0021] 211: NFET region

[0022] 212: PFET region

[0023] 270: Distance

[0024] 271: Vertical edge

[0025] 272: Mask boundary

[0026] 280: Distance

[0027] 281: Vertical side

[0028] 282: Mask boundary

[0029] 290: Distance

[0030] 300: Semiconductor Structure

[0031] 330: Oxidation diffusion zone

[0032] 331: Thickness

[0033] 332: Distance

[0034] 400:Substrate

[0035] 402: Nanosheets / Second Epitaxial Layer

[0036] 500: Shallow trench isolation feature

[0037] 600: Source / Drain Region

[0038] 700: Interlayer dielectric layer

[0039] 800: Gate Trench

[0040] 801: Gate Dielectric Layer

[0041] 901: First material layer

[0042] 902: Second material layer

[0043] 903: Third material layer

[0044] 910: Mask

[0045] 911: Covered Area

[0046] 912: Covered Area

[0047] 915: Sidewall

[0048] 916: Sidewall

[0049] 920: Mask

[0050] 921: Covered Area

[0051] 922: Covered Area

[0052] 925: side wall

[0053] 926: side wall

[0054] D1: side dimension

[0055] D2: side dimension

[0056] D3: side dimension

[0057] D4: side dimension DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. The specific examples described below are provided for the purposes of simplicity and clarity. Indeed, the described examples are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly contacting each other, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact each other. Furthermore, in various examples, reference numerals and / or letters have been repeated in the figures for the sake of simplicity and clarity. Such repetition of reference numerals and / or letters is not to be construed as affecting the general scope of the various embodiments and / or configurations described herein.

[0059] Also for ease of description, spatial terms such as "beneath", "below", "lower", "above", "upper" and like terms can be used herein with respect to the orientation of one element or feature relative to another element or feature as illustrated in the figures. These spatial terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

[0060] When the spatially relative terms are used herein as described above, to orient the relationship of one element to another element, the first element can be directly above the other element, or there can be other elements or layers between the first element and the other element. When an element or layer is said to be on another element or layer, it means that it is directly on the other element or layer and in contact with it.

[0061] In particular embodiments, the material layer comprises at least 50 wt. % of the identifiable material, for example at least 60 wt. % of the identifiable material, or at least 75 wt. % of the identifiable material, at least 90 wt. % of the identifiable material; or at least 99 wt. % of the identifiable material; and the layer of the facet material comprises at least 50 wt. % of the identifiable material, for example at least 60 wt. % of the identifiable material, at least 75 wt. % of the identifiable material, at least 90 wt. % of the identifiable material, or at least 99 wt. % of the identifiable material. For example, in particular embodiments, the layer of titanium nitride and the layer of the facet material can represent a layer of at least 50 wt. % of titanium nitride, at least 60 wt. % of titanium nitride, at least 75 wt. % of titanium nitride, at least 90 wt. % of titanium nitride, or at least 99 wt. % of titanium nitride.

[0062] Unless otherwise indicated, molecular weight refers to weight average molecular weight (Mw). Unless otherwise indicated, the use of "a" or "an" or "the" means one or more. The use of "or" as a connective or disjunctive word is intended to encompass both alternatives and the alternative of the alternative. Synonyms such as "include," "including," and "includes" have the same meaning. The use of "about" in relation to a described quantity means that the quantity can vary from the stated amount by an amount that is within the ordinary skill of the person to which the description and claims relate. Generally, such amounts are ±10%. Thus, "about 10" means between 9 and 11. Unless otherwise explicitly stated, all numbers describing quantities, ratios of materials, physical properties of materials, and / or the like are understood to be modified by "about." Unless otherwise explicitly stated, the term "percent (%)," as used herein, is intended to mean percent by weight.

[0063] Briefly stated, the typical techniques associated with semiconductor device processing can not be described in detail herein. In addition, the various tasks and processes described herein can include a number of sub-steps that can be combined into a single step or further subdivided into additional sub-steps. It is also understood that the various tasks and processes described herein can be performed by specific hardware components or modules or by software components or modules that are executed by a suitably programmed digital computer. In particular, the various tasks and processes described herein can be performed by a combination of dedicated hardware components and suites of executable instructions, or tasks and processes can be performed by a suitably programmed digital computer. In general, the various tasks and processes described herein can be performed by any suitable means including, but not limited to, hardware, software, and / or firmware. Particular embodiments of the application are described herein, including the best mode known to the inventors of practicing the application at the time of filing. Of course, many modifications can be made by those skilled in the art, many of which have been noted above. Applicant does not wish to be bound by any particular details of the embodiments described herein, but instead intends to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application. Accordingly, other embodiments are within the scope of the following claims:

[0064] Embodiments of forming semiconductor devices, such as fin field effect transistors or multi-gate transistors, are described herein. Multi-gate transistors are transistors with gate structures formed on at least two sides of the channel region. Multi-gate devices can include a multi-gate device for a P-type metal oxide field effect transistor (PMOS) and / or a multi-gate device for an N-type metal oxide field effect transistor (NMOS). Specific examples herein can be or refer to gate-all-around (GAA) devices. Gate-all-around devices include any device with a gate structure that is formed on or partially on four sides of the channel region (such as around a portion of the channel region).

[0065] Embodiments disclosed herein also include nanosheet structures with a channel region. The term "nanosheet" refers to any material portion that is elongated in shape at the nanoscale or any cross-sectional portion that is elongated in shape at the microscopic scale, regardless of the profile shape of the cross-section. Thus, nanosheets can refer to elongated materials with circular and substantially circular cross-sections, such as nanowires, bundles, or rod-shaped materials that have a cross-section that is cylindrical or substantially rectangular.

[0066] As described herein, a method is provided to avoid loss of metal gate boundary material during processing. For example, forming an NMOS device adjacent to a PMOS device can include forming a material, such as a transition metal, over both devices, which can be performed before selectively masking or removing the material over one of the devices. Methods described herein are by wet etching, where the etchant does not excessively etch the mask to avoid damage to the material layer and underlying structures covered by the mask. For example, the etchant and conditions of the etching can be selected such that the maximum dimension etched by the etchant, such as the lateral or non-perpendicular dimension, of the mask is no more than 5 nm, such as no more than 4 nm, no more than 3 nm, or no more than 2 nm.

[0067] Reducing the dimension or depth of etching of the etchant to the mask reduces the degree of protection of the lateral dimension of the masked region by the mask. Thus, transistors can be positioned closer to other adjacent transistors. In other words, the transistor density of the semiconductor structure is increased.

[0068] Reference is made to Figure 1 describing a method 100 of fabricating a semiconductor structure, Figure 1 The method 100 and subsequent Figures 2 to 13 are collectively described, with each pair of figures being a set, illustrating a fin 200 at the same stage of processing, as shown below, Figure 2 and Figure 3 are a set, Figure 4 and Figure 5 are a set, Figure 6 and Figure 7As a group, Figure 8 and Figure 9 As a group, Figure 10 and Figure 11 As a group, Figure 12 and Figure 13 As a group, among which Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 and Figure 12 This is a schematic diagram of the cross-section in the Y direction, and Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 This is a schematic diagram of the cross-section in the X direction.

[0069] Interactive Reference Figure 1 , Figure 2 and Figure 3 ,At Figure 1 In operation S101 of method 100, a semiconductor structure 300 is provided over a semiconductor substrate 400. In some embodiments, the substrate 400 may be a semiconductor substrate, such as a silicon substrate. The substrate 400 may include different layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 400 may include different doping configurations based on design requirements of this art. For example, different dopants (such as P-type semiconductors and N-type semiconductors) may be formed in different regions on the substrate 400, and these regions are designed for different device types (such as N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for P-wells and phosphorus (P) for N-wells. In some embodiments, the surface portion of the substrate 400 includes at least one single crystalline semiconductor layer. Substrate 400 may comprise a single crystalline semiconductor material, but is not limited to silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). Alternatively, substrate 400 may comprise compound semiconductors and / or alloy semiconductors. In the described embodiments, substrate 400 is crystalline silicon.

[0070] One or more epitaxial layers are formed on the substrate 400. In some embodiments, an epitaxial stack is formed over the substrate 400 with first epitaxial layers (not shown) of a first composition interlaced with second epitaxial layers 402 of a second composition. The first and second compositions can be different. Embodiments can include providing different oxidation rates and / or etch selectivities for the first and second compositions. In one embodiment, the first epitaxial layers are silicon germanium (SiGe) and the second epitaxial layers 402 are silicon. In some embodiments herein, the first epitaxial layers include silicon germanium (SiGe) and the second epitaxial layers 402 include silicon, and the oxidation rate of silicon is lower than the oxidation rate of silicon germanium. It is noted that the second epitaxial layers 402 are shown in the figures as having three layers, which is for illustrative purposes only and does not limit the scope of the patent. It is noted that any number of epitaxial layers can be formed in a stack; the number of layers depends on the number of channel regions desired for the semiconductor structure 300. In some embodiments, the number of second epitaxial layers 402 is between 2 and 10, such as 6 or 7.

[0071] In some embodiments, the first epitaxial layers have a thickness in the range of 5 nm to 15 nm. The first epitaxial layers can have a substantially uniform thickness. In some embodiments, the second epitaxial layers 402 have a thickness in the range of 5 nm to 15 nm. In some embodiments, the second epitaxial layers 402 have a substantially uniform thickness. The second epitaxial layers 402 can serve as channel regions for subsequently formed multi-gate devices, and their thicknesses can be selected depending on the conditions under which the devices are to perform. The first epitaxial layers can serve to define gaps between adjacent channel regions for subsequently formed multi-gate devices, and their thicknesses depend on the conditions under which the devices are to perform.

[0072] Epitaxial growth can be performed in processes including molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes, as illustrated by the following examples. In some embodiments, the epitaxial growth layers, such as the second epitaxial layers 402, include the same material as the substrate 400. In some embodiments, the first epitaxial layers and the second epitaxial layers 402 include different materials than the substrate 400. As noted above, in at least some examples, the first epitaxial layers include silicon germanium epitaxial layers (SiGe) and the second epitaxial layers 402 include silicon. 1-x Ge x(where x ranges from 10 to approximately 55% in this document), and the second epitaxial layer 402 comprises a silicon epitaxial layer (Si). In contrast, in some embodiments, either the first or second epitaxial layer 402 may comprise other materials, as shown below, such as germanium (Ge), compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), indium gallium phosphide (GaInP), and / or gallium arsenide indium phosphide (GaInAsP), or any combination thereof. As mentioned above, the materials of the first and second epitaxial layers 402 may depend on the amount of oxidation and etch selectivity provided. In various embodiments, the first and second epitaxial layers 402 are substantially undoped (e.g., the exogenous doping concentration ranges from approximately 0 cm⁻¹). -3 Up to 1×10 17 cm -3 In other words, doping is not intentionally performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack are silicon-germanium layers (not shown in the figure). Conversely, in some embodiments, the bottom layer of the epitaxial stack is a silicon layer, and the top layer of the epitaxial stack is a silicon-germanium layer (not shown in the figure).

[0073] like Figure 3 As shown, the epitaxial stack is patterned to form fins 200 and trenches 130. In some embodiments, a mask layer (not shown) is formed over the epitaxial stack. The mask layer may include a first mask sublayer and a second mask sublayer. A particular first mask sublayer may be an oxide pad layer made of silicon oxide and may be formed by thermal oxidation. A particular second mask sublayer may be silicon nitride and may be formed by chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The mask layer is patterned to form a mask pattern and may be formed by patterning operations including lithography and etching. The epitaxial stack is subsequently patterned in an etching process, such as by dry etching (e.g., reactive ion etching), wet etching, and / or other suitable methods, and performed through openings defined by the patterned mask layer. The second epitaxial layer 402 is patterned to form fins 200. The process of forming fins 200 results in the formation of grooves 130 between pairs of parallel fins 200, such as... Figure 3 As shown.

[0074] Each fin 200 is raised from the substrate 400 in the Z-direction and has a length extending in the X-direction. The sidewalls of the fins 200 can be straight or angled (not shown). The fins 200 can have the same or different widths.

[0075] As shown in Figure 3 A shallow trench isolation feature 500 (STI) is formed in the trench 130 between adjacent fins 200. The shallow trench isolation feature 500 can be formed by filling a dielectric material layer in the trench 130 around the fins 200 to cover the top surfaces and sidewalls (not shown) of the fins 200. The dielectric material layer can include one or more dielectric materials. The dielectric material layer can include silicon dioxide (SiO2). Suitable dielectric materials for the dielectric material layer include silicon dioxide, silicon nitride, silicon carbide, fluorine silicon glass (FSG), low dielectric constant materials, and / or other suitable dielectric materials. The dielectric material can be deposited by any suitable technique, including temperature-controlled, flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition (HDP-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable spin-on techniques. The dielectric material layer can then be planarized, for example, using a chemical mechanical planarization (CMP) process, until the mask layer is exposed (not shown), and the dielectric material layer is recessed to form the shallow trench isolation feature 500, as shown in Figure 2 In some embodiments, the shallow trench isolation feature 500 is formed over the substrate 400. Any suitable etching technique can be used for the shallow trench isolation feature 500, including dry etching, wet etching, reactive ion etching (RIE), and / or other etching methods, and in some embodiments, anisotropic dry etching is used to selectively remove the dielectric material of the shallow trench isolation feature 500 but does not etch the fins 200. The mask layer (not shown) can be removed before, during, or after the shallow trench isolation feature 500. In some embodiments, the mask layer is removed by a chemical mechanical planarization (CMP) process before the shallow trench isolation feature 500. In some embodiments, the mask is removed with the etchant used for the shallow trench isolation feature 500.

[0076] Although not shown in the figures, a sacrificial gate is formed over the stack of second epitaxial layers 402. For example, in certain embodiments, the sacrificial material can include a sacrificial gate dielectric material and a sacrificial gate electrode material. A layer of sacrificial gate dielectric material is preferentially deposited. The layer of sacrificial gate dielectric material includes silicon dioxide, silicon nitride, or a combination thereof. In some embodiments, the layer of sacrificial gate dielectric material has a thickness in a range from 1 nm to 5 nm. A layer of sacrificial gate electrode material is then deposited over the layer of sacrificial gate dielectric material. In some embodiments, the layer of sacrificial gate electrode material has a thickness in a range from 100 nm to 200 nm. The layer of sacrificial gate electrode material includes a silicon material, such as polysilicon or amorphous silicon. In some embodiments, the layer of sacrificial gate electrode material is subjected to a planarization process. The layer of sacrificial gate dielectric material and the layer of sacrificial gate electrode material are deposited by a chemical vapor deposition (CVD) process, including low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable processes. In addition, a gate mask can be formed over the sacrificial material. The gate mask can include a silicon dioxide mask and a silicon nitride mask. The gate mask is subjected to a patterning and etching process, and the sacrificial material is etched to form a sacrificial gate.

[0077] After the sacrificial gate is formed, spacers can be formed, source / drain regions 600 can be formed, and an interlayer dielectric layer 700 (ILD) can be formed over the source / drain regions 600 and between the sacrificial gates. Depending on the context, "source / drain region" can independently or in combination represent a source or a drain. After the sacrificial gate structure is removed, gate trenches 800 are formed over the fins 200 and between the interlayer dielectric layer 700, as shown in Figure 2 In addition, after the first epitaxial layer of the epitaxial stack is removed, the remaining second epitaxial layers 402 are now formed as nanosheets 402, as shown in Figure 3 The nanosheets 402 constitute channel regions extending between the source / drain regions 600 and are parallel to each other and aligned along the Z direction.

[0078] As shown in Figure 2 and Figure 3As shown, a gate dielectric layer 801 may be deposited over the structure and cover the nanosheets 402. In some exemplary embodiments, the gate dielectric layer 801 is uniformly deposited and covers each of the nanosheets 402. According to some embodiments, the gate dielectric layer 801 comprises silicon dioxide, silicon nitride, or any of the above multilayer structures. In some embodiments, the gate dielectric layer 801 is a high dielectric constant material, and in some embodiments, the k-value of the gate dielectric layer 801 may be greater than about 7.0, and may comprise metal oxides or silicides of the following elements, such as hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and any combination thereof. Methods for forming the gate dielectric layer 801 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma chemical vapor deposition (PECVD), or other suitable methods.

[0079] Therefore, operation S101 can form a semiconductor structure 300 as described above.

[0080] Interactive Reference Figure 1 , Figure 2 and Figure 3 Method 100 further includes operation S102, forming a first material layer 901 in the gate trench 800 and encapsulating the nanosheet 402. For example, the first material may be deposited in a blanket manner in the interlayer dielectric layer 700 within the gate trench 800 and surround the nanosheet 402, such as... Figure 2 As shown, it simultaneously covers the shallow trench isolation feature 500, fin 200, and nanosheet 402, as... Figure 3 As shown. In a specific embodiment, the first material fills the spaces between the nanosheets 402 and is fused together, as... Figure 2 and Figure 3 As shown.

[0081] In some specific embodiments, the thickness of the formed first material layer 901 is at least 10 Å, for example at least 15 Å, at least 20 Å, at least 25 Å, at least 30 Å, or at least 32.5 Å. In some specific embodiments, the thickness of the formed first material layer 901 is no more than 50 Å, for example no more than 45 Å, no more than 40 Å, no more than 35 Å, or no more than 32.5 Å.

[0082] In some specific embodiments, Figure 2 The fin 200 includes an NFET region 201 and a PFET region 202. Furthermore, Figure 3 The fins 200 in the middle form NFET region 211 and PFET region 212 respectively.

[0083] In some specific embodiments, the first material layer 901 is made of a metal, such as a transition metal. For example, the first material layer 901 can include titanium (Ti), tungsten (W), vanadium (V), niobium (Nb), manganese (Mn), molybdenum (Mo), aluminum (Al), or a combination thereof. In some specific embodiments, the first material layer 901 is an N-type metal oxide semiconductor field effect transistor work function adjustment layer.

[0084] In some specific embodiments, the first material layer 901 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable methods.

[0085] By way of example, Figure 1 , Figure 4 with Figure 5 , the method 100 further includes an operation S103 of etching the first material layer 901. Specifically, a portion of the first material layer 901 is over the interlayer dielectric layer 700 (ILD), the first material layer 901 is over the shallow trench isolation feature 500, and the first material layer 901 is over the uppermost nanosheet 402, and the nanosheet 402 is etched to a desired vertical thickness. In some specific embodiments, the etching process operation S103 is anisotropic. In some specific embodiments, the etching process operation S103 is a dry etching or a plasma etching.

[0086] In some specific embodiments, after the etching process is performed, the first material layer 901 has a thickness of at least 5 A, such as at least 10 A, at least 12 A, at least 15 A, or at least 17 A. In some specific embodiments, after the etching process is performed, the first material layer 901 has a thickness of no more than 30 A, such as no more than 25 A, no more than 20 A, no more than 18 A, or no more than 17 A.

[0087] In some specific embodiments, the first material layer 901 has a thickness of at least 0.5 nanometer, such as at least 1 nanometer, at least 2 nanometers, at least 5 nanometers, at least 10 nanometers, at least 15 nanometers, or 20 nanometers. In some specific embodiments, the first material layer 901 has a thickness of no more than 20 nanometers, such as no more than 15 nanometers, no more than 10 nanometers, no more than 5 nanometers, or no more than 2 nanometers.

[0088] By way of example, Figure 1 , Figure 6 with Figure 7The method 100 further includes operation S104 to cover the selected region of the structure with a mask 910. The mask 910 can include a coating layer. For example, the coating layer can be a bottom anti-reflective coating (BARC). The BARC can provide absorption of incident light to the substrate during a photolithography process, including exposure processes of an overlying photoresist layer. In some embodiments, the coating layer can be formed to a thickness in a range of 80 nanometers (nm) to 200 nm.

[0089] The mask 910 can further include a reflective multi-layer (ML) overlying the coating layer. In some embodiments, the reflective ML can have a total thickness in a range of 3 nm to 7 nm.

[0090] Covering the selected region of the structure with the mask 910 can include removing the mask 910 from non-selected regions. For example, a photoresist can be formed over the mask 910. The photoresist can be a positive photoresist or a negative photoresist. In one embodiment, the photoresist is a chemical amplified photoresist (CAR). The photoresist can include a polymer, a photoacid generator (PAG) that causes a solubility change to a developer, a solvent, and / or other suitable components. The photoresist can be formed from a process such as a coating (e.g., a spin-on coating) and a soft bake. In some embodiments, the photoresist can be formed to a thickness in a range of 80 nm to 100 nm.

[0091] After the photoresist is formed, a patterning process is performed. For example, the method may use multiple and / or different radiation wavelengths to expose the energy-sensitive layer. In one embodiment, the mask is irradiated with ultraviolet (UV) radiation or extreme ultraviolet (EUV) radiation. The radiation beam may additionally or alternatively contain other radiation beams, such as ion beams, X-rays, extreme ultraviolet, deep ultraviolet, and other suitable radiation energies. In one case, the photoresist contains a photoacid-generating agent (PAG) that generates acid in photolithography, thus altering the solubility of the exposed / unexposed material. Lithography processes include immersion lithography, photolithography, optical lithograph, and / or other patterning methods that can transfer patterns onto the photosensitive layer. Patterning may also include a post-exposure bake (PEB) process. In the baking process, the photoresist layer is provided with gradually increasing temperatures. This condition causes more acid to be converted from photo-generated acids during the chemical amplification process. Furthermore, patterning may involve developing the photoresist layer. This development process may form a patterned photoresist layer containing multiple masking elements or features. During the development process, a developer is applied to the photoresist layer. In one embodiment, the developer removes the photoresist material under radiation exposure. However, this technique is also feasible when applied to negative photoresists. The developer or developing solution may be a positive or negative developer. One exemplary developer is tetramethylammonium hydroxide (TMAH).

[0092] After the photoresist undergoes a development process, the mask 910 is patterned, and the semiconductor structure 300 directly beneath it is defined as the covered area 911, while the semiconductor structure 300 not covered by the mask 910 is defined as the uncovered area 912. Figure 6 In this context, NFET region 201 is the covered region 911, while PFET region 202 is the uncovered region 912. Figure 7 In the NFET region 211, the covered region 911 is the NFET region 212, while the uncovered region 912 is the PFET region 212.

[0093] like Figure 6 and Figure 7 As shown, after patterning, the mask 910 has sidewalls 915 and sidewalls 916 respectively.

[0094] Interactive Reference Figure 1 , Figure 6 and Figure 7 Method 100 further includes operation S105, etching the first material layer 901 in the uncovered region 912. Specifically, the first material layer 901 in the uncovered region 912 may be completely removed.

[0095] In some particular embodiments, a wet etching process is performed by selecting an etchant for the first material layer 901 and the mask 910, and etching the first material layer 901 with the etchant. In some particular embodiments, the etching is isotropic to remove the first material layer 901. In some particular embodiments, the etchant includes a first component, an oxidizing agent, and water.

[0096] In some particular embodiments, the first component is an organic acid having a molecular weight in the range of 14 to 10 4 g / mol. In some particular embodiments, the first component is an organic acid and has a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element. In some particular embodiments, the first component is an organic acid, and the etchant has a concentration of the organic acid in the range of 0.001 to 100 wt. %.

[0097] In some particular embodiments, the first component is an organic base having a molecular weight in the range of 20 to 10 4 g / mol. In some particular embodiments, the first component is an organic base and has a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element. In some particular embodiments, the first component is an organic base, and the etchant has a concentration of the organic base in the range of 0.001 to 100 wt. %.

[0098] In some particular embodiments, the oxidizing agent is a peroxide, such as hydrogen peroxide. In some particular embodiments, the oxidizing agent is ozone. In some particular embodiments, the oxidizing agent is present in the etchant at a concentration in the range of 0.1 to 10 7 ppm.

[0099] In some particular embodiments, the etching process is performed at a temperature in the range of 10 to 70 °C. For example, the etching process is performed at a temperature of at least 10 °C, such as at least 20 °C, at least 30 °C, at least 40 °C, at least 50 °C, or at least 60 °C. In some particular embodiments, the etching process is performed at a temperature in the range of not more than 70 °C, such as not more than 60 °C, not more than 50 °C, not more than 40 °C, not more than 30 °C, or not more than 20 °C. In some particular embodiments, the etching process is performed at ambient temperature or room temperature.

[0100] As mentioned above, the etchant is selected to etch the first material layer 901 and avoid etching the mask 910. As shown in FIG. 9B, the etchant can etch a side dimension D1 of the mask 910 via the sidewall 915 in the X-direction. Similarly, as shown in FIG. 9C, the etchant can etch a side dimension D2 of the mask 910 via the sidewall 915 in the Y-direction. Figure 6 Figure 7 ​As shown, from the Y direction, the etchant can etch one side dimension D2 of the mask 910 via the sidewall 916. The one side dimension D1 and the side dimension D2 are each no more than 5 nm, such as no more than 4 nm, no more than 3 nm, or no more than 2 nm.

[0101] By way of example, Figure 1 , Figure 8 and Figure 9 , the method 100 proceeds to operation S106, removing the mask 910 from the covered region 911.

[0102] Further, the method 100 can proceed to operation S107, etching back the first material layer 901 from the covered region 911. In particular, the first material layer 901 is partially above the interlayer dielectric layer 700 (ILD), partially above the shallow trench isolation feature 500 (STI), and partially above the uppermost nanosheet 402, and the first material layer 901 above each of these is etched to a vertical thickness of zero, in other words, the first material layer 901 is removed from above each of the following: the interlayer dielectric layer 700 (ILD), the shallow trench isolation feature 500 (STI), and the uppermost nanosheet 402. After performing operation S107, the first material layer 901 is only below each nanosheet 402, and provides for the nanosheets 402 to be interconnected. In some particular embodiments, the etching process operation S107 is anisotropic. In some particular embodiments, the etching process operation S107 is dry etching or plasma ion etching.

[0103] By way of example, Figure 1 , Figure 10 and Figure 11 , the method 100 proceeds to operation S108, forming a second material layer 902 above the semiconductor structure 300. In particular, the second material layer 902 can be uniformly deposited above the gate dielectric layer 801, the interlayer dielectric layer 700 (ILD), the uppermost nanosheet 402, and the shallow trench isolation feature 500 (STI). In the uncovered region 912, the second material layer 902 covers the nanosheets 402. For example, the second material layer 902 fills in between the nanosheets 402, as shown in Figure 10 and Figure 11 .

[0104] In some particular embodiments, the second material layer 902 is a transition metal. For example, in some particular embodiments, the second material layer 902 is a work function adjustment layer.

[0105] The work function adjusting layer (second material layer 902) for the PFET region can comprise one or more layers of conductive material. For example, the second material layer 902 can comprise titanium, tungsten, vanadium, niobium, manganese, and / or molybdenum or other similar metals. For example, the second material layer 902 can be titanium nitride. In a particular embodiment, the second material layer 902 has a thickness in a range from 1 to 40 A, such as from 20 to 35 A, such as 30 A.

[0106] By cross-reference to Figure 1 , Figure 12 and Figure 13 , the method 100 additionally comprises operation S109 to cover the selected region of structure with a mask 920. The mask 920 can comprise a layer of coating material, such as a bottom anti-reflective coating (BARC), a reflective multi-layer (ML), and a photoresist, and is patterned in a manner similar to that described above with respect to Figure 6 and Figure 7 . After patterning, the mask 920 defines a covered region 921 of the semiconductor structure 300 directly underneath the mask 920, and an uncovered region 922 of the semiconductor structure 300 not covered by the mask 920. In Figure 12 , the PFET region 202 is the covered region 921, and the NFET region 201 is the uncovered region 922. In Figure 7 , the PFET region 212 is the covered region 921, and the NFET region 211 is the uncovered region 922.

[0107] As shown in Figure 12 and Figure 13 , after patterning, the mask 920 has a sidewall 925 and a sidewall 926.

[0108] By cross-reference to Figure 1 , Figure 12 and Figure 13 , the method 100 additionally comprises operation S110 to etch the second material layer 902 and the first material layer 901 for the uncovered region 922. In particular, the second material layer 902 and the first material layer 901 for the uncovered region 922 can be completely removed.

[0109] In some particular embodiments, an etchant specific to the second material layer 902, the first material layer 901, and the mask 920 is selected to perform the etching of the second material layer 902 and the first material layer 901 in a wet etching process. In some particular embodiments, the etching process to remove the second material layer 902 and the first material layer 901 is isotropic. In some particular embodiments, the etchant comprises a first component, an oxidizer, and water.

[0110] In some particular embodiments, the first component is a 14 to 10 4an organic acid having a molecular weight of 20 to 10,000 g / mol. In some particular embodiments, the first component is an organic acid and has a functional group comprising a Group III element, a Group IV element, a Group VI element, and / or a Group VII element. In some particular embodiments, the first component is an organic acid, and the etchant is an organic acid having a concentration ranging from 0.001 to 100 wt. %.

[0111] In some particular embodiments, the first component is an organic acid having a molecular weight of 20 to 10,000 g / mol. In some particular embodiments, the first component is an organic acid and has a functional group comprising a Group III element, a Group IV element, a Group VI element, and / or a Group VII element. In some particular embodiments, the first component is an organic acid, and the etchant is an organic acid having a concentration ranging from 0.001 to 100 wt. %. 4 an organic base having a molecular weight of 20 to 10,000 g / mol. In some particular embodiments, the first component is an organic base and has a functional group comprising a Group III element, a Group IV element, a Group VI element, and / or a Group VII element. In some particular embodiments, the first component is an organic base, and the etchant is an organic base having a concentration ranging from 0.001 to 100 wt. %.

[0112] In some particular embodiments, the oxidizing agent is a peroxide, such as hydrogen peroxide. In some particular embodiments, the oxidizing agent is ozone. In some particular embodiments, the oxidizing agent is present in the etchant at a concentration ranging from 0.1 to 10 7 ppm.

[0113] In some particular embodiments, the etching process is performed at a temperature ranging from 10 to 70 °C. For example, the etching process is performed at a temperature of at least 10 °C, such as at least 20 °C, at least 30 °C, at least 40 °C, at least 50 °C, or at least 60 °C. In some particular embodiments, the etching process is performed at a temperature not exceeding 70 °C, such as not exceeding 60 °C, not exceeding 50 °C, not exceeding 40 °C, not exceeding 30 °C, or not exceeding 20 °C. In some particular embodiments, the etching process is performed at ambient temperature or room temperature.

[0114] As mentioned above, the etchant is selected to etch the least or avoid etching the etch mask 920. As shown in FIG. 9A, the etchant can etch one side dimension D3 of the etch mask 920 via the sidewall 925 in the X direction. Similarly, as shown in FIG. 9B, the etchant can etch one side dimension D4 of the etch mask 920 via the sidewall 926 in the Y direction. The one side dimension D3 and the one side dimension D4 are each less than 5 nm, such as not more than 4 nm, not more than 3 nm, or not more than 2 nm. Figure 12 Figure 13 Referring to FIGS. 9A and 9B, the etch mask 920 has a sidewall 925 and a sidewall 926. The sidewall 925 and the sidewall 926 are each less than 5 nm, such as not more than 4 nm, not more than 3 nm, or not more than 2 nm.

[0115] Referring to FIGS. 9A and 9B, the etch mask 920 has a sidewall 925 and a sidewall 926. The sidewall 925 and the sidewall 926 are each less than 5 nm, such as not more than 4 nm, not more than 3 nm, or not more than 2 nm. Figure 1 , Figure 12 and Figure 13 ​, the method 100 can continue with other processes, such as completing the formation of metal gates. For example, the mask 920 can be removed from the covered regions 921 and additional metal layers can be formed in the process of forming metal gates over the NFET region 201, the PFET region 202, the NFET region 211, and the PFET region 212. Further, a gate electrode material can be deposited over the NFET region 201, the NFET region 211. An example gate material is a conductive material including one or more layers of metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or iridium (Ir), or other metals. In other embodiments, the conductive material includes a silicon alloy, including one of titanium silicon alloy (Ti x Si y ), cobalt silicon alloy (Co x Si y ), nickel silicon alloy (Ni x Si y ), tungsten silicon alloy (W x Si y ), molybdenum silicon alloy (Mo x Si y ), tantalum silicon alloy (Ta x Si y ), or other suitable conductive metals. In one embodiment, tungsten (W) is used as the material. The conductive material is formed by a process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or other suitable processes. Subsequent processes can form interlayer dielectric layers (ILD) and / or intermetal dielectric layers (IMD), form contacts and conductive interconnections, and other production line backend processes.

[0116] Figure 14 is a cross-sectional view, similar to Figure 13 , illustrating forming a third material layer 903 over the semiconductor structure 300 in the NFET region 211 and the PFET region 212. For example, the third material layer 903 can be a work function adjustment layer for the NFET region 211, such as a transition metal. For example, the third material layer 903 can be aluminum titanium (TiAl).

[0117] Before forming the third material layer 903, the remaining portion of the second material layer 902 has a distance 270 between the vertical edge 271 and the mask boundary 272 of the mask 920, for example, the mask boundary 272 is aligned with the sidewall 926. The distance 270 between the vertical edge 271 and the mask boundary 272 can be reduced, for example, 5 nanometers, due to the etching of the mask 920 up to 2 nanometers using an etchant in the etching process.

[0118] Based on the same etching process, the distance 280 between the vertical edge 281 of the nanosheet 402 of the NFET region 211 and the mask boundary 282 can also be reduced by 5 nanometers. Thus, the distance between transistors can also be reduced by 5 to 10 nanometers, such as 10 nanometers. The distance between transistors 290 can range from 15 to 30 nanometers.

[0119] Referring to Figure 15 is a top view of the semiconductor structure 300. Due to the reduced boundary loss in the etching processes of operation S105 and operation S110, the method now used is to reduce the boundary margin or tolerance. Oxidation diffusion regions 330 (OD, defining P-type metal-oxide field-effect transistor p-active regions / N-type metal-oxide field-effect transistor n-active regions) are equally spaced on the semiconductor structure. The oxidation diffusion regions 330 are active regions in which one or more device features can be formed thereon, such as source / drain regions.

[0120] As described above, each of the oxidation diffusion regions 330 has the same thickness 331. For example, the thickness 331 can range from 11 to 30 nanometers, such as 13 nanometers. In these embodiments, the shallow trench isolation features (STI) can have a thickness ranging from 33 to 48 nanometers, so the oxidation diffusion / shallow trench isolation feature ratio (OD / STI ratio) ranges from 0.23 to 0.91.

[0121] In addition, one and another of the adjacent oxidation diffusion regions 330 are separated by an evenly distributed distance 332. For example, the evenly distributed distance 332 can range from 36 to 46 nanometers, such as 36 nanometers.

[0122] Compared to those processes that do not etch the mask boundary by the etchant as described herein, with this layout, the oxidation diffusion pattern density can be improved by 15% to 20%, such as 17%.

[0123] In some particular embodiments, the wet etching is reduced by 5 to 7 nanometers, less than 2 nanometers, with an improvement of 71%.

[0124] In some particular embodiments, due to the necessary boundary margin reduction, the critical dimension can be improved by a range of 3 to 5 nanometers.

[0125] In some particular embodiments, the improvement in transistor density facilitates the wet etching in the original 26 nanometer oxidation diffusion layer (OD-OD) distribution distance, with a 5 nanometer improvement, with an improvement rate of 19.3%.

[0126] In some particular embodiments, the oxidation diffusion layer (OD-OD) distribution distance can be reduced by a range of 26 to 16 nanometers, with a decrease of 15% to 20%.

[0127] In some particular embodiments, the pH of the etchant is adjusted to reduce etching of the mask and reduce metal boundary shift.

[0128] In some particular embodiments, reducing the loss of metal boundaries provides higher semiconductor density.

[0129] In one embodiment, a method includes forming a first structure and a second structure over a substrate; forming a material layer over each of the first structure and the second structure; covering the first structure with a mask, wherein the second structure is uncovered; performing an etching process to remove the material layer from the second structure, wherein the etching process is performed by an etchant, the etchant includes a first component and an oxidizing agent, and wherein the first component is selected from an organic acid having a molecular weight of 14 to 10 4 g / mol, and an organic base having a molecular weight of 20 to 10 4 g / mol.

[0130] In some particular embodiments of the method, each structure includes at least one nanoplate, and forming the material layer over each structure includes depositing the material layer to cover each nanoplate.

[0131] In some particular embodiments of the method, the material layer includes a transition metal, and the material layer is formed to have a thickness in a range of 0.5 to 20 nanometers.

[0132] In some particular embodiments of the method, the first component is present in the etchant at a concentration of at least 0.001 wt. %.

[0133] In some particular embodiments of the method, the oxidizing agent is present in the etchant at a concentration in a range of 0.1 to 10 7 ppm.

[0134] In some particular embodiments of the method, the etching process is performed at a temperature in a range of 10 to 70 °C.

[0135] In some particular embodiments of the method, the first component is an organic acid having a molecular weight of 14 to 10 4 g / mol, and having a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element.

[0136] In some particular embodiments of the method, the first component is an organic base having a molecular weight of 20 to 10 4 g / mol, and having a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element.

[0137] In particular embodiments of some methods, the mask has a sidewall after covering the first structure with the mask, and the etchant etches the sidewall of the mask by less than 2 nanometers in dimension when performing the etching process.

[0138] In another embodiment, a method includes forming a first gate-all-around field effect transistor (GAAFET) structure including at least one nanosheet at a first transistor region; forming a second gate-all-around field effect transistor structure including at least one nanosheet at a second transistor region, wherein the second gate-all-around field effect transistor structure is located less than 20 nanometers from the first gate-all-around field effect transistor structure; forming a work function adjustment layer over each of the first gate-all-around field effect transistor structure and the second gate-all-around field effect transistor structure; forming a mask over the first gate-all-around field effect transistor structure, wherein the second gate-all-around field effect transistor structure is uncovered; and performing an etching process to remove the work function adjustment layer of the second gate-all-around field effect transistor structure with an etchant, wherein the etchant etches a dimension of the mask by less than 5 nanometers.

[0139] In particular embodiments of some methods, the etchant etches a dimension of the mask by less than 2 nanometers.

[0140] In particular embodiments of some methods, the work function adjustment layer is titanium, tungsten, vanadium, niobium, manganese, molybdenum, or aluminum.

[0141] In particular embodiments of some methods, the work function adjustment layer has a thickness of 10 to 40 A.

[0142] In particular embodiments of some methods, the etchant includes a first component, an oxidizing agent, and water, and the first component is an organic acid having a molecular weight of 14 to 10 4 g / mol and having a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element.

[0143] In particular embodiments of some methods, the etchant includes a first component, an oxidizing agent, and water, and the first component is an organic base having a molecular weight of 20 to 10 4 g / mol and having a functional group including a Group III element, a Group IV element, a Group VI element, and / or a Group VII element.

[0144] In particular embodiments of some methods, the etchant includes a first component and an oxidizing agent, the first component is selected from an organic acid and an organic base, and the first component is present in the etchant at a concentration of at least 0.001 wt. %.

[0145] In particular embodiments of some methods, the etchant includes a first component and an oxidizing agent, the first component is selected from an organic acid and an organic base, and the oxidizing agent is present in the etchant at a concentration of 0.1 to 10 7A concentration of 1 ppm is present in the etchant.

[0146] In some embodiments of the method, the etchant comprises a first component selected from the group consisting of an organic acid and an organic base, and an oxidizing agent that is hydrogen peroxide.

[0147] In another embodiment, the semiconductor structure comprises a P-type metal oxide semiconductor (PMOS) region; an N-type metal oxide semiconductor (NMOS) region; and oxide diffusion (OD) structures located in the PMOS region and the NMOS region, wherein one and the other of the oxide diffusion structures are uniformly spaced apart by a distance of less than 20 nm.

[0148] In some embodiments, one and the other of the oxide diffusion structures are uniformly spaced apart by a distance of 16 nm.

[0149] In some embodiments, the oxide diffusion structures have a thickness of 11 nm to 30 nm.

[0150] In one embodiment, the semiconductor structure comprises a first all-around gate field effect transistor structure comprising at least one nanosheet in a first transistor region, and a second all-around gate field effect transistor structure comprising at least one nanosheet in a second transistor region, wherein the second all-around gate field effect transistor structure is located at a distance of less than 20 nm from the first all-around gate field effect transistor structure.

[0151] In some embodiments, the semiconductor structure further comprises a first work function adjusting layer covering the at least one nanosheet of the first all-around gate field effect transistor structure.

[0152] In some embodiments, the semiconductor structure further comprises a second work function adjusting layer covering the at least one nanosheet of the second all-around gate field effect transistor structure.

[0153] In some embodiments, the first work function adjusting layer has a thickness of 10 Å to 40 Å.

[0154] In some embodiments, the at least one nanosheet of the first all-around gate field effect transistor structure has a thickness of 5 nm to 15 nm.

[0155] In one embodiment, a semiconductor structure includes a first all-around gate field effect transistor structure including at least one nanosheet in a first transistor region, a second all-around gate field effect transistor structure including at least one nanosheet in a second transistor region, wherein the second all-around gate field effect transistor structure is located at a distance of less than 20 nanometers from the first all-around gate field effect transistor structure, and a work function adjusting layer covering the at least one nanosheet of the first all-around gate field effect transistor structure.

[0156] In some particular embodiments, the work function adjusting layer has a thickness of 10 A to 40 A.

[0157] The foregoing outlines features of several embodiments so that a thorough comprehension of the disclosure can be attained. Familiarity with the art can be assumed without loss of generality. Those skilled in the art will recognize that the disclosure can be practiced with modification and alteration, and that the disclosure is not limited to the above described embodiments. Rather, the disclosure includes all such modifications and alterations and fall within the scope of the disclosure.

Claims

1. A semiconductor structure, characterized by, Comprising: a p-channel metal oxide semiconductor region; an n-channel metal oxide semiconductor region; and a plurality of oxide diffusion layer structures located in the p-channel metal oxide semiconductor region and the n-channel metal oxide semiconductor region, wherein one and another of the plurality of oxide diffusion layer structures are uniformly spaced apart by a distance of less than 20 nanometers.

2. The semiconductor structure of claim 1, wherein, wherein one and another of the plurality of oxide diffusion layer structures are uniformly spaced apart by a distance of less than 16 nanometers.

3. The semiconductor structure of claim 1, wherein, wherein a thickness of the plurality of oxide diffusion layer structures is 11 nanometers to 30 nanometers.

4. A semiconductor structure, characterized by Comprising: a first all-around gate field effect transistor structure comprising at least one nanosheet in a first transistor region; and a second all-around gate field effect transistor structure comprising at least one nanosheet in a second transistor region, wherein the second all-around gate field effect transistor structure is located at a distance of less than 20 nanometers from the first all-around gate field effect transistor structure.

5. The semiconductor structure of claim 4, wherein, further comprising a first work function adjusting layer covering the at least one nanosheet of the first all-around gate field effect transistor structure.

6. The semiconductor structure of claim 5, wherein, further comprising a second work function adjusting layer covering the at least one nanosheet of the second all-around gate field effect transistor structure.

7. The semiconductor structure of claim 5, wherein, wherein the first work function adjusting layer has to a thickness.

8. The semiconductor structure of claim 4, wherein, wherein a thickness of the at least one nanosheet of the first all-around gate field effect transistor structure is 5 nanometers to 15 nanometers.

9. A semiconductor structure, characterized by Comprising: a first all-around gate field effect transistor structure comprising at least one nanosheet in a first transistor region; a second all-around gate field effect transistor structure comprising at least one nanosheet in a second transistor region, wherein the second all-around gate field effect transistor structure is located at a distance of less than 20 nanometers from the first all-around gate field effect transistor structure; and a work function adjusting layer covering the at least one nanosheet of the first all-around gate field effect transistor structure.

10. The semiconductor structure of claim 9, wherein, wherein the work function adjusting layer has to a thickness.

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