Resistive memory element and memory device

Abstract

The utility model discloses a resistive memory element and a memory device, and the resistive memory element comprises a lower electrode structure, and a resistive layer and an upper electrode structure which are sequentially stacked above the lower electrode structure. A first side wall and a second side wall are sequentially arranged in the side wall direction, opposite to the resistive storage element, of the upper electrode structure and the resistive layer; the first side wall covers the upper electrode structure and the side wall of the resistive layer; the second side wall covers the surface of the first side wall; the first side wall and the second side wall are made of different materials. By utilizing the scheme of the invention, the backwash problem of the resistive random access memory in the preparation process can be solved, and the stability of the memory element is improved. The first side wall can resist heat and pressure and can be tightly combined with the upper electrode structure and the resistive layer, and the second side wall can be tightly combined with the first side wall and a dielectric material deposited in the subsequent contact hole preparation process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the technical field of memory data processing. More specifically, the present disclosure relates to a resistive memory element and a memory device. BACKGROUND

[0002] In the prior art, the preparation process of a resistive random access memory (RRAM) includes the following main steps: first, a first lower electrode layer is prepared on a copper substrate, then a second lower electrode layer, a resistive switching layer and an upper electrode structure are deposited, and finally the preparation of the resistive random access memory is completed by etching and cleaning the second lower electrode layer, the resistive switching layer and the upper electrode structure. However, when etching the second lower electrode layer, the sputtered metal is easily back-sputtered to the upper electrode structure and the resistive switching layer, which may affect the electrical performance.

[0003] Therefore, there is an urgent need to provide a resistive memory element to solve the back-sputtering problem of the resistive random access memory in the preparation process and increase the stability of the memory element. SUMMARY

[0004] To at least solve one or more of the above-mentioned technical problems, the present disclosure proposes a scheme for resistive random access memory data retention in various aspects.

[0005] In a first aspect, the present disclosure provides a resistive memory element, comprising a lower electrode structure and a resistive switching layer and an upper electrode structure which are sequentially stacked above the lower electrode structure, characterized in that the upper electrode structure and the resistive switching layer are sequentially provided with a first sidewall and a second sidewall in the direction of the sidewall of the resistive memory element; the first sidewall covers the sidewall of the upper electrode structure and the resistive switching layer; the second sidewall covers the surface of the first sidewall; the first sidewall and the second sidewall are made of different materials.

[0006] In some embodiments, the material of the first sidewall includes a metal oxide material, and the metal oxide material has an expansion coefficient less than a preset expansion coefficient value and a stress change value less than a preset stress change value within a preset temperature range.

[0007] In some embodiments, the thermal expansion coefficient of the first sidewall and the thermal expansion coefficient of the upper electrode structure are both less than the thermal expansion coefficient of the second sidewall.

[0008] In some embodiments, the melting point of the first sidewall is higher than the melting point of the second sidewall and the melting point of the upper electrode structure.

[0009] In some embodiments, the first sidewall has a first adhesive layer connecting both the upper electrode structure and the resistive switching layer, and the first sidewall has a second adhesive layer connecting the second sidewall.

[0010] In some embodiments, the first sidewall has a contact layer in contact with the upper electrode structure, and the contact layer is a dense metal oxide layer.

[0011] In some embodiments, the second sidewall employs a material comprising a dielectric material.

[0012] In some embodiments, the second sidewall has a third adhesive layer connecting a dielectric material deposited in a subsequent contact hole fabrication process.

[0013] In some embodiments, the metal element in the metal oxide material comprises one or more of aluminum, titanium, and hafnium.

[0014] In some embodiments, the dielectric material is a silicon-containing dielectric material.

[0015] In some embodiments, the dielectric material comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0016] In some embodiments, the first sidewall has a resistivity greater than a resistivity of the resistive switching layer.

[0017] In some embodiments, the first sidewall has a resistivity greater than 10 5 Ω·m.

[0018] In some embodiments, the lower electrode structure comprises a first lower electrode layer and a second lower electrode layer disposed above the first lower electrode layer.

[0019] In some embodiments, the upper electrode structure comprises a first upper electrode layer, a second upper electrode layer disposed above the first upper electrode layer, and an upper electrode hard mask layer disposed above the second upper electrode layer.

[0020] In some embodiments, the upper electrode hard mask layer has a thickness greater than a thickness of the second lower electrode layer, and the thickness of the upper electrode hard mask layer is greater than

[0021] In a second aspect, the present disclosure provides a resistive memory device comprising an array of the resistive memory elements of any of the embodiments of the first aspect.

[0022] With the help of the resistive memory element provided above, the embodiments of the present disclosure can solve the problem of back sputtering in the preparation process of the resistive memory and increase the stability of the memory element by sequentially arranging a first sidewall and a second sidewall in the direction of the sidewall of the resistive memory element opposite to the upper electrode structure and the resistive switching layer, wherein the first sidewall and the second sidewall are made of different materials. Further, in some embodiments, by using a material with stability and electronegativity for the first sidewall, the first sidewall can have an expansion coefficient less than a preset expansion coefficient value, a stress change value less than a preset stress change value, and form a covalent bond with the upper electrode structure and the resistive switching layer within a preset temperature range, so that the first sidewall can resist heat and pressure, and can be tightly combined with the upper electrode structure and the resistive switching layer. Further, in some embodiments, by using a material with bonding performance for the second sidewall, the second sidewall can form a covalent bond with the first sidewall and a dielectric material deposited in the subsequent contact hole process, so that the second sidewall can be tightly combined with the first sidewall and the dielectric material deposited in the subsequent contact hole process. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figures 1A-1E A semiconductor cross-sectional structure schematic diagram of a prior art resistive memory is shown;

[0025] Figure 2 An exemplary structural block diagram of a preparation method of a resistive memory element of the embodiments of the present application is shown;

[0026] Figures 3A-3F A semiconductor cross-sectional structure schematic diagram of a resistive memory element prepared by using the preparation method of the embodiments of the present application is shown. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0028] It should be understood that the terms "comprises" and "comprising" used in the specification and claims of the application indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] It should also be understood that the terms used in the specification and the claims are not to be interpreted as limiting, but rather as describing specific embodiments. As used in the specification and the claims, the singular forms "a," "an" and "the" include plural references unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0030] It should also be understood that, for the purpose of simplicity, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, can be used herein for the purpose of describing the relationship of one element or component to another element or component. When an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, then there are no intervening elements or layers present.

[0031] The specific embodiments of the present application will be described in detail below with reference to the attached drawings.

[0032] Figure 1A A semiconductor cross-sectional structure diagram of preparing a first lower electrode layer of a resistive random access memory in the prior art is shown.

[0033] As shown in Figure 1A A copper metal substrate 110 is provided, a first dielectric layer 120 and a second dielectric layer 130 are sequentially formed on the copper metal substrate 110 by a thin film deposition process, a deposition groove in communication with the copper metal substrate 110 is formed in the first dielectric layer 120 and the second dielectric layer 130 by a photolithography process and an etching process, and a first lower electrode layer 140 is deposited in the deposition groove by a thin film deposition process, a chemical mechanical polishing process, etc.

[0034] Figure 1B A semiconductor cross-sectional structure diagram of preparing a second lower electrode layer, a resistive layer and an upper electrode structure in the prior art is shown.

[0035] As shown in Figure 1BAs shown, a thin film deposition process is used to sequentially form a second lower electrode layer 150, a resistive switching layer 160, and an upper electrode structure 170 over the second dielectric layer 130 and the first lower electrode layer 140, wherein the upper electrode structure 170 includes a first upper electrode layer 171, a second upper electrode layer 172 disposed over the first upper electrode layer 171, and an upper electrode hard mask layer 173 disposed over the second upper electrode layer 172.

[0036] Figure 1C A semiconductor cross-sectional structure diagram showing the etching of the second lower electrode layer, the resistive switching layer, and the upper electrode structure in the prior art is shown. As shown, Figure 1C A photolithography process and an etching process are used to etch the second lower electrode layer 150, the resistive switching layer 160, and the upper electrode structure 170.

[0037] Figure 1D A semiconductor cross-sectional structure diagram showing the semiconductor structure causing sputtering in the prior art is shown. As shown, Figure 1D During the etching of the second lower electrode layer 150, metal back sputtering occurs on the first upper electrode layer 171 and the resistive switching layer 160, forming sputtering residues 180, which causes sidewall leakage of the resistive switching memory and affects the performance of the resistive switching memory.

[0038] Figure 1E A semiconductor cross-sectional structure diagram showing the cleaning of the resistive switching memory in the prior art is shown. As shown, Figure 1E During the cleaning of the resistive switching memory formed above, some sputtering residues can be removed during the enhanced cleaning of the sputtering caused by etching, but this easily causes side etching 190, and even causes peeling of the first upper electrode layer.

[0039] Therefore, the disclosure embodiments provide a preparation scheme of a resistive switching memory element, which sequentially arranges a first sidewall and a second sidewall in a direction away from the sidewall of the resistive switching memory element, wherein the materials of the first sidewall and the second sidewall are different, which can solve the back sputtering problem of the resistive switching memory during the preparation process and increase the stability of the resistive switching memory element.

[0040] Figure 2 An exemplary structural block diagram of a preparation method 200 of a resistive switching memory element according to an embodiment of the present application is shown.

[0041] As shown, Figure 2As shown in FIG. 2, in step S210, a first lower electrode layer is formed, and a second lower electrode layer, a resistance change layer and an upper electrode structure are sequentially formed on the first lower electrode layer. In step S220, the resistance change layer and the upper electrode structure are selectively etched to remove part of the resistance change layer and part of the upper electrode structure. In step S230, a first side wall and a second side wall are sequentially deposited on the remaining resistance change layer, the remaining upper electrode structure and the exposed area of the second lower electrode layer. In step S240, the second side wall, the first side wall and the second lower electrode layer are sequentially etched.

[0042] Based on Figure 2 the manufacturing process of the resistive memory element, the manufacturing process of the resistive memory element is described in detail below with reference to the semiconductor cross-sectional structure shown in Figures 3A-3F FIG. 2.

[0043] Figure 3A FIG. 2 shows a semiconductor cross-sectional structure of the first lower electrode layer according to an embodiment of the present application.

[0044] As shown in FIG. 2, a substrate 310 is provided, and a first dielectric layer 320 and a second dielectric layer 330 are sequentially formed on the substrate 310 by a thin film deposition process. A deposition groove is formed in the first dielectric layer 320 and the second dielectric layer 330 by a photolithography process and an etching process, and the first lower electrode layer 340 is deposited in the deposition groove. Figure 3A

[0045] Specifically, the material of the substrate 310 can be copper metal.

[0046] Specifically, the first dielectric layer 320 can be a silicon nitride layer for protecting the substrate 310, and the second dielectric layer 330 can be a silicon oxide layer for effectively isolating the first lower electrode layer 340 and the substrate 310 as an insulating layer.

[0047] Specifically, the first lower electrode layer 340 can be deposited in the deposition groove by a thin film deposition process, and the deposited first lower electrode layer 340 can be planarized by a chemical mechanical polishing process or the like, so that the upper surface of the first lower electrode layer 340 is flush with the upper surface of the second dielectric layer 330.

[0048] Specifically, the aforementioned thin film deposition process can include physical vapor deposition (PVD), chemical vapor deposition (CVD) or the like.

[0049] ​In the embodiment of the present application, the first lower electrode layer 340 can adopt one or a combination of a titanium nitride layer, a tungsten metal layer, a platinum metal layer, a gold metal layer, and a ruthenium metal layer. In a preferred embodiment, the first lower electrode layer 340 adopts a titanium nitride layer.

[0050] Figure 3B A semiconductor sectional structure diagram showing the preparation of the second lower electrode layer, the resistance change layer, and the upper electrode structure of the embodiment of the present application is shown.

[0051] As shown in Figure 3B , a second lower electrode layer 350, a resistance change layer 360, and an upper electrode structure 370 are sequentially formed above the second dielectric layer 330 and the first lower electrode layer 340 by using a thin film deposition process, wherein the upper electrode structure 370 includes a first upper electrode layer 371, a second upper electrode layer 372 disposed above the first upper electrode layer 371, and an upper electrode hard mask layer 373 disposed above the second upper electrode layer 372.

[0052] In the embodiment of the present application, the second lower electrode layer 350 can adopt one or a combination of a titanium nitride layer, a tungsten metal layer, a platinum metal layer, a gold metal layer, and a ruthenium metal layer, but the selection of the material of the second lower electrode layer 350 is not limited thereto, which is not limited herein. In a preferred embodiment, a tungsten metal layer is adopted for the second lower electrode layer 350 in actual material selection, so as to achieve the required electrical performance.

[0053] In the embodiment of the present application, the resistance change layer 360 can adopt one or a combination of an aluminum oxide layer, a titanium oxide layer, a zinc oxide layer, a nickel oxide layer, a hafnium oxide layer, and a zirconium oxide layer, so as to form a three-layer structure of the resistance memory element and achieve the required resistance change effect by disposing the resistance change layer 360.

[0054] In the embodiment of the present application, the first upper electrode layer 371 and the second upper electrode layer 372 can adopt one or a combination of a titanium nitride layer, an aluminum nitride layer, a titanium metal layer, a tantalum metal layer, an aluminum metal layer, and a nickel metal layer, but the selection of the material of the first upper electrode layer 371 and the second upper electrode layer 372 is not limited thereto, which is not limited herein. In a preferred embodiment, the first upper electrode layer 371 adopts an aluminum nitride layer, and the second upper electrode layer 372 adopts a titanium nitride layer.

[0055] In the embodiment of the present application, the upper electrode hard mask layer 373 can adopt a silicon nitride layer, but the material thereof is not limited thereto.

[0056] Figure 3C A semiconductor sectional structure diagram showing the etching of the resistance change layer and the upper electrode structure of the embodiment of the present application is shown. As shown in Figure 3CAs shown, the resistive switching layer 360 and the upper electrode structure 370 are selectively etched to remove the two side portions of the resistive switching layer 360 and the two side portions of the upper electrode structure 370.

[0057] In the embodiments of this application, various known processes can be used during the etching process, and there are no limitations in this regard. For example, photolithography and reactive ion etching (RIE) methods are used to pattern the resistive switching layer 360 and the upper electrode structure 370, so that the RIE etching stops above the second lower electrode layer 350.

[0058] Figure 3D A schematic diagram of the semiconductor cross-sectional structure of the deposited first and second sidewalls according to an embodiment of this application is shown.

[0059] like Figure 3D As shown, a first sidewall 381 and a second sidewall 382 are sequentially deposited in the exposed areas of the retained resistive switching layer 360, the retained upper electrode structure 370, and the second lower electrode layer 350, such that the first sidewall 381 covers the exposed areas of the retained resistive switching layer 360, the retained upper electrode structure 370, and the second sidewall 382 covers the first sidewall 381.

[0060] In the embodiments of this application, the first sidewall 381 and the second sidewall 382 are made of different materials. Therefore, the coefficient of thermal expansion of both the first sidewall 381 and the upper electrode structure 370 can be smaller than that of the second sidewall 382. By making the coefficients of thermal expansion of both the first sidewall 381 and the upper electrode structure 370 smaller than those of the second sidewall 382, ​​the accumulation of thermal stress caused by temperature changes during device fabrication and use can be effectively prevented, thereby reducing the risk of interface delamination or cracking caused by thermal stress. Furthermore, the first sidewall 381 and the upper electrode structure 370 have similar coefficients of thermal expansion, resulting in similar deformation during temperature changes, further improving their bonding stability.

[0061] To improve the bonding stability between the layers of the resistive memory element, the first sidewall 381 can form a first adhesive layer with the upper electrode structure 370 and the resistive switching layer 360, respectively. The first adhesive layer is a transition region structure formed by the strong interaction between the metal oxide material of the first sidewall 381 and the atoms on the surface of the upper electrode structure 370 and the resistive switching layer 360, which has a stronger bonding force than simple physical adsorption. Accordingly, a second adhesive layer can be formed between the first sidewall 381 and the second sidewall 382. The second adhesive layer is a mixed transition layer structure formed at the interface between the metal oxide of the first sidewall 381 and the silicon-containing dielectric material of the second sidewall 382, which enhances the bonding strength between the two layers. Similarly, a third adhesive layer is formed between the second sidewall 382 and the subsequently deposited dielectric material. The third adhesive layer is a network structure formed at the interface between the second sidewall 382 and the subsequently deposited dielectric material due to the presence of silicon elements in both, thereby significantly improving the bonding stability between the two.

[0062] Further, the melting point of the first sidewall 381 can be higher than the melting point of the second sidewall 382 and the melting point of the upper electrode structure 370. By setting the first sidewall 381 to have a higher melting point, it can be ensured that the first sidewall 381 maintains stable physical form and chemical properties during subsequent device processes, especially during high-temperature processes. The design of such material properties not only helps to prevent material softening or deformation during high-temperature processes, but also improves the reliability of the first sidewall 381 as a protective layer, thereby better protecting the upper electrode structure 370 and the resistive switching layer 360. At the same time, since the melting point of the first sidewall 381 is higher than the melting point of the upper electrode structure 370, the diffusion of the material of the upper electrode structure 370 can be effectively prevented during device preparation and use, further improving the stability and reliability of the device.

[0063] In some embodiments, the material used for the first sidewall 381 can have stability and electronegativity, so that it can have a coefficient of thermal expansion less than a preset coefficient of thermal expansion value, a stress change value less than a preset stress change value, and form a covalent bond with the upper electrode structure 370 and the resistive switching layer 360 within a preset temperature range.

[0064] In the embodiments of the present application, the preset temperature range is [T1, T2], where T1 and T2 can be set according to actual needs and the process used in the preparation of the first sidewall 381. In some embodiments of the present application, the preset temperature range is [200°C, 500°C]. By making the coefficient of thermal expansion of the first sidewall 381 less than the preset coefficient of thermal expansion value within the preset temperature range, the first sidewall 381 can be heat-resistant.

[0065] In the embodiments of the present application, the preset value of the coefficient of thermal expansion and the preset value of the stress change can be set according to actual needs and the process used in the preparation of the first sidewall 381, which is not limited herein.

[0066] By making the stress change value of the first sidewall 381 less than the preset value of the stress change in the preset temperature range, the first sidewall 381 can be made to be stress-resistant. By forming a covalent bond between the first sidewall 381 and the upper electrode structure 370 and the resistive switching layer 360, the first sidewall 381 can be tightly combined with the upper electrode structure 370 and the resistive switching layer 360.

[0067] By making the first sidewall 381 stress-resistant and heat-resistant, the thermal stability and stress stability of the prepared resistive switching element can be improved.

[0068] In some embodiments of the present application, the material used by the first sidewall 381 includes a metal oxide material. Since the metal oxide material has strong compactness, by setting the material used by the first sidewall 381 as a metal oxide material, the diffusion of the materials in the upper electrode structure 370 and the resistive switching layer 360 can be prevented, and a covalent bond can be formed between the first sidewall 381 and the upper electrode structure 370 and the resistive switching layer 360, thereby increasing the stability of the prepared resistive switching element, improving the performance of the prepared resistive switching element, and improving the reliability of the prepared resistive switching element.

[0069] In some embodiments, the first sidewall 381 of the present application can use a metal oxide material, in particular, an oxide containing one or more of aluminum, titanium, hafnium, and the like. Such materials have good thermal stability and chemical stability, and at the same time, due to their special electronic structure, they can form a stable interface with the upper electrode structure 370 and the resistive switching layer 360. In addition, these metal oxide materials have appropriate dielectric constants, so they can effectively prevent the generation of leakage current.

[0070] In the embodiments of the present application, the resistivity of the first sidewall 381 is greater than the resistivity of the resistive switching layer 360. Thus, the first sidewall 381 is more insulating than the resistive switching layer 360, which can effectively prevent the formation of a current path in the first sidewall 381 region, thereby guiding the current to flow more to the resistive switching layer 360 rather than the first sidewall, thereby improving the performance and reliability of the formed resistive switching element.

[0071] In some embodiments, the resistivity of the first sidewall 381 is greater than 10 5 Ω·m.

[0072] In the embodiments of the present application, the material of the second sidewall 382 has a bonding property, so that it can form a covalent bond with the first sidewall 381 and the dielectric material deposited in the subsequent contact hole manufacturing process. By forming a covalent bond between the second sidewall 382 and the first sidewall 381 and the dielectric material deposited in the subsequent contact hole manufacturing process, the second sidewall 382 can be tightly combined with the first sidewall 381 and the dielectric material deposited in the subsequent contact hole manufacturing process.

[0073] In some embodiments of the present application, the material of the second sidewall 382 is a dielectric material.

[0074] Specifically, the aforementioned dielectric material is a silicon-containing dielectric material. More specifically, the dielectric material includes one or more of silicon oxide, silicon nitride and silicon oxynitride, but the selection of the dielectric material is not limited thereto, which is not limited herein. By using a silicon-containing dielectric material for the second sidewall 382, the second sidewall 382 and the dielectric material deposited in the subsequent contact hole manufacturing process both contain silicon, so that a covalent bond is formed between the second sidewall 382 and the dielectric material deposited in the subsequent contact hole manufacturing process, and they are more tightly combined.

[0075] By tightly combining the first sidewall 381 with the upper electrode structure 370 and the resistive switching layer 360, and tightly combining the second sidewall 382 with the first sidewall 381 and the dielectric material deposited in the subsequent contact hole manufacturing process, the prepared resistive memory element is more stable.

[0076] In the embodiments of the present application, by covering the first sidewall 381 with the second sidewall 382, and using different materials for the first sidewall 381 and the second sidewall 382, the first sidewall 381 can be used as a stop layer in the subsequent etching process of the second sidewall 382, and a high-selectivity etching technology is used to etch the second sidewall 382, so as to improve the uniformity of etching (i.e. the uniformity of etching rate and depth).

[0077] In the embodiments of the present application, the first sidewall 381 is deposited by a PVD process, and the thickness of the first sidewall 381 is 2-9 nm. The second sidewall 382 is deposited by a CVD process, and the thickness of the second sidewall 382 is 9-50 nm. During the deposition of the second sidewall 382, the temperature is 200-500 °C.

[0078] By using a higher temperature (200-500 °C) in the process of depositing the second sidewall 382, when the material used in the first sidewall 381 is a metal oxide material, the first sidewall 381 and the upper electrode structure 370 and the resistive switching layer 360 form a covalent bond at a higher temperature, which enhances the bonding force between the first sidewall 381 and the upper electrode structure 370 and the resistive switching layer 360, and the first sidewall 381 and the second sidewall 382 form a covalent bond at a higher temperature, which makes the first sidewall 381 and the second sidewall 382 more closely combined.

[0079] Figure 3E A semiconductor cross-sectional structure diagram of etching the first sidewall, the second sidewall and the second lower electrode layer is shown.

[0080] As shown in Figure 3E , the first sidewall 381 is used as an etching stop layer to etch the second sidewall 382. Then, the first sidewall 381 is etched using the second lower electrode layer 350 as an etching stop layer, so that the remaining first sidewall 381 covers at least the sidewall of the remaining upper electrode structure 370 and the resistive switching layer 360, and the remaining second sidewall 382 covers the surface of the remaining first sidewall 381. Then, the second lower electrode layer 350 is etched.

[0081] During the etching of the second lower electrode layer, metal back sputtering occurs on the first sidewall 381 and the second sidewall 382, and thus the first sidewall 381 and the second sidewall 382 protect the resistive switching layer 360 and the first upper electrode layer 371 from the metal back sputtering.

[0082] Specifically, after etching the first sidewall 381, part of the upper electrode hard mask layer 373 is consumed during the etching of the second lower electrode layer. In order to reserve part of the upper electrode hard mask layer 373 to be consumed in the subsequent preparation process to protect the first upper electrode layer and the second upper electrode layer, the thickness of the upper electrode hard mask layer is greater than the thickness of the second lower electrode layer before the first sidewall and the second sidewall are partially etched, and the thickness of the upper electrode hard mask layer is greater than

[0083] Specifically, after part of the upper electrode hard mask layer 373 is consumed, the thickness of the remaining upper electrode hard mask layer is greater than and greater than the second lower electrode layer, thereby protecting the first upper electrode layer and the second upper electrode layer.

[0084] Figure 3F A semiconductor cross-sectional structure diagram of cleaning the resistive memory element is shown.

[0085] As shown in Figure 3FThe formed resistive memory element is cleaned. In the cleaning process of the metal back-sputtering caused by etching, the first sidewall 381 and the second sidewall 382 protect the resistive switching layer 360 and the first upper electrode layer 371, so that the cleaning process can remove the back-sputtering residues without causing RRAM side etching.

[0086] Specifically, in the cleaning process of the formed resistive memory element, the cleaning liquid used in the cleaning process is selected based on the material of the second sidewall. For example, since the material of the second sidewall is a silicon-containing dielectric material, the cleaning liquid used is EKC590.

[0087] The embodiment of the present application also provides a resistive memory element, which can be prepared by the preparation method 200 of the resistive memory element provided by the embodiment of the present application.

[0088] Specifically, the structural diagram of the resistive memory element can refer to Figures 3A-3F The resistive memory element includes a lower electrode structure, a resistive switching layer 360 and an upper electrode structure 370 stacked in sequence above the lower electrode structure, wherein the upper electrode structure 370 and the resistive switching layer 360 are provided with a first sidewall 381 and a second sidewall 382 in sequence in the direction of the sidewall of the resistive memory element; the first sidewall 381 covers the sidewall of the upper electrode structure and the resistive switching layer; the second sidewall 382 covers the surface of the first sidewall 381; the materials of the first sidewall 381 and the second sidewall 382 are different.

[0089] Specifically, the lower electrode structure includes a first lower electrode layer 340 and a second lower electrode layer 350 arranged above the first lower electrode layer 340. The upper electrode structure 370 includes a first upper electrode layer 371, a second upper electrode layer 372 arranged above the first upper electrode layer 371, and an upper electrode hard mask layer 373 arranged above the second upper electrode layer 372.

[0090] In the embodiment of the present application, the resistivity of the first sidewall 381 is greater than the resistivity of the resistive switching layer 360, so that the first sidewall 381 is more insulating than the resistive switching layer 360, which can effectively prevent the current from forming a path in the first sidewall 381 region, thereby guiding the current to flow more to the resistive switching layer 360 rather than the first sidewall. Specifically, the resistivity of the first sidewall 381 is greater than 10 5 Ω·m.

[0091] Specifically, the first sidewall 381 and the upper electrode structure 370 can form a covalent bond, which enhances the bonding force between the first sidewall 381 and the upper electrode structure 370, and the first sidewall 381 and the second sidewall 382 can form a covalent bond, so that the first sidewall 381 and the second sidewall 382 are more closely combined.

[0092] In the embodiments of the present application, the thickness of the upper electrode hard mask layer 373 is greater than and greater than the second lower electrode layer, thereby protecting the first upper electrode layer and the second upper electrode layer.

[0093] In summary, by virtue of the resistive memory element provided as above, the embodiments of the present disclosure can solve the problem of back sputtering in the preparation process of the resistive memory and increase the stability of the memory element by sequentially arranging the first sidewall and the second sidewall in the direction of the sidewall of the resistive memory element opposite to the upper electrode structure and the resistive layer, wherein the first sidewall and the second sidewall are made of different materials. Further, in some embodiments, by using a material with stability and electronegativity for the first sidewall, so that the expansion coefficient of the first sidewall is less than the preset expansion coefficient value, the stress change value is less than the preset stress change value, and a covalent bond is formed between the first sidewall and the upper electrode structure and the resistive layer, so that the first sidewall can resist heat and pressure, and can be tightly combined with the upper electrode structure and the resistive layer.

[0094] Further, in some embodiments, by using a material with bonding performance for the second sidewall, so that a covalent bond is formed between the second sidewall and the first sidewall, and a covalent bond is formed between the second sidewall and the dielectric material deposited in the subsequent preparation of the contact hole process, so that the second sidewall can be tightly combined with the first sidewall and the dielectric material deposited in the subsequent preparation of the contact hole process. In addition, in some embodiments, by setting the thickness of the upper electrode hard mask layer to be greater than the thickness of the second lower electrode layer, the first upper electrode layer and the second upper electrode layer are protected by the upper electrode hard mask layer.

[0095] The embodiments of the present application also provide a resistive memory device comprising an array of the resistive memory elements as described above.

[0096] Although the embodiments of the present application have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Many modifications, changes and substitutions can be made by those skilled in the art without departing from the idea and spirit of the present application. It should be understood that various alternatives to the embodiments of the present application described herein can be employed in practicing the present application. The appended claims are intended to define the scope of protection of the present application and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A resistive memory element comprising a lower electrode structure and a resistive switching layer and an upper electrode structure stacked in sequence over the lower electrode structure, characterized in that, The back-resistance memory element has a first sidewall and a second sidewall arranged in sequence in a sidewall direction of the upper electrode structure and the resistive switching layer, the first sidewall covers sidewalls of the upper electrode structure and the resistive switching layer, and the second sidewall covers a surface of the first sidewall. The first sidewall and the second sidewall are made of different materials.

2. The resistive memory element of claim 1, wherein, The first sidewall and the upper electrode structure have a thermal expansion coefficient less than that of the second sidewall.

3. The resistive memory element of claim 1 or 2, wherein, The first sidewall has a melting point higher than that of the second sidewall and the upper electrode structure.

4. The resistive memory element of claim 1, wherein, The first sidewall has a first adhesive layer connected with the upper electrode structure and the resistive switching layer, and has a second adhesive layer connected with the second sidewall.

5. The resistive memory element of claim 1, wherein, The first sidewall has a contact layer in contact with the upper electrode structure, and the contact layer is a dense metal oxide layer.

6. The resistive memory element of claim 1, wherein, The second sidewall is made of a dielectric material. The second sidewall has a third adhesive layer connected with a dielectric material deposited in a subsequent contact hole preparation process.

7. The resistive memory element of claim 6, wherein, The dielectric material is a silicon-containing dielectric material.

8. The resistive memory element of claim 1, wherein, The first sidewall has a resistivity greater than that of the resistive switching layer.

9. The resistive memory element of claim 8, wherein, The first sidewall has a resistivity greater than 10 5 Ω-m.

10. The resistive memory element of claim 1, wherein, The lower electrode structure includes a first lower electrode layer and a second lower electrode layer arranged above the first lower electrode layer.

11. The resistive memory element of claim 10, wherein, The upper electrode structure includes a first upper electrode layer, a second upper electrode layer arranged above the first upper electrode layer, and an upper electrode hard mask layer arranged above the second upper electrode layer.

12. The resistive memory element of claim 11, wherein, The upper electrode hard mask layer has a thickness greater than that of the second lower electrode layer, and the thickness of the upper electrode hard mask layer is greater than 250 Å.

13. A resistive memory device, comprising: The resistive memory device includes an array of the resistive memory elements as claimed in any one of claims 1-12.

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