Semiconductor test structure
By dividing the test area within the substrate and setting the gate projection to cover the doped region, the problem of not being able to place the test structure due to changes in chip shape is solved, thus achieving effective monitoring of semiconductor devices and efficient utilization of test space.
Patent Information
- Application Number
- CN202520502731.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-03-21
AI Technical Summary
As the chip shape changes, the number of dicing lines in the same exposure area decreases, making it impossible to place a complete test structure, which affects the testing efficiency of wafer acceptance testing.
A first test region and a second test region are divided within the substrate, and a gate is set on the substrate so that its projection covers part of the doped region. The doped region is connected by an electrical connector to simulate the different regional structures of a semiconductor device and reduce the size of a single semiconductor test structure.
It enables effective monitoring of different semiconductor device fabrication processes, improving the efficiency of testing space and wafer acceptance testing.
Smart Images
Figure CN223957957U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor test structure. BACKGROUND
[0002] Wafer Acceptance Test (WAT) is completed by using a test structure specially designed on a scribe lane of a wafer. By testing different combinations of various test structures and analyzing the corresponding test results, basically every process of wafer manufacturing can be monitored.
[0003] However, with the development of product function diversity, the shape of the chip also changes. Compared with the case where the shape of the chip is rectangular, in the case where the shape of the chip is square, the number of scribe lanes in the same exposure area is compressed, thereby causing a shot to be unable to place a set of test structures for monitoring a complete process. CONTENT OF THE UTILITY MODEL
[0004] Therefore, it is necessary to provide a semiconductor test structure to reduce the size of a single semiconductor test structure and improve the use efficiency of a test space.
[0005] The present application provides a semiconductor test structure, comprising:
[0006] a substrate comprising a first test region and a second test region arranged adjacent to each other along a surface direction of the substrate, a first doped region and a second doped region being arranged in the first test region and isolated from each other, and the first doped region and the second doped region extending from the first test region into the second test region, a third doped region being further arranged in the first test region and the second test region, and projections of the first doped region and the second doped region on the surface of the substrate falling into a region enclosed by a projection of the third doped region on the surface of the substrate;
[0007] a gate arranged above the substrate, a gate projection of the gate on the substrate falling into the first test region, and the gate projection covering part of the first doped region, part of the second doped region and part of the third doped region.
[0008] In one of the embodiments, the semiconductor test structure further comprises:
[0009] a plurality of electrical connectors arranged on the substrate near one side of the gate, and the plurality of electrical connectors being connected to the first doped region, the second doped region and the third doped region respectively.
[0010] In one of the embodiments, the electrical connector comprises:
[0011] a first electrical connection, a projection of the first electrical connection toward a direction of the substrate falls within the first test region, a plurality of the first electrical connections respectively connect a portion of the first doped region within the first test region, a portion of the second doped region within the first test region and a portion of the third doped region within the first test region;
[0012] a second electrical connection, a projection of the second electrical connection toward a direction of the substrate falls within the second test region, a plurality of the second electrical connections respectively connect a portion of the first doped region within the second test region, a portion of the second doped region within the second test region and a portion of the third doped region within the second test region.
[0013] In one embodiment, the gate includes one of a metal gate and a poly-silicon gate.
[0014] In one embodiment, when the gate is the poly-silicon gate, the semiconductor test structure further includes:
[0015] a gate lead disposed on a side of the gate away from the substrate.
[0016] In one embodiment, the semiconductor test structure further includes:
[0017] an isolation trench within the substrate, and the isolation trench is disposed between the first doped region and the second doped region, between the first doped region and the third doped region, and between the second doped region and the third doped region, respectively.
[0018] In one embodiment, the semiconductor test structure further includes:
[0019] a gate dielectric layer disposed between the gate and the substrate.
[0020] In one embodiment, the first doped region and the second doped region are of a same doping type, and the first doped region and the third doped region are of different types.
[0021] In one embodiment, the first doped region is a source region, and the second doped region is a drain region.
[0022] In one embodiment, the semiconductor test structure is disposed within a street of a wafer.
[0023] An unexpected benefit of this application is that by dividing the substrate into a first test region and a second test region, both regions contain a first doped region, a second doped region, and a third doped region. Simultaneously, by setting a gate and ensuring that the gate projection towards the substrate falls within the first test region, the first and second test regions of the semiconductor test structure respectively simulate the fabrication effects of different regions in a semiconductor device, facilitating the monitoring of different fabrication processes of the semiconductor device. Furthermore, by setting a semiconductor test structure including the first and second test regions, this application effectively reduces the size of a single semiconductor test structure, thereby improving the efficiency of test space utilization. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of a wafer structure when the chip shape is rectangular, as shown in the wafer acceptance test of a related technology.
[0026] Figure 2 This is a schematic diagram of a wafer structure when the chip shape is square during wafer acceptance testing of a related technology.
[0027] Figure 3 This is a schematic diagram of the test structure used in wafer acceptance testing for a related technology.
[0028] Figure 4 This is a schematic diagram of a semiconductor test structure provided in an embodiment of this application.
[0029] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the semiconductor test structure along the AB direction.
[0030] Figure 6 for Figure 4 The diagram shows a cross-sectional view of the semiconductor test structure along the CD direction.
[0031] Explanation of reference numerals in the attached figures:
[0032] 100 - First wafer; 110 - First exposure area; 111 - First chip; 112 - First dicing track;
[0033] 200 - Second wafer; 210 - Second exposure area; 211 - Second chip; 212 - Second dicing track;
[0034] 300 - test structure; 310 - field region test structure; 311 - first active region; 312 - field region electrical connection; 313 - gate layer; 320 - isolation region test structure; 321 - second active region; 322 - isolation region electrical connection; 330 - test pad;
[0035] 400 - semiconductor test structure; 410 - substrate; 411 - first doped region; 412 - second doped region; 413 - third doped region; 414 - isolation trench; 420 - gate; 430 - electrical connection; 431 - first electrical connection; 432 - second electrical connection; X1 - first test area; X2 - second test area. DETAILED DESCRIPTION
[0036] For the purposes of this application, reference will be made to the accompanying drawings in which embodiments of the application are illustrated. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0038] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected", or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.
[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0040] The singular forms "a", "an", and "the" used herein include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0041] In a typical wafer acceptance test (WAT), the test key used for electrical testing is usually set within the scribe line of the wafer. By combining different test keys to obtain and analyze the corresponding test results, each step in the wafer manufacturing process can be monitored.
[0042] See Figure 1 In one embodiment, a plurality of first exposure regions 110 are arranged in a two-dimensional array on the first wafer 100. Each first exposure region 110 is provided with a plurality of first chips 111, and the first chips 111 are rectangular in shape. A first dicing channel 112 is provided between two adjacent first chips 111.
[0043] See Figure 2 In one embodiment, a plurality of second exposure regions 210 are arranged in a two-dimensional array on the second wafer 200. Each second exposure region 210 is provided with a plurality of second chips 211, and the chip shape of the second chips 211 is square. A second dicing channel 212 is provided between two adjacent second chips 211.
[0044] like Figure 1 The first cutting channel 112 shown and as shown Figure 2 The second cutting channel 212 shown typically contains several test structures. (See reference...) Figure 3 In one embodiment, the test structure 300 includes a field test structure 310 and an isolation test structure 320, and both the field test structure 310 and the isolation test structure 320 are led out through different test pads 330 for wafer acceptance testing.
[0045] Among them, the multiple test pads 330 of the test structure 300 are along the cutting path where the test structure 300 is located (e.g., Figure 1 The first cutting channel 112 shown or Figure 2 The second dicing channel 212 shown is arranged in the extension direction, and different monitoring structures (not shown in the figure) can be set between each two adjacent test pads 330 to monitor whether the fabrication process of different parts of the semiconductor device meets the process requirements.
[0046] Continue reading Figure 3The field region test structure 310 and the isolation region test structure 320 are different in that the field region test structure 310 not only includes the first active region 311 and the field region electrical connector 312, but also is provided with the gate layer 313 to monitor whether the preparation process of the field region part in the semiconductor device meets the process requirement; while the isolation region test structure 320 is only provided with the second active region 321 and the isolation region electrical connector 322 to monitor whether the preparation process of the isolation region part in the semiconductor device meets the process requirement.
[0047] It should be noted that, Figure 3 The top view of the test structure 300 is shown in the figure, and in the actual test structure 300, the gate layer 313 is located above the film layer where the first active region 311 is located, and a gate dielectric layer (not shown in the figure) is arranged between the gate layer 313 and the first active region 311 for isolation.
[0048] However, with the development of product function diversity, the chip shape in the wafer is also changing, and when the chip shape changes, the number of cutting lanes in the same area of the exposure area (Shot) will change accordingly, which causes the problem that a complete test structure cannot be placed in a single exposure area in some cases, thereby failing to realize the monitoring of the complete process, and further affecting the test efficiency of the wafer acceptance test.
[0049] In order to solve the above problems, the present application provides a semiconductor test structure, which can realize the monitoring of different preparation processes of the semiconductor device while effectively reducing the size of a single semiconductor test structure, thereby improving the use efficiency of the test space and the test efficiency of the wafer acceptance test.
[0050] Figure 4 The structure of the semiconductor test structure provided by an embodiment of the present application is shown in the figure. Referring to Figure 4In one of the embodiments, the semiconductor test structure 400 comprises a substrate 410 and a gate 420; wherein the substrate 410 comprises a first test region X1 and a second test region X2 arranged adjacently along a direction parallel to a surface of the substrate 410, the first test region X1 is provided with a first doped region 411 and a second doped region 412 isolated from each other, and the first doped region 411 and the second doped region 412 extend from the first test region X1 into the second test region X2, the first test region X1 and the second test region X2 are further provided with a third doped region 413, and projections of the first doped region 411 and the second doped region 412 onto the surface of the substrate 410 all fall within a region enclosed by a projection of the third doped region 413 onto the surface of the substrate 410; the gate 420 is arranged above the substrate 410 in a spaced manner, and a gate projection (the topography of the gate projection is the same as that of a rectangular region corresponding to the gate 420) of the gate 420 towards the substrate 410 falls within the first test region X1, and the gate projection covers part of the first doped region 411, part of the second doped region 412 and part of the third doped region 413.
[0051] The semiconductor test structure as described above, by dividing the first test region and the second test region in the substrate, the first test region and the second test region both contain the first doped region, the second doped region and the third doped region, and by arranging the gate and making a gate projection of the gate towards the substrate fall within the first test region, the first test region and the second test region of the semiconductor test structure respectively simulate the preparation effect of different region structures in the semiconductor device, which helps to realize the monitoring of different preparation processes of the semiconductor device. In addition, by arranging the semiconductor test structure comprising the first test region and the second test region, the size of a single semiconductor test structure is effectively reduced, thereby improving the use efficiency of the test space.
[0052] Continuing to refer to Figure 4 In one of the embodiments, the semiconductor test structure 400 further comprises a plurality of electrical connectors 430 arranged on one side of the substrate 410 close to the gate 420, and the plurality of electrical connectors 430 are respectively connected to the first doped region 411, the second doped region 412 and the third doped region 413 to lead out the first doped region 411, the second doped region 412 and the third doped region 413 respectively, so as to perform electrical test on the semiconductor test structure.
[0053] Figure 5 A cross-sectional structure schematic view of the first test region in the semiconductor test structure provided by one of the embodiments of the present application (i.e. a cross-sectional structure schematic view along the AB direction in the figure); Figure 4 A cross-sectional structure schematic view of the second test region in the semiconductor test structure provided by one of the embodiments of the present application (i.e. a cross-sectional structure schematic view along the CD direction in the figure); Figure 6 A cross-sectional structure schematic view of the second test region in the semiconductor test structure provided by one of the embodiments of the present application (i.e. a cross-sectional structure schematic view along the CD direction in the figure); Figure 4A cross-sectional structure view in the CD direction).
[0054] Referring to Figure 5 and Figure 6 In one embodiment, the electrical connections 430 include first electrical connections 431 and second electrical connections 432. The first electrical connections 431 are projected towards the substrate 410 and fall within the first test region X1, and the first electrical connections 431 are respectively connected to the portions of the first doped region 411, the second doped region 412 and the third doped region 413 within the first test region X1. The second electrical connections 432 are projected towards the substrate 410 and fall within the second test region X2, and the second electrical connections 432 are respectively connected to the portions of the first doped region 411, the second doped region 412 and the third doped region 413 within the second test region X2.
[0055] It should be noted that in other embodiments of the present application, the number and arrangement of the electrical connections in the semiconductor test structure can be adjusted according to actual needs, as long as the arrangement of the electrical connections can meet the test requirements of each part of the semiconductor test structure, so as to ensure that the semiconductor test structure can be used for electrical testing.
[0056] Continuing to refer to Figure 5 In one embodiment, the gate 420 includes one of a metal gate and a poly gate. Figure 5 In the case of the metal gate, the side of the gate 420 away from the substrate 410 does not need to be provided with an additional gate lead-out. In other embodiments of the present application, in the case of the poly gate, the semiconductor test structure further includes a gate lead-out, and the gate lead-out is arranged on the side of the gate away from the substrate, so as to connect the external circuit to the gate in the subsequent test process.
[0057] It should be noted that the semiconductor test structure using the poly gate can be used for electrical testing of low-voltage (LV) devices, and the semiconductor test structure using the metal gate can be used for electrical testing of high-voltage (HV) devices. In other embodiments of the present application, the arrangement of part of the structure in the semiconductor test structure, i.e. the selection of the material, can be adjusted according to the type of semiconductor device to be tested by the semiconductor test structure, so as to ensure that the semiconductor test structure provided by the present application can monitor different process procedures of the semiconductor device.
[0058] In one embodiment, the semiconductor test structure further includes a gate dielectric layer disposed between the gate and the substrate to electrically isolate the gate from the substrate. Optionally, the gate dielectric layer is made of an insulating material, such as silicon oxide. It is noted that the gate dielectric layer is not shown in FIGS. 4A and 4B for the sake of clarity. Figure 4 and Figure 5 The gate dielectric layer is typically disposed in the blank area between the substrate 410 and the gate 420. For the sake of clarity, the gate dielectric layer is not shown in FIGS. 4A and 4B. Figure 4 and Figure 5 The gate dielectric layer is not shown in FIGS. 4A and 4B.
[0059] Referring to Figure 4 to Figure 6 The semiconductor test structure 400 further includes isolation trenches 414 formed in the substrate 410 to isolate the first doped region 411 from the second doped region 412, the first doped region 411 from the third doped region 413, and the second doped region 412 from the third doped region 413.
[0060] Continuing to refer to Figure 5 and Figure 6 In one embodiment, the first doped region 411 and the second doped region 412 are of the same doping type, and the first doped region 411 and the third doped region 413 are of different doping types. Optionally, the first doped region 411 includes an N+ doped region disposed in the substrate 410 proximate to the gate 420, and an N doped region disposed in the N+ doped region distal to the gate 420; the second doped region 412 is of the same structure and doping type as the first doped region 411; and the third doped region 413 is a P+ doped region. In other embodiments, the doping type and doping concentration of the doped regions in the substrate 410 can be adjusted as desired, which is not limited in the present application. For example, in one embodiment, the first doped region 411 can be a source region, and the second doped region 412 can be a drain region.
[0061] In one embodiment, the semiconductor test structure is disposed in a scribe lane of a wafer to improve the space utilization of the wafer.
[0062] The application has the unexpected effect that: by dividing the first test region and the second test region in the substrate, the first test region and the second test region both contain the first doped region, the second doped region and the third doped region, and by setting the gate and making the gate projection towards the substrate direction fall into the first test region, the first test region and the second test region of the semiconductor test structure respectively simulate the preparation effect of different region structures in the semiconductor device, which helps to realize the monitoring of different preparation processes of the semiconductor device. In addition, by setting the semiconductor test structure including the first test region and the second test region, the size of a single semiconductor test structure is effectively reduced, thereby improving the use efficiency of the test space.
[0063] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.
[0064] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.
[0065] The above-mentioned embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the application scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A semiconductor test structure, characterized by, The semiconductor test structure comprises: a substrate comprising a first test region and a second test region arranged adjacently along a direction parallel to a surface of the substrate, the first test region comprising a first doped region and a second doped region isolated from each other, and the first doped region and the second doped region extending from the first test region into the second test region, the first test region and the second test region further comprising a third doped region, a projection of the first doped region and the second doped region onto the surface of the substrate falling within a region enclosed by a projection of the third doped region onto the surface of the substrate; a gate electrode arranged above the substrate, a gate electrode projection of the gate electrode onto the direction of the substrate falling within the first test region and covering part of the first doped region, part of the second doped region and part of the third doped region.
2. The semiconductor test structure of claim 1, wherein, The semiconductor test structure further comprises: a plurality of electrical connections arranged on the substrate near a side of the gate electrode, the plurality of electrical connections respectively connecting the first doped region, the second doped region and the third doped region.
3. The semiconductor test structure of claim 2, wherein, The electrical connections comprise: a first electrical connection, a projection of the first electrical connection onto the direction of the substrate falling within the first test region, the plurality of first electrical connections respectively connecting part of the first doped region, part of the second doped region and part of the third doped region within the first test region; a second electrical connection, a projection of the second electrical connection onto the direction of the substrate falling within the second test region, the plurality of second electrical connections respectively connecting part of the first doped region, part of the second doped region and part of the third doped region within the second test region.
4. The semiconductor test structure of claim 1, wherein, The gate electrode comprises one of a metal gate electrode and a polysilicon gate electrode.
5. The semiconductor test structure of claim 4, wherein, In the case that the gate electrode is the polysilicon gate electrode, the semiconductor test structure further comprises: a gate electrode lead-out arranged on a side of the gate electrode away from the substrate.
6. The semiconductor test structure of claim 1, wherein, Further comprising: an isolation trench arranged in the substrate, and the isolation trench being arranged between the first doped region and the second doped region, between the first doped region and the third doped region, and between the second doped region and the third doped region.
7. The semiconductor test structure of claim 1, wherein, The semiconductor test structure further comprises: a gate dielectric layer arranged between the gate electrode and the substrate.
8. The semiconductor test structure of claim 1, wherein, The first doped region and the second doped region have the same doping type, and the first doped region and the third doped region have different doping types.
9. The semiconductor test structure of claim 1, wherein, The first doped region is a source region, and the second doped region is a drain region.
10. The semiconductor test structure of claim 1, wherein, The semiconductor test structure is arranged in a scribe lane of a wafer.