Improved structure of semiconductor memory packaging unit
By introducing redistribution layer technology into semiconductor memory packaging units, the problems of unstable soldering and design difficulties caused by dense circuits have been solved, enabling more flexible circuit layout and cost reduction, thereby improving product reliability and market competitiveness.
Patent Information
- Application Number
- CN202423166580.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2034-12-20
AI Technical Summary
In existing semiconductor memory packaging units, the circuitry on the chip package is too dense, resulting in inaccurate soldering, difficulty in circuit layout planning, increased manufacturing costs, and reduced product reliability and market competitiveness.
The redistribution layer technology adds a dielectric layer and conductive lines to the chip package. This technology improves the layout design space of the circuit, increases the spacing between lines, and connects external circuits through solder balls.
Improve welding reliability and product yield, reduce manufacturing costs, and enhance product market competitiveness.
Smart Images
Figure CN223957966U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor memory package unit, especially a semiconductor memory package unit with at least one additional redistribution layer on the chip package. BACKGROUND
[0002] Reference Figures 8 to 11 , which is a known standardized structure of a semiconductor memory package unit 1a, reference Figure 8 The semiconductor memory package unit 1a includes a chip package 10a, a plurality of first connectors 40a, and a substrate 50a. The chip package 10a is composed of the first connectors 40a and the substrate 50a to form the semiconductor memory package unit 1a. The chip package 10a includes a chip 11a and an insulating layer 30a. The chip 11a has a first surface 12a with a plurality of pads 13a. The insulating layer 30a is located on the chip 11a and covers the chip 11a. The insulating layer 30a has a first surface 31a and a plurality of first openings 32a. Each first opening 32a is provided with a copper pillar 321a for external electrical connection of the pads 13a of the chip 11a. A portion of each first connector 40a is arranged in each first opening 32a of the insulating layer 30a, and each first connector 40a is electrically connected to each pad 13a of the chip 11a through each copper pillar 321a. The substrate 50a is located on the first surface 31a of the insulating layer 30a and each first connector 40a. The substrate 50a has a first surface 51a and an opposite second surface 52a. The first surface 51a of the substrate 50a has a first protective layer 53a, and the second surface 52a of the substrate 50a has a second protective layer 54a. The first protective layer 53a has a plurality of second openings 55a, each second opening 55a has a first circuit 56a, and each first circuit 56a is externally electrically connected. Each first circuit 56a is externally electrically connected through a second connector 60a (such as a tin ball). The second protective layer 54a has a plurality of third openings 57a, each third opening 57a has a second circuit 58a. A portion of each first connector 40a is arranged in each third opening 57a, and each first connector 40a is electrically connected to each second circuit 58. Each first circuit 56a and each second circuit 58a has a conductive pillar 59a, and each conductive pillar 59a is electrically connected to each first circuit 56a and each second circuit 58a. In order to make the figure content simple and easier to clearly explain the relationship between the structures, therefore, in Figure 8The each pad 13a, the each first opening 32a, the each copper pillar 321a, the each first connecting body 40a, the each second opening 55a, the each first line 56a, the each third opening 57a, the each second line 58a and the each conductive pillar 59a in the semiconductor memory package unit 1a are taken as an example of 1 / 1 unit.
[0003] Referring to Figure 8 The thickness of the existing standard structure of the semiconductor memory package unit 1a is as follows: the thickness of the each copper pillar 321a is 50um, the thickness of the each first connecting body 40a is 20um, the thickness of the first outer layer 53a is 30um, the thickness of the each second line 58a is 25um, the thickness of the each conductive pillar 59a is 75um, the thickness of the substrate 50a is 75um, the thickness of the each first line 56a is 25um, and the thickness of the connecting body formed by the tin ball connected to the each first line 56a is 350um.
[0004] Referring to Figure 9 It is a chip side up view of the chip package 10a, the chip size is 9963um x 7498um, the minimum pad size on the chip 11a is 50um x 60um, and the minimum space between the each pad 13a is 30um.
[0005] Referring to Figure 10 It is a SBT top view of the substrate 50a, the POD is 11000um x 9000um, the minimum space between the each second line 58a on the second surface 52a is 30um, the minimum line width of the each second line 58a is 30um, the laser size is 200um, and the laser pad size is 100um.
[0006] Referring to Figure 11 It is a SBT bottom view of the substrate 50a, the minimum space between the each first line 56a on the first surface 51a of the substrate 50a is 30um, the minimum line width of the each first line 56a is 30um, the number of tin balls is 78, the size of the tin ball electrically connected to the each first line 56a is 500um, and the minimum ball pitch between the each tin ball is 800um.
[0007] However, the layout of the lines on the chip package 10a is too dense to be designed easily (as shown in Figure 9 Thus, the layout of the lines on the substrate 50a (as shown in Figure 10 Thus, the layout of the lines on the substrate 50a (as shown in Figure 11 Thus, the layout of the lines on the substrate 50a (as shown in
[0008] Therefore, a semiconductor memory package unit with an improved structure is provided to solve the problems of the dense layout of the lines on the chip package and the difficulty in designing the layout of the lines, to facilitate the layout of the lines by the manufacturer and reduce the cost of the manufacturer, and to improve the market competitiveness of the product. Content of the Invention
[0009] The main purpose of the present application is to provide a semiconductor memory package unit with an improved structure. The semiconductor memory package unit comprises a chip package, a plurality of first connecting bodies, and a substrate. The chip package comprises a redistribution layer with a dielectric layer and a plurality of conductive lines. Each conductive line is electrically connected to a plurality of pads of the chip of the chip package. The redistribution layer technique is used to improve the design space of the layout of each external connecting conductive line on the chip package. The semiconductor memory package unit is molded to increase the spacing between the lines and effectively solve the problems of the dense layout of the lines on the chip package and the difficulty in designing the layout of the lines in the existing semiconductor memory package unit. This facilitates the layout of the lines by the manufacturer and reduces the cost of the manufacturer, and improves the market competitiveness of the product.
[0010] To achieve the above object, the utility model provides a kind of improved structure of semiconductor memory package unit, the semiconductor memory package unit includes a chip package, multiple first connectors and a substrate, the chip package is by each the first connector with the substrate constitutes the semiconductor memory package unit;Wherein the chip package includes a chip and an insulating layer;Wherein the chip has a first surface, the first surface has multiple crystal pads;Wherein the insulating layer is located on the chip and covers the chip, the insulating layer has a first surface and multiple first openings, each the crystal pad of the chip can be electrically connected outside each the first opening;Wherein a part of each the first connector is arranged in each the first opening of the insulating layer, and each the first connector is electrically connected with each the crystal pad of the chip;Wherein the substrate is located on the first surface of the insulating layer and each the first connector, the substrate has a first surface and an opposite second surface, the first surface of the substrate has a first outer protective layer, and the second surface of the substrate has a second outer protective layer;Wherein the first outer protective layer has multiple second openings, a first circuit is arranged in each the second opening, and each the first circuit is electrically connected outside;Wherein the second outer protective layer has multiple third openings, each the third opening has a second circuit;Wherein a part of each the first connector is arranged in the multiple third openings, and each the first connector is electrically connected with each the second circuit;Wherein there is a conductive column between each the first circuit and each the second circuit, and each the conductive column is electrically connected with each the first circuit and each the second circuit;Wherein the semiconductor memory package unit further has a redistribution layer formed by using redistribution layer technology (RDL, Redistribution Layer), the redistribution layer is arranged between the chip and the insulating layer and covered by the insulating layer, and the redistribution layer has a dielectric layer and multiple conductive circuits;Wherein the dielectric layer has a first surface, the first surface of the dielectric layer is arranged on the first surface of the chip, and the dielectric layer has multiple grooves, each the groove can expose each the crystal pad of the chip outside;Wherein each the conductive circuit is arranged in the multiple grooves, and each the conductive circuit is electrically connected with each the crystal pad;Wherein each the conductive circuit is made of metal;Wherein the chip of the semiconductor memory package unit is electrically connected outside in sequence via each the crystal pad, each the conductive circuit, each the first connector, each the second circuit, each the conductive column and each the first circuit.
[0011] In a preferred embodiment of the utility model, each the conductive circuit exposed by each the first opening is further welded outside by using tin ball, and tin ball is further located in each the first opening and each the third opening after welding to form each the first connector.
[0012] In the preferable embodiment of the utility model, the first line of each second opening of the substrate is further welded with tin ball outside, and the tin ball further forms a second connecting body on the first line of each second opening after welding.
[0013] In the preferable embodiment of the utility model, the thickness of each crystal pad is 2um; the thickness of the dielectric layer is 10um; the thickness of each first connecting body is 50um; the thickness of the substrate is 135um; the thickness of the first outer protective layer is 30um; the thickness of the second outer protective layer is 30um; the thickness of the first line is 25um; the thickness of the second line is 25um; the thickness of each conductive column is 75um; and the thickness of each second connecting body is 350um.
[0014] In the preferable embodiment of the utility model, each first line, each second line and each conductive column are made of copper (Cu) metal material.
[0015] In the preferable embodiment of the utility model, the semiconductor memory packaging unit is further arranged on a printed circuit board (PCB).
[0016] In the preferable embodiment of the utility model, the memory type of the semiconductor memory packaging unit includes dynamic random-access memory (DRAM), static random-access memory (SRAM) and synchronous dynamic random-access memory (SDRAM). BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 It is the plane schematic view of the side section of the semiconductor memory packaging unit of the utility model.
[0018] Figure 2 It is the plane schematic view of the side section of the chip packaging combined with the substrate of the utility model.
[0019] Figure 3 It is the plane schematic view of the side section of the semiconductor memory packaging unit of the utility model setting tin ball.
[0020] Figure 4 It is the plane schematic view of the first surface of the insulating layer of the chip packaging of the utility model.
[0021] Figure 5 is a partial enlarged schematic view of Figure 4 .
[0022] Figure 6 is a plan view of a second surface of a substrate of the present application.
[0023] Figure 7 is a partial enlarged schematic view of Figure 6 .
[0024] Figure 8 is a plan view of a side cross-section of a conventional semiconductor memory package unit.
[0025] Figure 9 is a plan view of a first surface of an insulating layer of a conventional chip package.
[0026] Figure 10 is a plan view of a second surface of a conventional substrate.
[0027] Figure 11 is a plan view of a first surface of a conventional substrate.
[0028] BRIEF DESCRIPTION OF DRAWINGS 1 - semiconductor memory package unit; 10 - chip package; 11 - chip; 12 - first surface; 13 - pad; 20 - rewiring layer; 21 - dielectric layer; 211 - first surface; 212 - recess; 22 - via line; 30 - insulating layer; 31 - first surface; 32 - first opening; 40 - first connector; 41 - solder ball; 50 - substrate; 51 - first surface; 52 - second surface; 53 - first outer layer; 54 - second outer layer; 55 - second opening; 56 - first line; 57 - third opening; 58 - second line; 59 - conductive pillar; 60 - second connector; 61 - solder ball; 1a - semiconductor memory package unit; 10a - chip package; 11a - chip; 12a - first surface; 13a - pad; 30a - insulating layer; 31a - first surface; 32a - first opening; 321a - copper pillar; 40a - first connector; 50a - substrate; 51a - first surface; 52a - second surface; 53a - first outer layer; 54a - second outer layer; 55a - second opening; 56a - first line; 57a - third opening; 58a - second line; 59a - conductive pillar; 60a - second connector; 2 - printed circuit board. DETAILED DESCRIPTION
[0029] With reference to the drawings, the structure and technical features of the present application will be described as follows. It should be noted that the drawings are only used to illustrate the structural relationship and related functions of the present application, and thus the sizes of the elements in the drawings are not drawn according to the actual scale and are not used to limit the present application.
[0030] refer to Figure 1 The present invention provides an improved structure for a semiconductor memory packaging unit 1, which includes a chip package 10, a plurality of first connectors 40 and a substrate 50. The chip package 10 is formed by the first connectors 40 and the substrate 50 to form the semiconductor memory packaging unit 1.
[0031] The chip package 10 includes a die 11, a redistribution layer 20, and an insulating layer 30, such as Figure 1 As shown.
[0032] The chip 11 has a first surface 12, on which a plurality of crystal pads 13 are provided, such as Figure 1 As shown.
[0033] The redistribution layer 20 is formed using redistribution layer technology (RDL). The redistribution layer 20 is disposed between the chip 11 and the insulating layer 30 and is covered by the insulating layer 30. The redistribution layer 20 has a dielectric layer 21 and multiple conductive lines 22, such as... Figure 1 As shown; wherein the dielectric layer 21 has a first surface 211, the first surface 211 of the dielectric layer 21 is correspondingly disposed on the first surface 12 of the chip 11, the dielectric layer 21 has multiple grooves 212, each groove 212 allowing each die pad 13 of the chip 11 to be exposed to the outside, such as Figure 1 As shown; each conductive line 22 is disposed within each groove 212, and each conductive line 22 is electrically connected to each crystal pad 13, as shown. Figure 1 As shown; each of the conductive lines 22 is made of metal.
[0034] The insulating layer 30 is located on and covers the chip 11. The insulating layer 30 has a first surface 31 and a plurality of first openings 32. Each first opening 32 allows for external electrical connection between each pad 13 of the chip 11 and the external circuitry. Figure 1 As shown.
[0035] A portion of each first connector 40 is disposed within each first opening 32 of the insulating layer 30, and each first connector 40 is electrically connected to each crystal pad 13 of the chip 11, such as... Figure 1 As shown.
[0036] The substrate 50 is located on the first surface 31 of the insulating layer 30 and each of the first connectors 40. The substrate 50 has a first surface 51 and an opposing second surface 52. The first surface 51 of the substrate 50 has a first outer sheath 53, and the second surface 52 of the substrate 50 has a second outer sheath 54. Figure 1as shown; wherein the first outer protective layer 53 has a plurality of second openings 55, each second opening 55 has a first circuit 56 therein, each first circuit 56 is for external electrical connection, such as Figure 1 as shown; wherein the second outer protective layer 54 has a plurality of third openings 57, each third opening 57 has a second circuit 58 therein, such as Figure 1 as shown; wherein a portion of each first connecting body 40 is disposed in each third opening 57, and each first connecting body 40 is electrically connected with each second circuit 58, such as Figure 1 as shown; wherein each conductive column 59 is electrically connected with each first circuit 56 and each second circuit 58, such as Figure 1 as shown.
[0037] The chip 11 of the semiconductor memory packaging unit 1 is sequentially electrically connected with the external through the bumps 13, the conductive lines 22, the first connecting bodies 40, the second circuits 58, the conductive columns 59 and the first circuits 56, such as Figure 1 as shown.
[0038] In order to make the drawing content simple and easy to clearly explain the relationship between the structures, therefore, in Figure 1 the bumps 13, the first openings 32, the first connecting bodies 40, the second openings 55, the first circuits 56, the third openings 57, the second circuits 58 and the conductive columns 59 are taken as an example for explanation in units of one / one line, but not to limit the present application.
[0039] Referring to Figure 1 , the conductive lines 22 exposed by the first openings 32 are further externally soldered by the solder balls 41, and the solder balls 41 are further located in the first openings 32 and the third openings 57 after soldering to form the first connecting bodies 40 (as shown in Figure 2 ).
[0040] Referring to Figure 1 , the first circuits 56 of the second openings 55 of the substrate 50 are further externally soldered by the solder balls 61, and the solder balls 61 form a second connecting body 60 on the first circuits 56 of the second openings 55 after soldering (as shown in Figure 3 ); wherein the thickness of each second connecting body 60 is 350um, such as Figure 1 as shown.
[0041] The thickness of each structure on the semiconductor memory packaging unit 1 is as follows but not limited: the thickness of each bump 13 is 2um (as shown in Figure 1 ), the thickness of the dielectric layer 21 is 10um (as shown in Figure 3As shown), the thickness of each conductive line 22 is 10um (as shown). Figure 2 As shown), the thickness of each first connector 40 is 50 μm (as shown). Figure 2 As shown), the thickness of the substrate 50 is 135 μm (as shown). Figure 3 As shown), the first outer protective layer 53 has a thickness of 30 μm (as shown). Figure 2 As shown), the second outer protective layer 54 has a thickness of 30 μm (as shown). Figure 3 As shown), the thickness of the first line 56 is 25µm (as shown). Figure 3 As shown), the thickness of the second line 58 is 25µm (as shown). Figure 2 As shown), the thickness of each conductive post 59 is 75µm (as shown). Figure 2 (As shown).
[0042] refer to Figure 2 Each conductive line 22 is made of silver (Ag) metal material, but is not limited to silver metal material. The silver metal material has the characteristics of relatively low cost, high conductivity and low temperature sintering, but since silver metal material is a common material, it will not be described in detail here; each first line 56, each second line 58 and each conductive post 59 is made of copper (Cu) metal material, but is not limited to copper metal material.
[0043] refer to Figure 1 The semiconductor memory packaging unit 1 is further disposed on a printed circuit board 2 (PCB), but is not limited thereto, in order to facilitate diversified applications.
[0044] refer to Figure 1 The memory type of the semiconductor memory package unit 1 includes dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM), but is not limited to any of them, in order to facilitate diversified applications.
[0045] refer to Figure 1The chip package 10 has a chip size of 9963um x 7498um, a minimum pad size of 60um x 149.8um, a minimum space between die pads of 20um, a minimum line width of 40um, a L2F-DIE align of 5um, a ball size of 170um, and a number of balls of 90, but not limited to.
[0046] Referring to Figure 4 The POD of the substrate 50 is 11000um x 9000um, the minimum space between the second lines 58 on the second surface 52 is 70um, the minimum line width of the second lines 58 is 70um, the laser size is 127um, and the laser pad size is 250um, but not limited to.
[0047] According to the current manufacturing practice of semiconductor memory package units, the manufacturing cost of a partial element (e.g. a printed circuit board) in a known existing standardized structure of a semiconductor memory package unit is about 0.6 dollars. The manufacturing cost of the related partial element (e.g. the redistribution layer / RDL 20 and the printed circuit board / PCB 2) corresponding to the semiconductor memory package unit 1 of the present application is estimated to be about 0.3 dollars by the applicant. Therefore, it can be known that, although the present application increases the manufacturing of the redistribution layer (RDL), it is at least cheaper by about half the price.
[0048] The method of manufacturing the semiconductor memory package unit 1 can include the following steps, but not limited to:
[0049] Step S1: providing a chip (Die) 11, as shown in Figure 5 ; wherein the chip 11 has a first surface 12, and the first surface 12 has a plurality of die pads 13, as shown in Figure 1 .
[0050] Step S2: using a redistribution layer technique (RDL, Redistribution Layer) to set a redistribution layer 20 on the first surface 11 of the chip 11, as shown in Figure 1As shown; the redistribution layer 20 has a dielectric layer 21 and multiple conductive lines 22, such as Figure 1 As shown; wherein the dielectric layer 21 has a first surface 211, the first surface 211 of the dielectric layer 21 is correspondingly disposed on the first surface 12 of the chip 11, the dielectric layer 21 has multiple grooves 212, each groove 212 allowing each die pad 13 of the chip 11 to be exposed to the outside, such as Figure 1 As shown; each conductive line 22 is disposed within each groove 212, and each conductive line 22 is electrically connected to each crystal pad 13, as shown. Figure 1 As shown.
[0051] Step S3: An insulating layer 30 is formed on the chip 11 and the redistribution layer 20, and the insulating layer 30 covers the chip 11 and the redistribution layer 20 together, thereby forming a chip package 10, as shown below. Figure 1 As shown; the insulating layer 30 has a first surface 31 and a plurality of first openings 32, each first opening 32 allowing each pad 13 of the chip 11 to be electrically connected to the external environment, such as... Figure 1 As shown.
[0052] Step S4: Provide a substrate 50, such as Figure 1 As shown; wherein the substrate 50 has a first surface 51 and an opposing second surface 52, the first surface 51 of the substrate 50 has a first outer protective layer 53, and the second surface 52 of the substrate 50 has a second outer protective layer 54, as shown. Figure 1 As shown; the first outer sheath 53 has multiple second openings 55, each second opening 55 containing a first circuit 56, each first circuit 56 being for external electrical connection, such as... Figure 1 As shown; the second outer sheath 54 has multiple third openings 57, and each third opening 57 contains a second circuit 58, as shown. Figure 1 As shown; a conductive post 59 is provided between each of the first lines 56 and each of the second lines 58, as shown. Figure 1 As shown, each conductive post 59 is electrically connected to each first line 56 and each second line 58, as follows: Figure 1 As shown.
[0053] Step S5: Electrically connect the chip package 10 and the substrate 50 together using multiple solder balls 40a, such as... Figure 2 As shown, after soldering, each solder ball 40a forms a plurality of first interconnects 40 between the chip package 10 and the substrate 50, such as... Figure 1 As shown, this constitutes a semiconductor memory package unit 1; wherein a portion of each first connector 40 is disposed within each first opening 32 of the insulating layer 30, and each first connector 40 is electrically connected to each die pad 13 of the chip 11, as shown. Figure 1As shown in the figure; wherein a portion of each first connector 40 is disposed within each third opening 57, and each first connector 40 is electrically connected with each second line 58, as shown in the figure. Figure 1 As shown in the figure; wherein the chip 11 of the semiconductor memory packaging unit 1 is externally electrically connected in sequence via each bump 13, each via line 22, each first connector 40, each second line 58, each conductive pillar 59, and each first line 56, as shown in the figure. Figure 1
[0054] As shown in step S2, the redistribution layer 20 is horizontally formed on the surface of the chip 11 using redistribution layer technology (RDL). Since the redistribution layer 20 is easy to implement precisely, the process is simplified, which enables the redistribution layer 20 to extend and interact in the XY plane, and also enables the completed semiconductor memory packaging unit 1 to maintain or achieve a certain degree of lightness, thinness, and smallness.
[0055] Compared with the existing semiconductor memory packaging unit, the semiconductor memory packaging unit 1 of the utility model has the following advantages:
[0056] (1) Each bump 13 of the utility model is redistributed and externally connected by each via line 22 using redistribution layer technology (RDL). The arrangement design between the external connection (or solder pad) of each via line 22 is more diversified.
[0057] (2) The layout space of the lines on the chip package 10 is relatively flexible and easy to design, which enables the layout of the lines on the substrate 50 that needs to be electrically connected with the chip package 10 to be relatively flexible and easy to design, which is beneficial to reduce the cost of the manufacturing end because the lines connected are easy to design and manufacture.
[0058] (3) The layout of the lines on the chip package 10 is relatively flexible, and the lines can avoid being too dense, which makes the welding process more reliable and successful, which helps to improve the reliability and yield of the product, and is beneficial to increase the market competitiveness of the product.
[0059] The above is only the preferred embodiment of the utility model, which is only illustrative but not limiting for the utility model. Those skilled in the art understand that many changes, modifications, or even equivalent changes can be made within the spirit and scope of the utility model claims, but all will fall within the protection scope of the utility model.
Claims
1. An improved structure of a semiconductor memory package unit, characterized by comprising: The semiconductor memory package unit includes a chip package, a plurality of first connectors, and a substrate. The chip package, the plurality of first connectors, and the substrate form the semiconductor memory package unit. The chip package includes a chip and an insulating layer. The chip has a first surface with a plurality of pads. The insulating layer is on the chip and covers the chip. The insulating layer has a first surface and a plurality of first openings. Each of the first openings is configured to expose the plurality of pads of the chip. Each of the first connectors is partially disposed in each of the first openings and electrically connected to each of the pads of the chip. The substrate is disposed on the first surface of the insulating layer and each of the first connectors. The substrate has a first surface and an opposite second surface. The first surface of the substrate has a first outer layer with a plurality of second openings. Each of the second openings has a first circuit disposed therein. The second surface of the substrate has a second outer layer with a plurality of third openings. Each of the third openings has a second circuit disposed therein. Each of the first connectors is partially disposed in each of the third openings and electrically connected to each of the second circuits. Each of the first circuits and each of the second circuits has a conductive pillar disposed therebetween. Each of the conductive pillars is electrically connected to each of the first circuits and each of the second circuits. The semiconductor memory package unit further includes a redistribution layer disposed between the chip and the insulating layer and covered by the insulating layer. The redistribution layer has a dielectric layer and a plurality of conductive lines. The dielectric layer has a first surface corresponding to the first surface of the chip. The dielectric layer has a plurality of recesses configured to expose the plurality of pads of the chip. Each of the conductive lines is disposed in each of the recesses and electrically connected to the plurality of pads. Each of the conductive lines is made of metal. The chip of the semiconductor memory package unit is electrically connected to the outside in sequence via each of the pads, each of the conductive lines, each of the first connectors, each of the second circuits, each of the conductive pillars, and each of the first circuits. Each of the conductive lines exposed by each of the first openings is soldered to the outside by a solder ball. The solder ball is disposed in each of the first openings and each of the third openings after soldering to form each of the first connectors.
2. The semiconductor memory package cell of claim 1, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. The first circuit of each of the second openings of the substrate is soldered to the outside by a solder ball. The solder ball is disposed on the first circuit of each of the second openings after soldering to form a second connector.
3. The semiconductor memory package cell of claim 1, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. 4. The semiconductor memory package cell of claim 3, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. Each of the die pads has a thickness of 2 um; wherein the dielectric layer has a thickness of 10 um; wherein each of the via lines has a thickness of 10 um; wherein each of the first connectors has a thickness of 50 um; wherein the substrate has a thickness of 135 um; wherein the first outer protective layer has a thickness of 30 um; wherein the second outer protective layer has a thickness of 30 um; wherein the first lines have a thickness of 25 um; wherein the second lines have a thickness of 25 um; wherein each of the conductive posts has a thickness of 75 um; wherein each of the second connectors has a thickness of 350 um.
5. The semiconductor memory package cell of claim 1, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. Each of the via lines is made of silver metal material; wherein each of the first lines, each of the second lines, and each of the conductive posts is made of copper metal material.
6. The semiconductor memory package cell of claim 1, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. The semiconductor memory package unit is disposed on a printed circuit board.
7. The semiconductor memory package cell of claim 1, wherein the semiconductor memory package cell is a dynamic random access memory (DRAM) cell. The memory type of the semiconductor memory package unit includes dynamic random access memory, static random access memory, and synchronous dynamic random access memory.