SiC MOSFET gate driver
By introducing current feedback and gate regulation unit into the SiC MOSFET gate driver, the gate resistance is adjusted in real time, which solves the problem of increased turn-off rate and loss caused by overvoltage spike suppression in the prior art, and achieves overvoltage suppression effect with high turn-off rate and low loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-03-03
AI Technical Summary
Existing SiC MOSFET gate drivers, when suppressing overvoltage spikes, result in reduced turn-off rate and increased turn-off losses, limiting device reliability and switching frequency.
By employing a combination of a gate control unit, a current feedback unit, and a gate adjustment unit, the gate resistance is adjusted to suppress overvoltage spikes by real-time detection of the drain current change rate, thereby ensuring a high turn-off rate and low turn-off loss.
This technology effectively suppresses overvoltage spikes at high turn-off rates in SiC MOSFETs, while reducing turn-off losses and delay time, thereby improving device reliability and switching frequency.
Smart Images
Figure CN223967852U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a SiC MOSFET gate driver, belonging to the field of power electronics technology. Background Technology
[0002] SiC MOSFETs (SiC stands for silicon carbide, and MOSFET stands for metal-oxide-semiconductor field-effect transistor) are high-performance third-generation power semiconductor devices. Benefiting from their excellent high-temperature, high-voltage, low-loss, and high-switching-rate characteristics, they significantly improve the conversion efficiency and power density of power electronic systems. However, during the high-speed turn-off process of SiC MOSFETs, the high drain current drop rate generates excessively high voltage spikes, limiting the rated voltage application range of SiC MOSFETs and reducing device reliability.
[0003] Currently, gate drivers suppress overvoltage spikes by increasing the gate resistance. The principle is that increasing the gate resistance slows down the gate voltage drop, reduces the rate of drain current decrease, and consequently lowers the induced potential of the parasitic inductance in the current loop, thus suppressing overvoltage spikes in the SiC MOSFET. However, increasing the gate resistance reduces the overall turn-off rate of the SiC MOSFET, decreasing not only the rate of change of drain current but also the rate of change of drain voltage and increasing the turn-off delay time. This increases turn-off losses and limits the switching frequency of the SiC MOSFET.
[0004] Therefore, a new method is needed to realize a gate driver that can suppress overvoltage spikes under high turn-off rate and low turn-off loss of SiC MOSFET. Summary of the Invention
[0005] The purpose of this invention is to provide a SiC MOSFET gate driver for suppressing overvoltage spikes under high turn-off rate and low turn-off loss.
[0006] To achieve the above objectives, the technical solution of this utility model is as follows:
[0007] A SiC MOSFET gate driver includes a gate control unit, a current feedback unit, and a gate adjustment unit; wherein,
[0008] A gate control unit, the output of which is connected to the gate g of the SiC MOSFET under test, includes a push-pull amplifier, a gate turn-on resistor and a gate turn-off resistor, and is used to turn on and off the gate g of the SiC MOSFET by switching the drive voltage.
[0009] The current feedback unit is connected between the power source S of the SiC MOSFET under test and the input terminal of the gate adjustment unit. It is used to detect the rate of change of the drain current during the turn-off process in real time and to feed back the current change status to the gate adjustment unit according to the rate of change of the drain current.
[0010] The gate adjustment unit, connected in parallel between the input of the gate control unit and the gate turn-off resistor, is used to receive the current change status signal output by the current feedback unit. By increasing the gate resistance in the gate control unit during the drain current decrease, the turn-off rate of the SiC MOSFET under test is slowed down, the drain current decrease rate is reduced, and thus the turn-off overvoltage spike is suppressed.
[0011] In some embodiments, the gate adjustment unit includes an OR gate, an amplifier DRIVE2, and a transistor Q3; one input terminal of the OR gate is connected to an input voltage Vp, the other input terminal of the OR gate is connected to a gate control unit, and the output terminal of the OR gate is connected to an input terminal of the amplifier DRIVE2; the output terminal of the amplifier DRIVE2 is connected to the base of the transistor Q3; and the collector of the transistor Q3 is connected to a drive voltage Vp. EE The emitter of transistor Q3 is connected to the gate control unit.
[0012] In some embodiments, the current feedback unit includes a resistor R. p Capacitor C p diode D p And comparator OP;
[0013] Capacitor C p One end of capacitor C is grounded; p The other end is connected to diode D p anode, resistance R p One end is connected; resistor R p The other end input voltage V Ss The cathode of diode Dp is connected to the positive input terminal of comparator OP, and the negative input terminal of comparator OP is connected to the reference voltage V. ref The comparator OP output voltage V t .
[0014] In some embodiments, the gate control unit includes amplifier DRIVE1, transistor Q1, transistor Q2, diode D1, and gate resistor R. g1 Gate resistance R g2 and gate resistance R g3 ;
[0015] The input voltage V at the input terminal of amplifier DRIVE1 PWMThe output of amplifier DRIVE1 is connected to the base of transistors Q1 and Q2; the collector of transistor Q1 is connected to the power supply voltage V. DD The collector connection drive voltage V of transistor Q2 EE The emitter of transistor Q1 and the emitter of transistor Q2, the anode of diode D1, and the gate resistor R g3 One end of diode D1 is connected to the gate resistor R; the cathode of diode D1 is connected to the gate resistor R. g1 One end is connected; gate resistor R g3 The other end is connected to the gate resistor R g2 One end is connected to the emitter of transistor Q3 in the gate adjustment unit; the gate resistor R g1 The other end is connected to the gate resistor R g2 The other end is connected to the gate g of the SiC MOSFET under test.
[0016] In some embodiments, the OR gate uses an SN74LVC1G32 chip, and the DRIVE2 amplifier uses an MCP1416 chip.
[0017] In some embodiments, the SiC MOSFET under test has a Kelvin-type structure with a parasitic inductance L between the auxiliary source S and the power source S. Ss .
[0018] In some embodiments, the current feedback unit is further configured to, when the drain current I D After dropping to zero, when high-frequency oscillation occurs, the current passes through resistor R. p and capacitor C p Filtering to remove high-frequency oscillations.
[0019] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0020] This invention suppresses overvoltage spikes by reducing the rate of decrease of drain current through current feedback, without changing the turn-off delay time or the rate of change of drain voltage. It can achieve overvoltage spike suppression under high turn-off rate and low turn-off loss of SiC MOSFET. Attached Figure Description
[0021] The accompanying drawings, as part of this utility model, are used to provide a further understanding of the present utility model. The illustrative embodiments and descriptions of the present utility model are used to explain the present utility model, but do not constitute an undue limitation of the present utility model. Obviously, the drawings described below are merely some embodiments; those skilled in the art can obtain other drawings based on these drawings without creative effort. In the drawings:
[0022] Figure 1 A circuit diagram of one embodiment of conventional gate drive;
[0023] Figure 2 This is a schematic diagram of a SiC MOSFET dual-pulse test circuit.
[0024] Figure 3 This is a schematic diagram of the turn-off transient process of a SiC MOSFET.
[0025] Figure 4 The transient waveform of SiC MOSFET turn-off controlled by a conventional gate driver;
[0026] Figure 5 A circuit diagram of one embodiment of adding a gate resistor to a conventional gate driver;
[0027] Figure 6 The turn-off transient waveform of a SiC MOSFET is controlled by adding a gate resistor to a conventional gate driver;
[0028] Figure 7 This is a circuit diagram of one embodiment of the gate driver of this utility model;
[0029] Figure 8 This invention relates to the gate driver controlling the turn-off transient waveform of a SiC MOSFET.
[0030] Figure labels: 10-SiC MOSFET under test, 20-Gate control unit, 30-Gate adjustment unit, 40-Current feedback unit.
[0031] It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but rather to illustrate the concept of the present invention to those skilled in the art by referring to specific embodiments. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings. The following embodiments are used to illustrate this utility model, but are not intended to limit the scope of this utility model.
[0033] Existing Example 1:
[0034] This embodiment provides a conventional gate drive circuit, such as Figure 1 As shown, it includes amplifier DRIVE1, transistors Q1 and Q2, diode D1, and gate resistor R. g1 and R g2 .
[0035] Among them, the input voltage V at the input terminal of amplifier DRIVE1 PWMThe output of amplifier DRIVE1 is connected to the base of transistors Q1 and Q2; the collector of transistor Q1 is connected to the power supply voltage V. DD The collector connection drive voltage V of transistor Q2 EE The emitter of transistor Q1 and the emitter of transistor Q2, the anode of diode D1, and the gate resistor R g2 One end of diode D1 is connected to the gate resistor R; the cathode of diode D1 is connected to the gate resistor R. g1 One end is connected; gate resistor R g1 The other end is connected to the gate resistor R g2 The other end is connected.
[0036] The control principle of a conventional driver is: when the switching signal V PWM When the voltage is high, driver DRIVE1 turns on transistor Q1, and gate current flows through diode D1 and gate resistor R. g1 and gate resistance R g2 Turn on the SiC MOSFET when the switching signal V PWM When the voltage is low, driver DRIVE1 turns on transistor Q2, and gate current flows through gate resistor R. g2 Turn off the SiC MOSFET.
[0037] The dual-pulse test method was used to verify the gate driver's control over the switching characteristics of the SiC MOSFET. Figure 2 This is a test circuit for the switching characteristics of SiC MOSFETs, including a DC power supply V. dc Parasitic inductance Lstry, freewheeling diode Dsic, load inductance Lload, SiC MOSFET under test, gate driver.
[0038] In this configuration, the gate driver is connected to the gate of the SiC MOSFET under test; the drain C of the SiC MOSFET is connected to the anode of the freewheeling diode Dsic and the load inductor L. load One end is connected; freewheeling diode D sic Cathode and load inductance L load At the other end, parasitic inductance L stry One end is connected; parasitic inductance L stry The other end is connected to the DC power supply V dc The positive terminal is connected; DC power supply V dc The negative terminal is connected to the source S of the SiC MOSFET.
[0039] The turn-off transient of SiC MOSFET is divided into three stages. Figure 3This is a schematic diagram of the turn-off transient. S1 is the turn-off delay stage, S2 is the stage where the drain voltage rises rapidly, and S3 is the stage where the drain current falls rapidly. The total time of the turn-off transient is the sum of the times from S1 to S3.
[0040] S1 stage: When the gate driver receives V PWM When the gate voltage is low (i.e., the turn-off signal), the gate voltage begins to decrease. At this time, the drain current remains constant, and the drain voltage V0 remains constant. DS The voltage gradually increases until it reaches 10% of the bus voltage, at which point this stage ends and the next stage begins.
[0041] S2 stage: Drain voltage V DS It begins to rise rapidly until it reaches 90% of the bus voltage, at which point this stage ends and the next stage begins, while the drain current remains unchanged.
[0042] In phase S3, when the drain voltage V DS Rise to bus voltage V dc After that, the drain current I D It begins to descend rapidly, parasitic inductance L stry Induced potential V stry Therefore, the drain voltage V of the SiC MOSFET DS for
[0043] V DS =V dc +V stry
[0044] The drain voltage V during phase S3 DS This causes a voltage overshoot.
[0045] Simulation analysis was performed by setting the parameters of the dual-pulse test circuit and the gate resistor. The simulation parameters are as follows: L stry 50nH, L load 100μH, bus power supply V dc 600V, R g2 It is 10Ω.
[0046] Figure 4 The transient waveform of turn-off under conventional gate drive is shown. It can be seen that the times for each stage are S1 276ns, S2 58ns, S3 76ns, and the overvoltage spike V... DS The voltage is 1158V, and the turn-off loss is E. off It is 24 mJ.
[0047] Existing Example 2:
[0048] Overvoltage spikes are suppressed by increasing the gate resistance. The gate control unit structure is as follows: Figure 5 As shown, with gate resistance Rg2 A resistor R is connected in series g3 .
[0049] Gate resistor R g3 Set to 10Ω, Figure 6 The simulation waveforms for the turn-off transient when the gate resistance is increased using a conventional gate drive are shown. It can be seen that the times for each stage are S1 (524 ns), S2 (102 ns), and S3 (104 ns), with the overvoltage spike V... DS The voltage is 988V, and the turn-off loss is E. off It is 46 mJ. (Comparison) Figure 4 and Figure 6 The results showed that although increasing the gate resistance could reduce the overvoltage spike V DS However, the turn-off loss increased by 1.9 times, and the total turn-off time increased by 320 ns.
[0050] Example of this application:
[0051] According to an embodiment of the present invention, a SiC MOSFET gate driver is provided, such as... Figure 7 As shown, it includes a gate control unit 20, a current feedback unit 40, and a gate adjustment unit 30; wherein,
[0052] The gate control unit 20 has its output terminal connected to the gate g of the SiC MOSFET 10 under test. The gate control unit 20 includes a push-pull amplifier, a gate turn-on resistor, and a gate turn-off resistor, and is used to turn on and off the gate g of the SiC MOSFET by switching the drive voltage.
[0053] The current feedback unit 40 is connected between the power source S of the SiC MOSFET 10 under test and the input terminal of the gate adjustment unit. It is used to detect the rate of change of the drain current during the turn-off process in real time and to feed back the current change status to the gate adjustment unit according to the rate of change of the drain current.
[0054] The gate adjustment unit 30 is connected in parallel between the input terminal of the gate control unit and the gate turn-off resistor. It is used to receive the current change status signal output by the current feedback unit. By increasing the gate resistance in the gate control unit during the drain current decrease, the turn-off rate of the SiC MOSFET10 under test is slowed down, the drain current decrease rate is reduced, and the turn-off overvoltage spike is suppressed.
[0055] The overvoltage suppression process of this invention is as follows: the current feedback unit 40 acquires the state of the drain current change during the turn-off transient of the SiC MOSFET in real time; the gate adjustment unit 30 adjusts the gate turn-off resistor in the gate controller during the drain current change; the change of the gate turn-off resistor of the gate controller changes the rate of change of the SiC MOSFET current, thereby suppressing the overvoltage spike.
[0056] Furthermore, refer to Figure 7 As shown, the current feedback unit 40 includes a resistor R p Capacitor C p diode D p And comparator OP. Where: capacitor C p One end of capacitor C is grounded; p The other end is connected to diode D p anode, resistance R p One end is connected; resistor R p The other end input voltage V Ss The cathode of diode Dp is connected to the positive input terminal of comparator OP, and the negative input terminal of comparator OP is connected to the reference voltage V. ref The comparator OP output voltage V t .
[0057] The gate adjustment unit 30 includes an OR gate, an amplifier DRIVE2, and a transistor Q3.
[0058] One input of an OR gate receives a voltage V. t The other input of the OR gate receives the switch signal V. pwm The output of the OR gate is connected to the input of amplifier DRIVE2; the output of amplifier DRIVE2 is connected to the base of transistor Q3; the collector of transistor Q3 is connected to the drive voltage V. EE The emitter of transistor Q3 is connected to the gate control unit.
[0059] In the preferred embodiment, the OR gate can be made of the SN74LVC1G32 chip, and the amplifiers DRIVE1 and DRIVE2 can be made of the MCP1416 chip.
[0060] Furthermore, the SiC MOSFET under test has a Kelvin-type structure, with a parasitic inductance L between the auxiliary source (s) and the power source (S). Ss The parasitic inductance L of the SiC MOSFET under test when drain current flows is... Ss A reverse potential V will be induced. Ss .
[0061] In an optional embodiment, the current feedback unit is further configured to, when the drain current I DAfter dropping to zero, when high-frequency oscillation occurs, the current passes through resistor R. p and capacitor C p Filtering to remove high-frequency oscillations.
[0062] Continue to combine Figure 7 The specific process of the gate driver proposed in this invention for suppressing transient overvoltage during SiC MOSFET turn-off is as follows:
[0063] The PWM signal V received by the gate driver PWM When the signal is low (i.e., a shutdown signal), transistor Q1 is turned off, and transistor Q2 is turned on. The SiC MOSFET under test enters the shutdown transient state, and the drain current I... D When no abrupt change occurs, the parasitic inductance L Ss Induced electromotive force V Ss The current feedback unit output voltage V is zero. p The voltage level is zero, so it passes through the OR gate and amplifier DRIVE2, turning on transistor Q3. The gate current of the SiC MOSFET then flows through the gate resistor R. g3 With transistor Q3, the turn-off rate of SiC MOSFET is accelerated;
[0064] Subsequently, when the drain current I D During rapid descent, parasitic inductance L Ss Induced electromotive force V Ss The current feedback unit outputs a positive voltage, V. p When the signal is high, it passes through the OR gate and amplifier DRIVE2, turning off transistor Q3. The gate current of the SiC MOSFET then flows through the gate resistor R. g2 Gate resistance R g3 With transistor Q3, the SiC MOSFET's turn-off rate is reduced, lowering the drain current I. D The rate of decrease of the voltage drop, thereby suppressing the shutdown overvoltage spike;
[0065] When the drain current I D After dropping to zero, high-frequency oscillations will occur, at which point the parasitic inductance L... Ss Induced electromotive force V Ss After passing through resistor R p and capacitor C p After filtering to remove high-frequency oscillations, the current feedback unit outputs voltage V. p When the voltage level is zero, transistor Q3 is turned on, and the turn-off rate of the SiC MOSFET is accelerated.
[0066] Figure 8The following is a simulation waveform of the turn-off transient using the gate driver of this invention. The reference level Vref is set to 2V. It can be seen that the times for each stage are S1 276ns, S2 58ns, S3 102ns, and the overvoltage spike V... DS The voltage is 986V, and the turn-off loss is E. off It is 27 mJ. (Comparison) Figure 8 and Figure 4 The results showed that the method of this invention can also reduce the overpressure peak V. DS Furthermore, the increase in turn-off loss was only 3 mJ, and the total turn-off time only increased by 26 ns in stage S3. Compared to Figure 6 The simulation results show that the turn-off loss was reduced by 73 mJ and the total turn-off time was reduced by 294 ns.
[0067] In summary, this invention provides a SiC MOSFET gate driver, in which the gate adjustment unit is used to adjust the gate resistance only during the current decrease process. During the rapid decrease of the transient drain current during SiC MOSFET turn-off, this solution increases the gate turn-off resistance by feeding back the current state signal generated during this phase, thereby suppressing overvoltage spikes. This solution can effectively suppress overvoltage spikes even at high turn-off rates of SiC MOSFETs.
[0068] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0069] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features found in other embodiments but not others, combinations of features from different embodiments are also within the scope of protection of this invention and form different embodiments. For example, in the embodiments described above, those skilled in the art can use them in combination based on known technical solutions and the technical problems to be solved by this application.
[0070] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.
Claims
1. A SiC MOSFET gate driver, characterized in that, It includes a gate control unit, a current feedback unit, and a gate adjustment unit; among which, The gate control unit, whose output terminal is connected to the gate g of the SiC MOSFET under test, includes a push-pull amplifier, a gate turn-on resistor, and a gate turn-off resistor, and is used to turn on and off the gate g of the SiC MOSFET by switching the drive voltage. The current feedback unit is connected between the power source S of the SiC MOSFET under test and the input terminal of the gate adjustment unit. It is used to detect the rate of change of the drain current during the turn-off process in real time and to feed back the current change status to the gate adjustment unit according to the rate of change of the drain current. The gate adjustment unit, connected in parallel between the input of the gate control unit and the gate turn-off resistor, is used to receive the current change status signal output by the current feedback unit. By increasing the gate resistance in the gate control unit during the drain current decrease, the turn-off rate of the SiC MOSFET under test is slowed down, the drain current decrease rate is reduced, and thus the turn-off overvoltage spike is suppressed.
2. A SiC MOSFET gate driver according to claim 1, characterized in that: The gate adjustment unit includes an OR gate, an amplifier DRIVE2, and a transistor Q3; One input of the OR gate is connected to the input voltage Vp, and the other input is connected to the gate control unit. The output of the OR gate is connected to the input of amplifier DRIVE2. The output of amplifier DRIVE2 is connected to the base of transistor Q3. The collector of transistor Q3 is connected to the drive voltage Vp. EE The emitter of transistor Q3 is connected to the gate control unit.
3. A SiC MOSFET gate driver according to claim 2, characterized in that: The current feedback unit includes a resistor R. p Capacitor C p diode D p And comparator OP; Capacitor C p One end of capacitor C is grounded; p The other end is connected to diode D p anode, resistance R p One end is connected; resistor R p The other end input voltage V Ss The cathode of diode Dp is connected to the positive input terminal of comparator OP, and the negative input terminal of comparator OP is connected to the reference voltage V. ref The comparator OP output voltage V t .
4. A SiC MOSFET gate driver according to claim 1, characterized in that: The gate control unit includes amplifier DRIVE1, transistor Q1, transistor Q2, diode D1, and gate resistor R. g1 Gate resistance R g2 and gate resistance R g3 ; The input voltage V at the input terminal of amplifier DRIVE1 PWM The output of amplifier DRIVE1 is connected to the base of transistors Q1 and Q2; the collector of transistor Q1 is connected to the power supply voltage V. DD The collector connection drive voltage V of transistor Q2 EE The emitter of transistor Q1 and the emitter of transistor Q2, the anode of diode D1, and the gate resistor R g3 One end of diode D1 is connected to the gate resistor R; the cathode of diode D1 is connected to the gate resistor R. g1 One end is connected; gate resistor R g3 The other end is connected to the gate resistor R g2 One end is connected to the emitter of transistor Q3 in the gate adjustment unit; the gate resistor R g1 The other end is connected to the gate resistor R g2 The other end is connected to the gate g of the SiC MOSFET under test.
5. A SiC MOSFET gate driver according to claim 2, characterized in that: The OR gate uses the SN74LVC1G32 chip, and the DRIVE2 amplifier uses the MCP1416 chip.
6. A SiC MOSFET gate driver according to claim 1, characterized in that: The SiC MOSFET under test has a Kelvin-type structure and a parasitic inductance L between the auxiliary source (s) and the power source (S). Ss .
7. A SiC MOSFET gate driver according to claim 1 or 6, characterized in that: The current feedback unit is also used when the drain current I D After dropping to zero, when high-frequency oscillation occurs, the current passes through resistor R. p and capacitor C p Filtering to remove high-frequency oscillations.