Dead zone insertion circuit based on gate-level circuit

Abstract

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

Description

Technical Field

[0001] This utility model relates to the field of gate-level circuit technology, and in particular to a dead-time insertion circuit. Background Technology

[0002] Dead time refers to the time period during which the output signal cannot respond or react promptly when the input signal in a circuit changes. Dead time phenomena commonly occur in sequential circuits, especially digital circuits. For example, during the rising or falling edge of a clock signal, if the rate of change of the input signal in the circuit is too fast, or during the transition period of the input signal, some gate circuits may not respond quickly enough, resulting in an unstable output and the formation of a dead time.

[0003] In existing technologies, dead-time insertion circuits are implemented based on delay circuits or specific clock synchronization mechanisms. However, dead-time insertion circuit design usually relies on multiple clock and gate circuit combinations, requiring meticulous debugging and highly complex design, which increases the design difficulty. In addition, traditional dead-time insertion circuits use a lot of resistors and capacitors, resulting in relatively high costs in practical applications. Utility Model Content

[0004] The purpose of this invention is to provide a dead-time insertion circuit based on gate-level circuits to solve the above-mentioned technical problems.

[0005] A dead-time insertion circuit based on gate-level circuitry includes,

[0006] A first NAND gate, the first input of the first NAND gate is connected to a first complementary signal;

[0007] The first NOT gate, the input of the first NOT gate is connected to the first input of the first NAND gate;

[0008] A first RC circuit is connected to the output terminal of the first NOT gate through a first resistor.

[0009] The second NAND gate has its first input terminal connected to a second complementary signal, and its second input terminal connected to the first RC circuit via a second resistor.

[0010] The second NOT gate, the input of the second NOT gate is connected to the first input of the second NAND gate;

[0011] The second RC circuit is connected to the output of the second NOT gate through a third resistor.

[0012] The fourth resistor has its first end connected to the second input terminal of the first NAND gate, and its second end connected between the third resistor and the second RC circuit.

[0013] Preferably, the first resistor-capacitor circuit includes,

[0014] The fifth resistor, wherein the first end of the fifth resistor is connected to the first end of the first resistor;

[0015] A first capacitor, the first end of which is connected to the second end of the fifth resistor, and the second end of the first capacitor is grounded.

[0016] Preferably, the second resistor-capacitor circuit includes,

[0017] A sixth resistor, the first end of which is connected to the second end of the fourth resistor;

[0018] The second capacitor has its first terminal connected to the second terminal of the sixth resistor, and its second terminal grounded.

[0019] Preferably, it also includes,

[0020] The first diode has its anode connected to the first terminal of the second resistor, and its cathode connected to the output terminal of the first NOT gate.

[0021] Preferably, it also includes,

[0022] The second diode has its anode connected to the first terminal of the sixth resistor and its cathode connected to the output terminal of the second NOT gate.

[0023] Preferably, the formula for the voltage change with time in the first RC circuit is:

[0024]

[0025] Among them, V t1 This represents the voltage across the first capacitor at time t1;

[0026] V u1 Indicates the voltage of the first charging power supply;

[0027] R5 represents the resistance value of the fifth resistor;

[0028] C1 represents the capacitance value of the first capacitor.

[0029] Preferably, the formula for the voltage change over time in the second RC circuit is:

[0030]

[0031] Among them, V t2 This represents the voltage across the second capacitor at time t2;

[0032] V u2 Indicates the voltage of the second charging power supply;

[0033] R6 represents the resistance value of the sixth resistor;

[0034] C2 represents the capacitance value of the second capacitor.

[0035] Preferably, the waveform signal at the output of the second NAND gate lags behind the first complementary signal at the falling edge by a time that is the dead time.

[0036] Preferably, the time by which the waveform signal at the output of the first NAND gate lags behind the second complementary signal at the falling edge is the dead time.

[0037] Preferably, the level states of the first complementary signal and the second complementary signal are opposite.

[0038] The beneficial effects of this utility model are: through the cooperation between NAND gates, NOT gates and RC circuits, the circuit structure is simple, the safety and reliability of the circuit operation are improved, and the cost is low. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the dead-time insertion circuit based on gate-level circuits of this utility model. Detailed Implementation

[0040] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0043] A dead-time insertion circuit based on gate-level circuits, such as Figure 1 As shown, including,

[0044] The first NAND gate U1, the first input terminal of the first NAND gate U1 is connected to the first complementary signal;

[0045] The input of the first NOT gate U2 is connected to the first input of the first NAND gate U1;

[0046] The first RC circuit is connected to the output terminal of the first NOT gate U2 through the first resistor R1.

[0047] The second NAND gate U3 has its first input terminal connected to the second complementary signal, and its second input terminal connected to the first RC circuit RC1 through the second resistor R2.

[0048] The input of the second NOT gate U4 is connected to the first input of the second NAND gate U3;

[0049] The second RC circuit is connected to the output terminal of the second NOT gate U4 through the third resistor R3.

[0050] The fourth resistor R4 has its first end connected to the second input terminal of the first NAND gate U1, and its second end connected between the third resistor R3 and the second RC circuit RC2.

[0051] Specifically, this utility model provides a dead-time insertion circuit based on gate-level circuits. The first input terminal of the first NAND gate U1 is ULI in the figure, the first input terminal of the second NAND gate U3 is UHI in the figure, and the output terminal of the first NAND gate U1 is... Figure 1 In the UHO, the output of the second NAND gate U3 is Figure 1 The ULO in the circuit receives complementary signals from the first input terminal of the first NAND gate U1 and the first input terminal of the second NAND gate U3, and outputs complementary signals with dead-time insertion from the output terminals of the first NAND gate U1 and the second NAND gate U3. "UH" is the high-side signal and "UL" is the low-side signal. It consists of two NAND gates, two NOT gates, and RC circuits. The circuit structure is simple, which improves the safety and reliability of the circuit operation and has low cost.

[0052] In a preferred embodiment, the first resistor-capacitor circuit RC1 includes,

[0053] The fifth resistor R5 is connected to the first terminal of the first resistor R1.

[0054] The first capacitor C1 has its first terminal connected to the second terminal of the fifth resistor R5, and its second terminal is grounded.

[0055] Specifically, after the low-side signal is input from ULI, it passes through the first NAND gate U1, then through the first NOT gate U2 and is output to the first RC circuit RC1, then through the second resistor R2 and input to the second NAND gate U3, and the ULO output waveform.

[0056] When ULI is high, the output of the first NOT gate U2 is low, the input of the second NAND gate U3 is low, and the output of ULO is high. When ULI is low, the output of the first NOT gate U2 is high, charging the first capacitor C1. After it is fully charged, after a delay, the output of the second NAND gate U3 is low.

[0057] In a preferred embodiment, the second resistor-capacitor circuit RC2 includes,

[0058] The sixth resistor R6 has its first end connected to the second end of the fourth resistor R4.

[0059] The second capacitor C2 has its first terminal connected to the second terminal of the sixth resistor R6, and its second terminal grounded.

[0060] Specifically, after the high-side signal is input from UHI, it passes through the second NAND gate U3, then through the second NOT gate U4 and is output to the second RC circuit RC2. After passing through the second NOT gate U4, it is input to the first NAND gate U1, and the UHO output waveform is obtained.

[0061] When UHI is high, the output of the second NOT gate U4 is low, the input of the first NAND gate U1 is low, and the output of UHO is high. When UHI is low, the output of the second NOT gate U4 is high, charging the second capacitor C2. After it is fully charged, after a delay, the output of the first NAND gate U1 is low.

[0062] In a preferred embodiment, it further includes,

[0063] The anode of the first diode D1 is connected to the first terminal of the second resistor R2, and the cathode of the first diode D1 is connected to the output terminal of the first NOT gate U2.

[0064] It also includes,

[0065] The anode of the second diode D2 is connected to the first terminal of the sixth resistor R6, and the cathode of the second diode D2 is connected to the output terminal of the second NOT gate U4.

[0066] Specifically, both the first diode D1 and the second diode D2 are used to provide a discharge circuit for the charging circuit (the first RC circuit RC1 and the second RC circuit RC2).

[0067] In a preferred embodiment, the formula for the voltage change over time in the first RC circuit RC1 is:

[0068]

[0069] Among them, V t1 This represents the voltage across the first capacitor C1 at time t1;

[0070] Vu1 Indicates the voltage of the first charging power supply;

[0071] R5 represents the resistance value of the fifth resistor R5;

[0072] C1 represents the capacitance value of the first capacitor C1;

[0073] e represents the natural constant;

[0074] The formula for the voltage change with time in the second RC circuit RC2 is:

[0075]

[0076] Among them, V t2 This represents the voltage across the second capacitor C2 at time t2;

[0077] V u2 Indicates the voltage of the second charging power supply;

[0078] R6 represents the resistance value of the sixth resistor R6;

[0079] C2 represents the capacitance value of the second capacitor C2;

[0080] e represents the natural constant.

[0081] Specifically, the delay time can be calculated using the formula above. Based on the principle of a first-order charging circuit, the dead time can be calculated. By selecting appropriate resistor and capacitor values, the dead time can be precisely controlled. Furthermore, the first diode D1 and the second diode D2 provide a discharge path for the charging circuit, ensuring stable and reliable circuit operation. The dead time can be flexibly adjusted to meet different requirements.

[0082] In a preferred embodiment, the waveform signal at the output of the second NAND gate U3 lags behind the first complementary signal at the falling edge by a time that is the dead time.

[0083] The time that the waveform signal at the output of the first NAND gate U1 lags behind the second complementary signal at the falling edge is called the dead time.

[0084] The first complementary signal and the second complementary signal have opposite level states.

[0085] Specifically, in sequential circuits, especially when using logic gates for timing control, the introduction of dead time helps prevent race conditions. Race conditions refer to situations where signals are simultaneously in inconsistent states or alternating states, leading to unpredictable circuit behavior. By setting dead time, the transitions between signals can be ensured to be ordered, avoiding race conditions.

[0086] Dead time provides a buffer period for signal transitions, helping to stabilize circuit timing and improve the circuit's tolerance to signal noise.

[0087] The hardware dead-time insertion circuit of this invention consists of 2 NAND gates, 2 NOT gates, 2 diodes, 6 resistors, and 2 capacitors. The peripheral circuit is simple, the cost is low, and the hardware is mature and stable.

[0088] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A dead-time insertion circuit based on gate-level circuits, characterized in that, include, The first NAND gate (U1) has its first input connected to a first complementary signal; The first NOT gate (U2) is connected to the first input of the first NAND gate (U1); The first RC circuit (RC1) is connected to the output terminal of the first NOT gate (U2) through the first resistor (R1); The second NAND gate (U3) has its first input terminal connected to the second complementary signal, and its second input terminal connected to the first RC circuit (RC1) through the second resistor (R2). The second NOT gate (U4) has its input connected to the first input of the second NAND gate (U3); The second RC circuit (RC2) is connected to the output terminal of the second NOT gate (U4) through the third resistor (R3); The fourth resistor (R4) has its first end connected to the second input terminal of the first NAND gate (U1), and its second end connected between the third resistor (R3) and the second RC circuit (RC2).

2. The dead-time insertion circuit based on gate-level circuits according to claim 1, characterized in that, The first resistor-capacitor circuit (RC1) includes, The fifth resistor (R5) has its first end connected to the first end of the first resistor (R1); The first capacitor (C1) has its first terminal connected to the second terminal of the fifth resistor (R5), and its second terminal is grounded.

3. The dead-time insertion circuit based on gate-level circuits according to claim 1, characterized in that, The second resistor-capacitor circuit (RC2) includes, The sixth resistor (R6) has its first end connected to the second end of the fourth resistor (R4); The second capacitor (C2) has its first terminal connected to the second terminal of the sixth resistor (R6), and its second terminal grounded.

4. The dead-time insertion circuit based on gate-level circuits according to claim 3, characterized in that, It also includes, The first diode (D1) has its anode connected to the first terminal of the second resistor (R2), and its cathode connected to the output terminal of the first NOT gate (U2).

5. The dead-time insertion circuit based on gate-level circuits according to claim 4, characterized in that, It also includes, The second diode (D2) has its anode connected to the first terminal of the sixth resistor (R6), and its cathode connected to the output terminal of the second NOT gate (U4).

6. The dead-time insertion circuit based on gate-level circuits according to claim 2, characterized in that, The formula for the voltage change over time in the first RC circuit (RC1) is as follows: Among them, V t1 This represents the voltage across the first capacitor (C1) at time t1; V u1 Indicates the voltage of the first charging power supply; R5 represents the resistance value of the fifth resistor (R5); C1 represents the capacitance value of the first capacitor (C1).

7. The dead-time insertion circuit based on gate-level circuits according to claim 3, characterized in that, The formula for the voltage change with time in the second RC circuit (RC2) is as follows: Among them, V t2 This represents the voltage across the second capacitor (C2) at time t2; V u2 Indicates the voltage of the second charging power supply; R6 represents the resistance value of the sixth resistor (R6); C2 represents the capacitance value of the second capacitor (C2).

8. The dead-time insertion circuit based on gate-level circuits according to claim 1, characterized in that, The waveform signal at the output of the second NAND gate (U3) lags behind the first complementary signal at the falling edge by a time called the dead time.

9. The dead-time insertion circuit based on gate-level circuits according to claim 8, characterized in that, The time that the waveform signal at the output of the first NAND gate (U1) lags behind the second complementary signal at the falling edge is the dead time.

10. The dead-time insertion circuit based on gate-level circuits according to claim 1, characterized in that, The first complementary signal has the opposite level to the second complementary signal.

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