Double-gate radio frequency switch device

Abstract

The utility model discloses a double-gate radio frequency switch device, and relates to the technical field of radio frequency switches. The SOI device comprises a substrate layer, a buried oxide layer and a device layer of an SOI wafer, the device layer comprises a source end, a drain end, a body end I, a body end II, a gate end I and a gate end II; the source end and the drain end are distributed on the two sides of the single NMOS switching device; the body end I, the body end II, the gate end I and the gate end II are distributed between the source end and the drain end; the gate end I is distributed at the upper part of the body end I; and the gate end II is distributed on the body end II. According to the scheme of the double-gate NMOS switch device designed based on the SOI process, the layout area of a radio frequency switch chip can be effectively reduced, the radio frequency layout area can be reduced by 30% to 35% under the condition of the same design index, the chip cost is effectively reduced, and the competitiveness of the chip is improved. Meanwhile, the conduction impedance of the double-gate NMOS switching device is obviously reduced, and the low-frequency insertion loss performance of the radio frequency switching circuit is effectively improved.

Description

Technical Field

[0001] This utility model belongs to the field of radio frequency switch technology, and in particular relates to a dual-gate radio frequency switch device. Background Technology

[0002] With the continuous development of wireless mobile communication technology, radio frequency switches are playing an increasingly important role in multi-band front-end modules and antenna tuners; especially in the multi-scenario application of antenna tuners, the application of small-size antenna tuners is gradually becoming a new industry trend.

[0003] Taking the industry-standard SP4T antenna tuner as an example, its package size has been continuously decreasing, from 1.5mm*1.5mm to 1.5mm*1.1mm, and then to 1.3mm*0.95mm. This shrinking package size has brought significant challenges to chip design. The SOI process node determines the area limit of the chip layout. To overcome this limit at the design level, new solutions must be used in the layout design of switching devices. This invention's dual-gate NMOS switching device solution based on SOI technology can effectively reduce the layout area of ​​RF switching chips—by 30% to 35% under the same design specifications—effectively reducing chip costs and enhancing chip competitiveness. Simultaneously, the on-resistance of the dual-gate NMOS switching device is significantly reduced, effectively improving the low-frequency insertion loss performance of the RF switching circuit. Utility Model Content

[0004] This invention provides a dual-gate RF switch device. Compared to existing single-gate NMOS switches, the number of gate terminals and body terminals is changed from one to two, resulting in a 15% to 20% increase in the overall layout area compared to single-gate NMOS switches. Simultaneously, the voltage withstand capability of the dual-gate NMOS switch is twice that of the single-gate NMOS switch, thus reducing the number of dual-gate NMOS switches used by half under the same voltage withstand conditions, resulting in a 30% to 35% reduction in overall area. Compared to single-gate NMOS switches, the normalized on-resistance of the dual-gate NMOS switch is 5% lower in practical designs. In summary, this invention solves the problem of the large layout area of ​​traditional single-gate NMOS switches.

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0006] This utility model discloses a dual-gate radio frequency switch device, comprising a substrate layer, a buried oxide layer, and a device layer of an SOI wafer.

[0007] The device layer includes a source terminal, a drain terminal, a body terminal one, a body terminal two, a gate terminal one, and a gate terminal two;

[0008] The source and drain terminals are located on both sides of a single NMOS switching device;

[0009] The body terminal one, body terminal two, gate terminal one, and gate terminal two are distributed in the middle of the source terminal and the drain terminal, and the ports of body terminal one, body terminal two, gate terminal one, and gate terminal two correspond one-to-one.

[0010] The first gate end is located on the upper part of the first body end; the second gate end is located on the upper part of the second body end.

[0011] Furthermore, a gap is provided between the first gate and the second gate, and the gap can be adjusted and optimized at the design level according to the specific rules of the process.

[0012] The present invention has the following advantages over the prior art:

[0013] (1) Compared with the planar schematic diagram of the dual-gate NMOS switching device based on SOI technology in this utility model, the gate terminal is changed from one to two, and the body terminal is changed from one to two. Therefore, the overall layout area of ​​the dual-gate NMOS switching device will increase by 15% to 20% compared with the layout area of ​​the single-gate NMOS switching device.

[0014] (2) The withstand voltage capability of dual-gate NMOS switching devices is twice that of single-gate NMOS switching devices. Therefore, under the same withstand voltage conditions, the number of dual-gate NMOS switching devices used can be reduced by half, and the overall area will be reduced by 30% to 35%.

[0015] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a cross-sectional schematic diagram of a single-gate NMOS switching device based on the SOI process in the prior art;

[0018] Figure 2 This is a cross-sectional schematic diagram of the dual-gate NMOS switching device based on SOI technology according to this utility model;

[0019] Figure 3 This is a planar schematic diagram of a single-gate NMOS switching device based on the SOI process in the prior art;

[0020] Figure 4 This is a planar schematic diagram of the dual-gate NMOS switching device based on SOI technology according to this utility model;

[0021] Figure 5 This is an equivalent relationship diagram showing the breakdown voltage performance of dual-gate and single-gate NMOS switching devices under the same breakdown voltage conditions;

[0022] The attached diagram lists the components represented by each number as follows:

[0023] B - Body terminal, B1 - Body terminal one, B2 - Body terminal two, G - Gate terminal, G1 - Gate terminal one, G2 - Gate terminal two, D - Drain terminal, S - Source terminal. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0025] In the description of this utility model, it should be understood that the terms "both sides", "middle", "port", "spacing", etc., which indicate orientation or positional relationship, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0026] like Figure 2 , Figure 4 As shown in the schematic cross-sectional view, the dual-gate NMOS switching device based on SOI technology of this invention mainly includes three layers: the substrate layer of the SOI wafer, the buried oxide layer, and the device layer. The device layer mainly includes six parts: source terminal S, drain terminal D, body terminal one B1, body terminal two B2, gate terminal one G1, and gate terminal two G2; the source terminal S and drain terminal D are distributed on both sides of a single NMOS switching device; body terminal one B1, body terminal two B2, gate terminal one G1, and gate terminal two G2 are distributed in the middle of the source terminal S and drain terminal D, and the ports of body terminal one B1, body terminal two B2, gate terminal one G1, and gate terminal two G2 correspond one-to-one; gate terminal one G1 is distributed on the upper part of body terminal one B1; gate terminal two G2 is distributed on the upper part of body terminal two B2.

[0027] There is a gap between gate terminal G1 and gate terminal G2; this gap can be adjusted and optimized at the design level according to the specific rules of the process.

[0028] Figure 1 Figure 2These are all cross-sectional views, showing the cross-section, so the layered information is more comprehensive. Figure 3 Figure 4 These are all plan views, showing the top view of the switching device;

[0029] like Figure 1 and Figure 3 The diagram shown is a cross-sectional view of a prior art single-gate NMOS switching device based on SOI technology. This invention will not provide a detailed description of it. The prior art solution includes a gate terminal G and a body terminal B.

[0030] like Figure 4 As shown, the present invention provides a planar schematic diagram of a dual-gate NMOS switching device based on SOI technology and as shown in the figure. Figure 3 Compared to the planar schematic diagram of a prior art single-gate NMOS switching device, the dual-gate NMOS switching device has two gate terminals (G1 and G2) and two body terminals (B1 and B2). Therefore, the overall layout area of ​​the dual-gate NMOS switching device will increase by 15% to 20% compared to the single-gate NMOS switching device; the exact size depends on the specific layout design details. Simultaneously, the voltage withstand capability of the dual-gate NMOS switching device is twice that of the single-gate NMOS switching device. Therefore, under the same voltage withstand conditions, the number of dual-gate NMOS switching devices used can be reduced by half, resulting in an overall area reduction of 30% to 35%. (Specific details are as follows...) Figure 5 As shown in Table 1 below, the normalized on-resistance of a dual-gate NMOS switch is 5% lower than that of a single-gate NMOS switch in practical designs.

[0031]

[0032] Table 1: Measured Analysis of Normalized On-Resistance of Dual-Gate and Single-Gate NMOS Switches in Actual Design Schemes

[0033] This invention presents a dual-gate NMOS switching device design based on SOI technology, which can effectively reduce the layout area of ​​RF switching chips by 30% to 35% under the same design specifications, thereby reducing chip costs and enhancing chip competitiveness. At the same time, the on-resistance of the dual-gate NMOS switching device is also significantly reduced, effectively improving the low-frequency insertion loss performance of the RF switching circuit.

[0034] The preferred embodiments of this utility model disclosed above are merely illustrative of the present utility model. These preferred embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A dual-gate radio frequency switching device, characterized in that, This includes the substrate layer, buried oxide layer, and device layer of the SOI wafer; The device layer includes a source terminal (S), a drain terminal (D), a body terminal one (B1), a body terminal two (B2), a gate terminal one (G1), and a gate terminal two (G2); The source (S) and drain (D) terminals are located on both sides of a single NMOS switching device; The body terminal 1 (B1), body terminal 2 (B2), gate terminal 1 (G1), and gate terminal 2 (G2) are distributed in the middle of the source terminal (S) and the drain terminal (D), and the ports of body terminal 1 (B1), body terminal 2 (B2), gate terminal 1 (G1), and gate terminal 2 (G2) correspond one-to-one. The first gate end (G1) is located on the upper part of the first body end (B1); the second gate end (G2) is located on the upper part of the second body end (B2).

2. The dual-gate radio frequency switch device according to claim 1, characterized in that, A gap is provided between the first gate (G1) and the second gate (G2).

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