Circuit combination structure and display device
By setting storage capacitor electrodes and signal lines on the substrate assembly of the OLED display and forming intervals, the problem of data signal coupling interference caused by parasitic capacitance is solved, the uniformity of the display screen is improved, and the display effect is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2026-03-03
AI Technical Summary
In the circuit design of OLED displays, parasitic capacitance causes data signal coupling interference, resulting in uneven display images and affecting display quality and user experience.
By setting storage capacitor electrodes and signal lines on the substrate assembly and forming a gap between them to reduce the size of the parasitic capacitance generation area, the coupling interference of the enable signal to the data signal is reduced. The storage capacitor electrodes and signal lines can be set on the same circuit wiring layer or different circuit wiring layers, and the coupling interference is reduced by increasing their distance.
It effectively improves the problem of uneven display screen caused by capacitive coupling, reduces the coupling interference of enable signal to data signal through parasitic capacitance, and ensures the performance of the display.
Smart Images
Figure CN223968172U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of circuit setup technology, and more specifically, to a circuit combination structure and a display device. Background Technology
[0002] Currently, a common problem in the circuit design of OLED displays is the coupling interference between the enable signal and the data signal caused by parasitic capacitance. This coupling interference directly leads to unevenness in the display image, thus affecting the display effect and user experience.
[0003] In existing technologies, the storage capacitor electrodes used for data signal storage and the enable signal line are generally placed at relatively close positions on the circuit wiring layer to improve the integration effect of integrated circuits. However, this arrangement will further aggravate the aforementioned coupling interference problem. Utility Model Content
[0004] In view of the problems in the prior art, the purpose of this disclosure is to provide a circuit combination structure and display device that can conveniently adjust the refresh rate of the displayed content during the screen test of the display panel, and make it easier to test the display effect of the display panel.
[0005] Specifically, the first aspect of this disclosure provides a circuit combination structure, which may include:
[0006] Substrate assembly;
[0007] At least one storage capacitor electrode is disposed on the substrate assembly, and the storage capacitor electrode is used to store data signals.
[0008] At least one signal line is disposed on the substrate assembly, and the signal line is used to transmit an enable signal;
[0009] In this process, a parasitic capacitance generation region is formed on the side of the storage capacitor electrode closest to the signal line, and a gap is formed between the storage capacitor electrode and the signal line. The size of the parasitic capacitance generation region is smaller than the size of the gap.
[0010] In one possible implementation of the first aspect described above, the substrate assembly includes at least one circuit wiring layer, on which the storage capacitor electrodes and signal lines are disposed.
[0011] In one possible implementation of the first aspect described above, the storage capacitor electrodes and signal lines are disposed on the same circuit wiring layer.
[0012] In one possible implementation of the first aspect described above, the signal line has an extending direction;
[0013] The signal line includes at least a first part, a second part, and a third part connected in sequence, wherein the first part and the third part extend along the extension direction;
[0014] The dimension of the second part along the extension direction is larger than the dimension of the storage capacitor electrode along the extension direction.
[0015] In one possible implementation of the first aspect described above, the substrate assembly includes at least two circuit wiring layers, with the storage capacitor electrodes and signal lines respectively disposed on the two different circuit wiring layers and spaced apart between the two different circuit wiring layers.
[0016] In one possible implementation of the first aspect described above, the substrate assembly includes at least two circuit wiring layers;
[0017] A portion of the signal line is disposed on the first circuit wiring layer;
[0018] Another part of the signal line is located on a second circuit routing layer, which is on a different layer than the first circuit routing layer;
[0019] The storage capacitor electrode is positioned close to the first circuit wiring layer relative to the second circuit wiring layer, and the storage capacitor electrode is positioned opposite another part of the signal line.
[0020] In one possible implementation of the first aspect above, the signal line includes at least a first part, a second part, and a third part connected in sequence, wherein the first part and the third part are disposed on a first circuit wiring layer;
[0021] The second part is located on the second circuit wiring layer.
[0022] In one possible implementation of the first aspect above, the signal line has an extension direction, and the first portion and the third portion extend along the extension direction;
[0023] The dimension of the second part along the extension direction is larger than the dimension of the storage capacitor electrode along the extension direction.
[0024] In one possible implementation of the first aspect described above, the second part includes a first part, a second part, and a third part connected sequentially, wherein the second part is positioned parallel to the extension direction, and the first and third parts are positioned perpendicular to the extension direction; and
[0025] The dimensions of the first and third parts in the direction perpendicular to the extension direction are larger than the dimensions of the parasitic capacitance generation region in the direction perpendicular to the extension direction.
[0026] A second aspect of this disclosure provides a display device that includes the circuit combination structure provided in the first aspect.
[0027] Compared with the prior art, this disclosure has the following beneficial effects:
[0028] The technical solution disclosed herein provides a combination of storage capacitor electrodes and signal lines, which can effectively improve the problem of uneven display screen caused by capacitive coupling, especially reducing the coupling interference of the enable signal to the data signal through parasitic capacitance, thereby ensuring the performance of the display and having promotional value. Attached Figure Description
[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0030] Figure 1 According to an embodiment of this disclosure, a schematic diagram of a circuit combination structure is provided. Detailed Implementation
[0031] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed herein. This disclosure can also be implemented or applied to systems through other different specific embodiments, and various details in this disclosure can also be modified or changed according to different viewpoints and application systems without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.
[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.
[0033] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.
[0034] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "a plurality of" means two or more, unless otherwise expressly and specifically defined.
[0035] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.
[0036] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.
[0037] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.
[0038] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0039] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.
[0040] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.
[0041] It is understandable that, based on the relevant descriptions in the background art, traditional screen-mounted devices suffer from long processing times and cumbersome operation during refresh rate updates. To address these practical problems, this disclosure provides a screen-mounted module and device with dynamic refresh rate adjustment. The specific implementation of this disclosure will be explained and illustrated below with reference to specific embodiments.
[0042] In some embodiments of this disclosure, Figure 1 A schematic diagram of a circuit combination structure is provided. For example... Figure 1 As shown, this circuit assembly includes: a substrate assembly; at least one storage capacitor electrode 1 disposed on the substrate assembly, the storage capacitor electrode 1 being used to store data signals; and at least one signal line 2 disposed on the substrate assembly, the signal line 2 being used to transmit an En signal; wherein, a parasitic capacitance generation region 8 is formed on the side of the storage capacitor electrode 1 near the signal line 2, and a gap is formed between the storage capacitor electrode 1 and the signal line 2, the size of the parasitic capacitance generation region 8 being smaller than the size of the gap. Furthermore, by maximizing the distance between the storage capacitor electrode 1 and the signal line 2 within the limited space of the circuit design, the parasitic capacitance generation region 8 is moved as far away from the signal line 2 as possible, thereby reducing the coupling interference of the enable signal to the data signal through the parasitic capacitance.
[0043] Furthermore, in some embodiments of this disclosure, the aforementioned dimensions are at least as follows: Figure 1 The dimensions shown are along the vertical direction of the paper; preferably, the size of the parasitic capacitance generation region 8 is the distance from the upper edge to the lower edge of the parasitic capacitance generation region 8; the size of the interval is from the lower edge of the storage capacitor electrode 1 to the upper edge of the portion of the signal line 2 near the storage capacitor electrode 1.
[0044] Furthermore, in some embodiments of this disclosure, the substrate assembly includes at least one circuit wiring layer, on which both the storage capacitor electrode 1 and the signal line 2 are disposed. In some embodiments, if only one circuit wiring layer exists, the storage capacitor electrode 1 and the signal line 2 may be disposed on the same circuit wiring layer, and the signal line 2 may be disposed away from the storage capacitor electrode to avoid interference between the enable signal and the data signal.
[0045] In some embodiments of this disclosure, if the substrate assembly includes two or more circuit wiring layers, then the storage capacitor electrode 1 and the signal line 2 can be respectively disposed on the two circuit wiring layers and spaced apart between the two circuit wiring layers.
[0046] In some embodiments of this disclosure, the circuit wiring layer on which the signal line 2 is provided includes a first circuit wiring layer 3 and a second circuit wiring layer 4 that are staggered. A portion of the signal line 2 is provided on the first circuit wiring layer 3, and another portion of the signal line 2 is provided on the second circuit wiring layer 4. The storage capacitor electrode is provided close to the first circuit wiring layer 3 relative to the second circuit wiring layer 4, and the storage capacitor electrode is provided directly opposite the other portion of the signal line 2.
[0047] In some embodiments of this disclosure, the first circuit wiring layer 3 and the second circuit wiring layer 4 are arranged in parallel.
[0048] In some embodiments of this disclosure, the signal line 2 has an extending direction, and the signal line 2 includes at least a first part 5, a second part 6 and a third part 7 connected in sequence. The first part 5 and the third part 7 are both disposed on the first circuit wiring layer 3, and the second part 6 is disposed on the second circuit wiring layer 4.
[0049] Furthermore, in some embodiments of this disclosure, the dimension of the second portion 6 along the extension direction is larger than the dimension of the storage capacitor electrode along the extension direction.
[0050] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model.
[0051] In some embodiments of this disclosure, a display device is also provided, which includes the circuit combination structure provided in the foregoing embodiments. In a feasible specific implementation, the circuit combination structure provided in the foregoing embodiments can be integrated into the display device to avoid interference between data signals and enable signals affecting the normal display function of the display device.
[0052] In summary, the technical solution provided in this disclosure offers a combination of storage capacitor electrodes and signal lines, which can effectively improve the uneven display screen caused by capacitive coupling. In particular, it reduces the coupling interference of the enable signal to the data signal through parasitic capacitance, thereby ensuring the performance of the display and has promotional value.
[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this disclosure and should not be construed as limiting the specific implementation of this disclosure to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this disclosure, and all such modifications and substitutions should be considered within the scope of protection of this disclosure.
Claims
1. A circuit combination structure, characterized in that, include: Substrate assembly; At least one storage capacitor electrode is disposed on the substrate assembly, and the storage capacitor electrode is used to store data signals; At least one signal line is disposed on the substrate assembly, and the signal line is used to transmit an enable signal; In this configuration, a parasitic capacitance generation region is formed on the side of the storage capacitor electrode closest to the signal line, and a gap is formed between the storage capacitor electrode and the signal line. The size of the parasitic capacitance generation region is smaller than the size of the gap.
2. The circuit combination structure according to claim 1, characterized in that, The substrate assembly includes at least one circuit wiring layer, and the storage capacitor electrodes and the signal lines are both disposed on the circuit wiring layer.
3. The circuit combination structure according to claim 2, characterized in that, The storage capacitor electrodes and the signal lines are disposed on the same circuit wiring layer.
4. The circuit combination structure according to claim 3, characterized in that, The signal line has an extending direction; The signal line includes at least a first part, a second part, and a third part connected in sequence, wherein the first part and the third part extend along the extension direction; The dimension of the second portion along the extension direction is greater than the dimension of the storage capacitor electrode along the extension direction.
5. The circuit combination structure according to claim 2, characterized in that, The substrate assembly includes at least two circuit wiring layers, the storage capacitor electrode and the signal line are respectively disposed on two different circuit wiring layers, and the spacing is formed between the two different circuit wiring layers.
6. The circuit combination structure according to claim 2, characterized in that, The substrate assembly includes at least two circuit wiring layers; A portion of the signal line is disposed on the first circuit wiring layer; Another portion of the signal line is disposed on a second circuit wiring layer that is different from the first circuit wiring layer; The storage capacitor electrode is positioned close to the first circuit wiring layer relative to the second circuit wiring layer, and the storage capacitor electrode is positioned opposite another portion of the signal line.
7. The circuit combination structure according to claim 6, characterized in that, The signal line includes at least a first part, a second part, and a third part connected in sequence, wherein the first part and the third part are disposed on the first circuit wiring layer; The second part is disposed on the second circuit wiring layer.
8. The circuit combination structure according to claim 7, characterized in that, The signal line has an extending direction, and the first portion and the third portion extend along the extending direction; The dimension of the second portion along the extension direction is greater than the dimension of the storage capacitor electrode along the extension direction.
9. The circuit combination structure according to claim 4 or claim 8, characterized in that, The second part includes a first part, a second part, and a third part connected in sequence. The second part is arranged in a direction parallel to the extension direction, and the first part and the third part are arranged in a direction perpendicular to the extension direction. as well as The dimensions of the first part and the third part in the direction perpendicular to the extension direction are greater than the dimensions of the parasitic capacitance generation region in the direction perpendicular to the extension direction.
10. A display device, characterized in that, The circuit combination structure includes any one of claims 1 to 6 above.