Semiconductor memory

Abstract

To provide a semiconductor memory device that can improve operating speed. [Solution] The semiconductor memory device of the embodiment comprises a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier module that reads data from the memory cell transistor via the bit line. The sense amplifier module includes a first node electrically connectable to the bit line and a second node capacitively coupled to the first node. The sense amplifier module is configured such that, during a read operation in which first data and second data are read consecutively, in the first period of the consecutive first and second periods, the voltage of the second node decreases in accordance with the decrease in the voltage of the first node due to capacitive coupling. The first data is determined based on the voltage of the second node that decreased in the first period, and the second data is determined based on the voltage of the first node that decreased in the second period.

Description

Technical Field

[0001] Embodiments relate to a semiconductor memory device.

Background Art

[0002] A NAND-type flash memory capable of storing data non-volatilely is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] [[ID=4!2]] To provide a semiconductor memory device with improved operating speed.

Means for Solving the Problems

[0005] It should be noted that there seems to be some incorrect tags in the original text (such as "!17" and "!40" and "!41" and "!42" which might be errors during input). The translation is done based on the provided text as accurately as possible while keeping those tags intact.The semiconductor memory device of the embodiment comprises a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier module that reads data from the memory cell transistor via the bit line. The sense amplifier module includes a first node electrically connectable to the bit line and a second node capacitively coupled to the first node. The sense amplifier module is configured such that, during a read operation in which a first voltage is applied to the gate of the memory cell transistor and first data and second data are read consecutively, in the first period of a consecutive first and second period, the voltage of the second node decreases in accordance with the decrease in the voltage of the first node due to the capacitive coupling of the first node and the second node. The first data is determined based on the voltage of the second node that decreased in the first period, and the second data is determined based on the voltage of the first node that decreased in the second period. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the overall configuration including the memory system and host equipment according to the embodiment. [Figure 2] A block diagram showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 4] A diagram showing an example of the threshold voltage distribution of memory cell transistors in a semiconductor memory device according to the embodiment. [Figure 5] A block diagram showing an example of the configuration of a sense amplifier module included in a semiconductor memory device according to the embodiment. [Figure 6] A circuit diagram showing an example of the circuit configuration of a sense amplifier module included in a semiconductor memory device according to the embodiment. [Figure 7] A diagram illustrating the selection of program operations in a write operation using a semiconductor memory device according to the embodiment. [Figure 8]A diagram illustrating the verification operation using a semiconductor memory device according to the embodiment. [Figure 9] A timing chart illustrating the verification operation using a semiconductor memory device according to the embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be given a common reference numeral. When multiple components having a common reference numeral need to be distinguished, a subscript will be added to the common reference numeral to distinguish them. When there is no particular need to distinguish between multiple components, only the common reference numeral will be assigned to those components, and no subscript will be added. Subscripts include, for example, lowercase alphabet letters added to the end of the reference numeral, and indices indicating arrangement.

[0008] 1. Embodiment A memory system according to an embodiment will be described.

[0009] 1.1 Configuration The configuration of the memory system according to the embodiment will be described.

[0010] 1.1.1 Memory System The overall configuration of the memory system according to this embodiment will be explained with reference to Figure 1. Figure 1 is a block diagram showing an example of the overall configuration including the memory system and host equipment according to this embodiment.

[0011] The memory system 3 comprises a semiconductor storage device 1 and a memory controller 2. The semiconductor storage device 1 and the memory controller 2 may, for example, be combined to form a single semiconductor device. The memory system 3 may be, for example, an SSD (solid state drive) or an SD TM It's a card.

[0012] The memory system 3 communicates with, for example, an external host device 4. The memory system 3 stores data from the host device 4. Also, the memory system 3 reads out data to the host device 4.

[0013] The semiconductor memory device 1 is, for example, a semiconductor memory. The semiconductor memory device 1 includes a plurality of memory cells. The semiconductor memory device 1 stores data non-volatilely. The semiconductor memory device 1 is, for example, a NAND-type flash memory. The semiconductor memory device 1 can also be called a memory device. The semiconductor memory device 1 is connected to the memory controller 2 by, for example, a NAND bus.

[0014] The NAND bus transmits and receives various signals conforming to the NAND interface via individual signal lines. The various signals include, for example, / CE, CLE, ALE, / WE, / RE, RE, / WP, / RB, DQ<7:0>, DQS, and / DQS.

[0015] Signal / CE is the Chip Enable signal. Signal / CE is a signal to enable semiconductor memory device 1. Signal CLE is the Command Latch Enable signal. Signal CLE notifies semiconductor memory device 1 that the signal DQ<7:0> flowing to semiconductor memory device 1 is a command while signal CLE is at the "H (High)" level. Signal ALE is the Address Latch Enable signal. Signal CLE notifies semiconductor memory device 1 that the signal DQ<7:0> flowing to semiconductor memory device 1 is an address while signal ALE is at the "H" level. Signal / WE is the Write Enable signal. Signal / WE instructs semiconductor memory device 1 to capture signal DQ<7:0>. Signal / WE instructs the semiconductor memory device 1 to capture signal DQ<7:0> as a command, address, or data on the rising edge of signal / WE in single data rate (SDR) mode. Signal / WE also instructs the semiconductor memory device 1 to capture signal DQ<7:0> as a command or address on the rising edge of signal / WE in double data rate (DDR) mode. Signal / RE is a read enable signal. Signal / RE instructs the semiconductor memory device 1 to output signal DQ<7:0>. Signal / RE instructs the semiconductor memory device 1 to output signal DQ<7:0> as data on the falling edge of signal / RE in single data rate mode. Signal / RE also instructs the semiconductor memory device 1 to output signal DQ<7:0> as data on both the falling and rising edges of signal / RE in double data rate mode. Signal RE is the complementary signal to signal / RE. Signal / WP is the Write Protect signal. Signal / WP instructs the semiconductor memory device 1 to prohibit the writing and erasure of data.Signal / RB is a Ready Busy signal. Signal / RB indicates whether the semiconductor memory device 1 is in a ready state (ready to accept external commands) or a busy state (not ready to accept external commands). Signal DQ<7:0> is, for example, an 8-bit signal. Signal DQS is a Data Strobe signal. Signal DQS is used to control the operating timing of the semiconductor memory device 1 related to signal DQ<7:0>. Signal DQS instructs the semiconductor memory device 1 to capture signal DQ<7:0> as data at the falling and rising edges of signal DQS, for example, in a double data rate. Signal DQS is also generated based on the falling and rising edges of signal / RE, for example, in a double data rate, and is output from the semiconductor memory device 1 along with signal DQ<7:0> as data. Signal / DQS is a complementary signal to signal DQS.

[0016] The signal DQ<7:0> is transmitted and received between the semiconductor memory device 1 and the memory controller 2, and includes a command CMD, an address ADD, and data DAT. The command CMD includes, for example, a command to cause the semiconductor memory device 1 to perform a write operation (write command), a command to cause the semiconductor memory device 1 to perform a read operation (read command), and a command to cause the semiconductor memory device 1 to perform an erase operation (erase command). The data DAT includes read data and written data.

[0017] The memory controller 2 is composed of an integrated circuit such as a SoC (System-on-a-Chip), for example. The memory controller 2 receives commands from the host device 4. The functions of each part of the memory controller 2 can be realized by dedicated hardware, a processor that executes a program and firmware, or a combination thereof. The memory controller 2 controls the semiconductor memory device 1 based on the commands received from the host device 4. Specifically, the memory controller 2 writes the data instructed to be written into the semiconductor memory device 1 based on the write command received from the host device 4. Also, the memory controller 2 reads out the data instructed to be read from the host device 4 from the semiconductor memory device 1 based on the read command received from the host device 4 and transmits it to the host device 4.

[0018] 1.1.2 Memory Controller The configuration of the memory controller 2 will be continuously described using FIG. 1.

[0019] The memory controller 2 includes a processor (CPU: Central Processing Unit) 21, a built-in memory 22, a buffer memory 23, a NAND I / F (NAND interface circuit) 24, and a host I / F (host interface circuit) 25.

[0020] The CPU 21 controls the operation of the entire memory controller 2. The CPU 21 issues, for example, commands for instructing the execution of various operations such as writing, reading, and erasing operations to the semiconductor memory device 1.

[0021] The built-in memory 22 is a semiconductor memory such as a DRAM (Dynamic Random Access Memory), for example. The built-in memory 22 is used as a working area for the CPU 21. The built-in memory 22 stores firmware for managing the semiconductor memory device 1 and various management tables and the like.

[0022] The buffer memory 23 temporarily stores data that has been written from the host device 4, and data that has been read by the memory controller 2 from the semiconductor storage device 1.

[0023] The NAND interface circuit 24 is connected to the semiconductor memory device 1 via a NAND bus and is responsible for communication with the semiconductor memory device 1. The NAND interface circuit 24 transmits the command CMD, address ADD, and write data to the semiconductor memory device 1 according to instructions from the CPU 21. The NAND interface circuit 24 also receives read data from the semiconductor memory device 1.

[0024] The host interface circuit 25 is connected to the host device 4 via the host bus and is responsible for communication between the memory controller 2 and the host device 4. For example, the host interface circuit 25 transfers instructions and data received from the host device 4 to the CPU 21 and buffer memory 23, respectively.

[0025] 1.1.3 Semiconductor memory devices Next, an example of the configuration of the semiconductor memory device 1 according to the embodiment will be described using Figure 2. Figure 2 is a block diagram showing an example of the configuration of the semiconductor memory device according to the embodiment.

[0026] The semiconductor memory device 1 includes a memory cell array 10, an input / output circuit 11, a logic control circuit 12, an address register 13, a command register 14, a sequencer 15, a driver module 16, a row decoder module 17, and a sense amplifier module 18.

[0027] The memory cell array 10 includes multiple blocks BLK0 to BLK(m-1), where m is an integer greater than or equal to 2. Each block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. Each block BLK is used, for example, as a data erasure unit. That is, data stored in the memory cell transistors contained within the same block BLK is erased all at once. The detailed configuration of the memory cell array 10 will be described later.

[0028] The input / output circuit 11 transmits and receives the signal DQ<7:0> to and from the memory controller 2. The input / output circuit 11 transfers the address ADD and command CMD within the signal DQ<7:0> to the address register 13 and the command register 14, respectively. The input / output circuit 11 also transmits and receives data DAT to and from the sense amplifier module 18.

[0029] The logic control circuit 12 receives signals such as / CE, CLE, ALE, / WE, / RE, RE, / WP, DQS, and / DQS from the memory controller 2. Based on the received signals, the logic control circuit 12 controls the input / output circuit 11. The logic control circuit 12 also generates the signal / RB and transmits it to the memory controller 2.

[0030] The address register 13 stores the address ADD transferred from the input / output circuit 11. The address register 13 then transfers the stored address ADD to the row decoder module 17 and the sense amplifier module 18.

[0031] Command register 14 stores the command CMD transferred from the input / output circuit 11. Command register 14 then transfers the stored command CMD to the sequencer 15.

[0032] The sequencer 15 receives a command CMD from the command register 14. The sequencer 15 controls the entire semiconductor memory device 1 according to the sequence based on the received command CMD. For example, when the sequencer 15 receives an erase command, a write command, and a read command, it instructs the driver module 16 to generate the voltage used in the corresponding operation.

[0033] The driver module 16 generates voltages used for erase, write, and read operations based on instructions from the sequencer 15. The driver module 16 supplies the generated voltages to the raw decoder module 17, sense amplifier module 18, etc.

[0034] The raw decoder module 17 receives a block address in address ADD from the address register 13. Based on this block address, the raw decoder module 17 selects one of several block BLKs. The raw decoder module 17 then applies, for example, the voltage supplied from the driver module 16 to the selected block BLK.

[0035] The sense amplifier module 18 receives the column address in address ADD from the address register 13. Based on this column address, the sense amplifier module 18 transfers data DAT between the memory controller 2 and the memory cell array 10. More specifically, during a write operation, the sense amplifier module 18 receives the write data from the input / output circuit 11 and transfers the received write data to the memory cell array 10. During a read operation, the sense amplifier module 18 senses the threshold voltage of the memory cell transistor targeted for read operation in the memory cell array 10, generates read data, and transfers the generated read data to the input / output circuit 11.

[0036] 1.1.4 Memory cell array The configuration of each block BLK included in the memory cell array 10 of the semiconductor memory device 1 will be explained with reference to Figure 3. Figure 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array provided in the semiconductor memory device according to this embodiment.

[0037] Block BLK includes, for example, five string units SU0, SU1, SU2, SU3, and SU4. Hereafter, unless otherwise distinguished, each of the string units SU0-SU4 will simply be referred to as string unit SU. Each string unit SU contains multiple NAND strings NS.

[0038] Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2. Hereinafter, when memory cell transistors MT0 to MT7 are not distinguished, each of them will simply be referred to as a memory cell transistor MT. The number of memory cell transistors MT included in each NAND string NS is not limited. Each memory cell transistor MT has a stacked gate including a control gate and a charge storage layer. Each memory cell transistor MT is connected in series between one end of selection transistor ST1 and one end of selection transistor ST2.

[0039] In each block BLK, the gates of the selection transistors ST1 of string units SU0 to SU4 are connected to selection gate lines SGD0 to SGD4, respectively. That is, each selection gate line SGD is connected to only one string unit SU within the same block BLK. Also, the gates of the selection transistors ST2 of all string units SU within a block BLK are connected to selection gate line SGS. That is, selection gate line SGS is connected to all string units SU within the same block BLK. Furthermore, the control gates of the memory cell transistors MT0 to MT7 within each block BLK are connected to word lines WL0 to WL7, respectively. That is, word lines WL with the same address are connected to all string units SU within the same block BLK.

[0040] The other end of the selection transistor ST1 is connected to one of several bit lines BL0 to BL(n-1), where n is an integer greater than or equal to 2. Each bit line BL is connected to the same row of NAND strings NS in each of the multiple blocks BLK.

[0041] The other end of the selection transistor ST2 is connected to the source line SL. The source line SL is shared, for example, between multiple blocks BLK.

[0042] As described above, data erasure is performed collectively, for example, on memory cell transistors MT within the same block BLK. In contrast, read and write operations can be performed collectively on multiple memory cell transistors MT connected to any word line WL in any string unit SU of any block BLK. In the configuration described above, a set of memory cell transistors MT sharing one word line WL in each string unit SU is called, for example, a cell unit CU. A cell unit CU is a set of memory cell transistors MT on which write or read operations are performed collectively. A cell unit CU corresponds to, for example, a set of one or more storage areas. A write or read operation on a single cell unit CU is performed on one of the storage areas in that set. Such a unit of storage area is called a "page".

[0043] 1.1.5 Threshold distribution of memory cell transistors The threshold voltage distribution of the memory cell transistor MT in the semiconductor memory device 1 will be explained using Figure 4. Figure 4 is a diagram showing an example of the threshold voltage distribution of the memory cell transistor in the semiconductor memory device according to this embodiment.

[0044] In Figure 4, the vertical axis of the threshold voltage distribution corresponds to the number of memory cell transistors (NMTs), and the horizontal axis corresponds to the threshold voltage (Vth) of the memory cell transistors (MTs).

[0045] In the semiconductor memory device 1 according to this embodiment, for example, eight states are formed by the threshold voltages of a plurality of memory cell transistors MT. That is, each memory cell transistor MT may have eight states. Hereinafter, these eight states will be referred to as the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state, in order from the lowest threshold voltage.

[0046] The “Er” state corresponds, for example, to a data erasure state. The threshold voltage of the memory cell transistor MT included in the “Er” state is less than the voltage VA.

[0047] State "A" to "G" corresponds to the state in which charge has been injected into the charge storage layer of the memory cell transistor MT. In state "A", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VA and less than voltage VB (VB>VA). In state "B", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VB and less than voltage VC (VC>VB). In state "C", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VC and less than voltage VD (VD>VC). In state "D", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VD and less than voltage VE (VE>VD). In state "E", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VE and less than voltage VF (VF>VE). In state "F", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VF and less than voltage VG (VG>VF). In state "G", the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VG and less than voltage VREAD (VREAD>VG).

[0048] When a voltage is applied to the control gate of a memory cell transistor (MT), the MT turns ON if its threshold voltage is less than the applied voltage. When a voltage is applied to the control gate of a memory cell transistor (MT), the MT turns OFF if its threshold voltage is greater than or equal to the applied voltage. Furthermore, when the voltage VREAD is applied to the control gate of a memory cell transistor (MT), the MT turns ON regardless of whether its state is "Er" through "G".

[0049] Each of the eight states described above is assigned a unique set of three bits of data. This allows each memory cell transistor (MT) to hold three bits of data. An example of data assignment for each of the eight states is listed below. In the following, the data assigned to each state is shown in the order of "higher bit, middle bit, lower bit" corresponding to that state.

[0050] “Er” state: “1, 1, 1” data, "A" state: "1, 1, 0" data, "B" state: "1, 0, 0" data, "C" state: "0, 0, 0" data, "D" state: "0, 1, 0" data, "E" state: "0, 1, 1" data, "F" state: "0, 0, 1" data, “G” state: “1, 0, 1” data.

[0051] When such data allocation is applied, the lower-order bits (lower page data) are determined by read operations using voltages VA and VE, respectively. The middle-order bits (middle page data) are determined by read operations using voltages VB, VD, and VF, respectively. The upper-order bits (upper page data) are determined by read operations using voltages VC and VG, respectively. Hereafter, voltages VA to VG will also be referred to as read voltages.

[0052] Furthermore, the number of states formed by the threshold voltages of multiple memory cell transistors MT is not limited to eight. For example, the number of states formed by the threshold voltages of multiple memory cell transistors MT may be two, four, or sixteen or more.

[0053] 1.1.6 Sense Amplifier Module The configuration of the sense amplifier module 18 in the semiconductor memory device 1 will be explained with reference to Figure 5. Figure 5 is a block diagram showing an example of the configuration of a sense amplifier module provided in the semiconductor memory device according to this embodiment.

[0054] The sense amplifier module 18 includes multiple sense amplifier units SAU0 to SAU(n-1) and multiple latch circuits XDL. Each of the multiple sense amplifier units SAU0 to SAU(n-1) is provided corresponding to multiple bit lines BL. Hereinafter, when the multiple sense amplifier units SAU0 to SAU(n-1) are not distinguished from each other, each of the multiple sense amplifier units SAU0 to SAU(n-1) will simply be referred to as a sense amplifier unit SAU. Each of the multiple latch circuits XDL is provided corresponding to multiple bit lines BL and multiple sense amplifier units SAU0 to SAU(n-1).

[0055] Each sense amplifier unit SAU includes, for example, latch circuits TDL, SDL, ADL, BDL, and CDL, and a sense circuit SA. The latch circuits TDL, SDL, ADL, BDL, and CDL and the sense circuit SA included in each sense amplifier unit SAU are connected to each other via the bus LBUS corresponding to the sense amplifier unit SAU. In addition, the latch circuit XDL corresponding to the sense amplifier unit SAU is connected to the latch circuits TDL, SDL, ADL, BDL, and CDL and the sense circuit SA via the bus LBUS. With this configuration, each of the latch circuits TDL, SDL, ADL, BDL, and CDL and the sense circuit SA included in each sense amplifier unit SAU and the latch circuit XDL corresponding to the sense amplifier unit SAU are connected to each other via the bus LBUS, enabling them to send and receive data.

[0056] The latch circuit XDL is used, for example, to transmit and receive data DAT between the sense amplifier unit SAU and the input / output circuit 11.

[0057] The latch circuits TDL, SDL, ADL, BDL, and CDL temporarily store, for example, written or read data. A more detailed configuration of the latch circuits TDL, SDL, ADL, BDL, and CDL will be described later.

[0058] The sense circuit SA senses the threshold voltage of the memory cell transistor MT based on the current flowing through the bit line BL during read operations. Furthermore, during write operations, the sense circuit SA applies a voltage to the bit line BL according to the data being written. In addition, the sense circuit SA performs various calculations using the data stored in the latch circuits TDL, SDL, ADL, BDL, CDL, and XDL.

[0059] 1.1.7 Sense Amplifier Unit An example of the circuit configuration of the sense amplifier unit SAU will be explained using Figure 6. Figure 6 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module provided in a semiconductor memory device according to the embodiment. In Figure 6, the circuit configuration of one sense amplifier unit SAU among the sense amplifier module 18 is shown together with the latch circuit XDL. Hereinafter, one of the source and drain of a transistor will be referred to as "one end of the transistor," and the other of the source and drain will be referred to as "the other end of the transistor."

[0060] First, let's explain the configuration of the sense circuit SA.

[0061] The sense circuit SA includes transistors 30-43 and capacitors 44 and 45. Transistor 30 is, for example, a high-voltage n-channel MOS (Metal-Oxide-Semiconductor) transistor. Transistors 31-43 are, for example, low-voltage p-channel MOS transistors. Capacitor 44 is, for example, the capacitance between different wirings, as will be described later. However, it is not limited to this, and capacitor 44 may be a capacitive element such as a MOS capacitor. Capacitor 45 is, for example, a capacitive element such as a MOS capacitor.

[0062] One end of transistor 30 is connected to the bit line BL. The other end of transistor 30 is connected to node BLI. The signal BLS is input to the gate of transistor 30.

[0063] One end of transistor 31 is connected to node BLI. The other end of transistor 31 is connected to node SCOM. The signal BLC is input to the gate of transistor 31. Transistor 31 is provided to clamp the bit line BL corresponding to transistor 31 to a voltage corresponding to the signal BLC.

[0064] One end of transistor 32 is connected to node SCOM. The other end of transistor 32 is connected to node SSRC. The signal BLX is input to the gate of transistor 32.

[0065] One end of transistor 33 is connected to node SSRC. The other end of transistor 33 is connected to node SRCGND. A voltage VSS is applied to node SRCGND, for example. The voltage VSS is, for example, the ground voltage. The gate of transistor 33 is connected to node LAT_S.

[0066] A voltage VDD is applied to one end of transistor 34 from the power supply. The other end of transistor 34 is connected to node SSRC. The gate of transistor 34 is connected to node LAT_S.

[0067] One end of transistor 35 is connected to node SCOM. The other end of transistor 35 is connected to node SEN1. The signal XXL is input to the gate of transistor 35.

[0068] A voltage VSENP is applied to one end of transistor 36. The other end of transistor 36 is connected to node SEN1. The signal HLL is input to the gate of transistor 36.

[0069] One end of transistor 37 is connected to node SEN1. The other end of transistor 37 is connected to node SEN2. The signal S2S is input to the gate of transistor 37.

[0070] One end of transistor 38 is connected to the bus LBUS. The signal STB is input to the gate of transistor 38.

[0071] One end of transistor 39 is connected to the other end of transistor 38. The other end of transistor 39 is connected to node LOP. A voltage VLOP is applied to node LOP from the power supply. The gate of transistor 39 is connected to node SEN2.

[0072] One end of transistor 40 is connected to the bus LBUS. The other end of transistor 40 is connected to node SEN2. The signal BLQ is input to the gate of transistor 40.

[0073] One end of transistor 41 is connected to node SEN2. The signal LSL is input to the gate of transistor 41.

[0074] One end of transistor 42 is connected to the other end of transistor 41. The other end of transistor 42 is connected to node LOP. The gate of transistor 42 is connected to bus LBUS.

[0075] A voltage VDD is applied to one end of transistor 43 from the power supply. The other end of transistor 43 is connected to the bus LBUS. The signal LPC is input to the gate of transistor 43.

[0076] Next, the configurations of the latch circuits TDL, SDL, ADL, BDL, and CDL will be explained using Figure 6. The circuit configurations of the latch circuits TDL, SDL, ADL, BDL, and CDL are substantially the same. Therefore, Figure 6 shows the circuit configurations of latch circuits TDL and SDL.

[0077] This section describes the circuit configuration of the latch circuit TDL.

[0078] The latch circuit TDL includes transistors 50-57. Transistors 50-53 are low-voltage n-channel MOS transistors. Transistors 54-57 are low-voltage p-channel MOS transistors.

[0079] One end of transistor 50 is connected to node INV_T. The other end of transistor 50 is connected to bus LBUS. The signal TTI is input to the gate of transistor 50.

[0080] One end of transistor 51 is connected to node LAT_T. The other end of transistor 51 is connected to bus LBUS. A TTL signal is input to the gate of transistor 51.

[0081] One end of transistor 52 is connected to node INV_T. The other end of transistor 52 is subjected to the voltage VSS. The gate of transistor 52 is connected to node LAT_T.

[0082] One end of transistor 53 is connected to node LAT_T. The other end of transistor 53 is connected to the other end of transistor 52. As a result, the voltage VSS is applied to the other end of transistor 53, just as it is to the other end of transistor 52. The gate of transistor 53 is connected to node INV_T.

[0083] A voltage VDD is applied to one end of transistor 54 from the power supply. The signal TLI is input to the gate of transistor 54.

[0084] One end of transistor 55 is connected to the other end of transistor 54. As a result, the voltage VDD is applied to one end of transistor 55, just as it is to the other end of transistor 54. The signal TLL is input to the gate of transistor 55.

[0085] One end of transistor 56 is connected to the other end of transistor 54. The other end of transistor 56 is connected to node INV_T. The gate of transistor 56 is connected to node LAT_T.

[0086] One end of transistor 57 is connected to the other end of transistor 55. The other end of transistor 57 is connected to node LAT_T. The gate of transistor 57 is connected to node INV_T.

[0087] In the latch circuit TDL, transistors 53 and 57 constitute the first inverter. Transistors 52 and 56 constitute the second inverter. The output of the first inverter and the input of the second inverter (voltage at node LAT_T) are connected to the bus LBUS via data transfer transistor 51. The input of the first inverter and the output of the second inverter (voltage at node INV_T) are also connected to the bus LBUS via data transfer transistor 50. The latch circuit TDL holds inverted data at nodes LAT_T and INV_T, respectively.

[0088] The latch circuit SDL includes transistors 60-67. Transistors 60-67 correspond to transistors 50-57, respectively. Signals STI, STL, SLI, and SLL correspond to signals TTI, TTL, TLI, and TLL, respectively. Nodes INV_S and LAT_S correspond to nodes INV_T and LAT_T, respectively. As mentioned above, the circuit configurations of latch circuits TDL, SDL, ADL, BDL, and CDL are substantially equivalent to each other, therefore, a detailed explanation of the SDL circuit configuration is omitted.

[0089] The various signals in the sense amplifier unit SAU described above are input, for example, through the control of the sequencer 15.

[0090] 1.2 Operation The operation using the semiconductor memory device 1 according to this embodiment will be described below. The writing operation using the semiconductor memory device 1 according to this embodiment will be described.

[0091] First, we will describe the overview of the writing operation in the embodiment.

[0092] The write operation includes a program operation and a verify operation. The program operation is an operation that increases the threshold voltage by injecting electrons into the charge storage layer, or maintains the threshold voltage by prohibiting injection. The verify operation is an operation that reads the data after the program operation and determines whether the threshold voltage of the memory cell transistor MT has reached a target voltage. Hereinafter, this target voltage will also be called the target level. The target level is set to, for example, voltages VA, VB, VC, VD, VE, VF, or VG. The semiconductor memory device 1 raises the threshold voltage of the memory cell transistor MT to the target level by repeatedly performing combinations of program operations and verify operations.

[0093] 1.2.1 Program Operation Selection In the write operation according to the embodiment, the operation and conditions to be applied in the next program operation are selected according to the result of the verification operation.

[0094] In the following section, the selection of program operations in a write operation using the semiconductor memory device 1 according to the embodiment will be explained with reference to Figure 7. Figure 7 is a diagram illustrating the selection of program operations in a write operation using the semiconductor memory device according to the embodiment. The example in Figure 7 shows an example of the threshold voltage distribution during the process of writing to a memory cell transistor MT with a target level of voltage VA from the “Er” state to the “A” state.

[0095] In the following, the operation that increases the threshold voltage will be referred to as the "0 program operation." The operation that maintains the threshold voltage will be referred to as the "1 program operation" or "write-protect (inhibit) operation."

[0096] In the embodiment, during the "0" program operation, either a first program condition in which the threshold voltage rise is relatively large, or a second program condition in which the threshold voltage rise is smaller than that of the first program condition, is applied depending on the difference between the target level and the threshold voltage of the memory cell transistor MT.

[0097] For example, if the threshold voltage of the memory cell transistor MT is sufficiently low to the target level, and it is expected that the target level will not be reached in the next program operation, then the first program condition, which involves a relatively large increase in the threshold voltage, is applied. Conversely, if the threshold voltage of the memory cell transistor MT is relatively close to the target level, and it is expected that applying the first program condition in the next program operation would cause the threshold voltage to significantly exceed the target level, then the second program condition is applied.

[0098] If the threshold voltage of a memory cell transistor MT is greater than or equal to voltage VH, the "1" program operation is applied to the memory cell transistor MT. If the threshold voltage of the memory cell transistor MT is less than voltage VH, the "0" program operation is applied. In the example in Figure 7, voltage VH is, for example, voltage VA. Furthermore, if the memory cell transistor MT is in the "A" state, the "1" program operation is applied. Furthermore, if the memory cell transistor MT is in the "Er" state, the "0" program operation is applied.

[0099] When the “0” program operation is applied, the semiconductor memory device 1 determines which of the first and second program conditions applies. In this determination, for example, a voltage VL lower than voltage VH may be set. As a result, if the threshold voltage of the memory cell transistor MT is less than voltage VL, the first program condition is applied to the memory cell transistor MT in the next program operation. In Figure 6, the state in which the threshold voltage of the memory cell transistor MT is less than voltage VL is shown as the “Er1” state. Also, if the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VL and less than voltage VH, the second program condition is applied to the memory cell transistor MT in the next program operation. In Figure 6, the state in which the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VL and less than voltage VH is shown as the “Er2” state.

[0100] 1.2.2 Verification Operation Next, the verification operation in the embodiment will be described.

[0101] 1.2.2.1 Overview First, an overview of the verification operation in the embodiment will be explained using Figure 8. Figure 8 is a diagram illustrating the verification operation using the semiconductor memory device according to the embodiment.

[0102] The verification operation in this embodiment includes a first sense operation and a second sense operation. The first sense operation is an operation that determines whether to apply the first program condition of the "0" program operation in the next program operation. The second sense operation is an operation that determines whether to apply the "1" program operation or the second program condition of the "0" program operation to the memory cell transistor MT that has been determined not to apply the first program condition of the "0" program operation in the next program operation. In this manner, the semiconductor memory device 1 according to this embodiment determines which of the "0" program operation and the "1" program operation to apply in the next program operation, and also determines which of the first program condition and the second program condition to apply when the "0" program operation is applied.

[0103] In other words, the first sense operation corresponds to determining whether the threshold voltage of the memory cell transistor MT has reached voltage VL. The second sense operation corresponds to determining whether the threshold voltage of the memory cell transistor MT whose threshold voltage has reached voltage VL has reached voltage VH.

[0104] In FIG. 8, the voltage of node SEN1 corresponding to the memory cell transistor MT targeted for the “1” program operation is indicated by a solid line. Also, the voltage of node SEN1 corresponding to the memory cell transistor MT targeted for the “0” program operation to which the first program condition is applied is indicated by a dashed line. Further, the voltage of node SEN1 corresponding to the memory cell transistor MT targeted for the “0” program operation to which the second program condition is applied is indicated by a one-dot chain line.

[0105] In the embodiment, in the verify operation, while voltage VH is applied to word line WL, the charge of node SEN1 is transferred to bit line BL. Note that, in the verify operation, nodes SEN1 and SEN2 are, for example, substantially the same node. Among these, the first sense period TSL from time t0 to t1 corresponds to the first sense operation, and the second sense period TSH from time t1 to t2 corresponds to the second sense operation. Hereinafter, when not distinguishing between the first sense period TSL and the second sense period TSH, the first sense period TSL and the second sense period TSH are each simply referred to as the sense period.

[0106] When the charge of node SEN1 is transferred to bit line BL during the sense period, the voltage of node SEN1 decreases. At this time, the rate at which the voltage of node SEN1 decreases varies according to the threshold voltage Vth of the memory cell transistor MT. For example, when the threshold voltage Vth is less than voltage VL (Vt < VL), the memory cell transistor MT is in a strong on state. Thereby, the voltage of node SEN1 (the dashed line in FIG. 8) rapidly decreases. When the threshold voltage Vth is greater than or equal to voltage VL and less than voltage VH (VL ≤ Vt < VH), the memory cell transistor MT is in a weak on state. Thereby, the voltage of node SEN1 (the one-dot chain line in FIG. 8) gradually decreases. Also, when the threshold voltage Vth is greater than or equal to voltage VH (Vt ≥ VH), the memory cell transistor MT is in an off state. Thereby, the voltage of node SEN1 (the solid line in FIG. 8) hardly decreases.

[0107] Based on the above relationship, the length of the first sense period TSL is set such that the voltage of node SEN1 corresponding to a memory cell transistor MT with a threshold voltage Vth less than voltage VL falls below a predetermined judgment level, and the voltage of node SEN1 corresponding to a memory cell transistor MT with a threshold voltage Vth greater than or equal to voltage VL falls above the judgment level. The length of the second sense period TSH is set such that the voltage of node SEN1 corresponding to a memory cell transistor MT with a threshold voltage Vth less than voltage VH falls below a predetermined judgment level, and the voltage of node SEN1 corresponding to a memory cell transistor MT with a threshold voltage Vth greater than or equal to voltage VH falls above the judgment level. The predetermined judgment level is, for example, the threshold voltage of transistor 39 in the sense amplifier unit SAU shown in Figure 6. During verification operation, for example, transistor 37 is turned on. As a result, during verification operation, for example, the voltage of node SEN1 and the voltage of node SEN2 are equivalent. Therefore, whether the voltage of node SEN1 falls above the judgment level corresponds to whether transistor 39 turns on in accordance with the voltages of nodes SEN1 and SEN2.

[0108] The sense amplifier module 18 determines whether the voltage at node SEN1 falls below a certain level at the end of the first sense period TSL and before the second sense period TSH. This allows the sense amplifier module 18 to determine whether the threshold voltage Vth of the memory cell transistor MT falls below voltage VL during the verify operation in which voltage VH is applied to the word line WL. In other words, the sense amplifier module 18 can determine whether to apply the "0" program operation of the first program condition. Furthermore, the sense amplifier module 18 determines again whether the voltage at node SEN1 falls below a certain level at the end of the second sense period TSH. This allows the sense amplifier module 18 to determine whether the threshold voltage Vth of the memory cell transistor MT, which was determined to be above voltage VL by the first sense operation, falls below voltage VH. In other words, the sense amplifier module 18 can determine whether to apply the "0" program operation or the "1" program operation of the second program condition.

[0109] 1.2.2.2 Timing Chart The voltages of each wire during the verification operation will be explained using Figure 9. Figure 9 is a timing chart for explaining the verification operation using a semiconductor memory device according to the embodiment. Figure 9 shows the voltages of the source line SL, bit line BL, word line WL, signals TTI, TTL, XXL, and STB, bus LBUS, and node SEN1.

[0110] In the following, memory cell transistors MT that are the target of a write operation will also be called selected memory cell transistors MT. Memory cell transistors MT that are not the target of a write operation will also be called unselected memory cell transistors MT. Furthermore, the word line WL corresponding to a selected memory cell transistor MT will also be called selected word line WLsel. Furthermore, the word line WL corresponding to an unselected memory cell transistor MT will also be called unselected word line WLnsel.

[0111] At time t10, the row decoder module 17 applies the voltage VCGRV to the selected word line WLsel. Also, the row decoder module 17 applies the voltage VREAD to the non - selected word line WLnsel. The voltage VCGRV corresponds to, for example, the voltage VH. Also, the row decoder module 17 turns on the selected transistors ST1 and ST2.

[0112] Also, at time t10, the sequencer 15 turns on the transistor 36, for example, by setting the signal HLL to the “H” level. As a result of this, the voltage of the node SEN1 rises from the voltage VSS to the voltage VSENP.

[0113] At time t11, the sequencer 15 turns on the transistor 43, for example, by setting the signal LPC to the “H” level. As a result of this, the voltage of the bus LBUS rises from the voltage VSS to the voltage VPC. Note that the voltage VPC is a voltage lower than the voltage VDD (VPC < VDD). In the above manner, the sense amplifier module 18 charges the bus LBUS. That is, the sense amplifier module 18 performs LBUS pre - charge. Also, as a result of the rise in the voltage of the bus LBUS, the voltage of the node SEN1 rises from the voltage VSENP to the voltage VS (VS > VSENP) due to the influence of capacitive coupling.

[0114] At time t12, the sense amplifier module 18 charges the bit line BL. That is, the sense amplifier module 18 performs BL pre - charge. By the above processing, the voltage of the bit line BL rises from the voltage VSS to the voltage VBL. Also, the driver module 16 applies the voltage VSL to the source line SL, for example.

[0115] At time t13, the sequencer 15 changes the signal TTI from "L" level to "H" level. This turns transistor 50 from the off state to the on state. The sequencer 15 also changes the signal STB from "L" level to "H" level. This turns transistor 38 from the off state to the on state. As mentioned above, the voltage at node SEN1 is set to voltage VS. That is, the voltage at node SEN1 is higher than the judgment level. This turns transistor 39 into the on state. Therefore, while signals TTI and STB are set to "H" level, the bus LBUS conducts to node LOP, causing the voltage of the bus LBUS to drop to, for example, voltage VSS. In this way, the data "1" is stored in the latch circuit TDL.

[0116] At time t14, the sequencer 15 changes signals TTI and STB from "H" level to "L" level. Subsequently, for example, the sense amplifier module 18 performs LBUS precharging again by changing the voltage of signal TTL from voltage VSS to a voltage obtained by adding the threshold voltage VT to voltage VPC (VPC+VT). As a result, the voltage of node SEN1 rises to voltage VS as the voltage of the bus LBUS increases.

[0117] At time t15, the sense amplifier module 18 changes the voltage of the TTL signal from voltage (VPC+VT) to voltage VSS.

[0118] During the period from time t15 to t17, the sequencer 15 performs the first sense operation and the second sense operation. The period from time t15 to t16 corresponds to the first sense period TSL. The period from time t16 to t17 corresponds to the second sense period TSH.

[0119] At time t15, the sequencer 15 changes the voltage of the signal TTL from (VPC+VT) to voltage VSS. This puts the bus LBUS into a floating state. In Figure 9, the voltage of the bus LBUS, which is in a floating state during the first sense operation and the second sense operation, is shown by a dashed line. Subsequently, the sequencer 15 changes the voltage of the signal TTL from voltage VSS to a voltage obtained by adding the threshold voltage VT to the voltage VSEN (VSEN+VT). This causes transistor 51 to switch from the off state to the on state when the voltage of the bus LBUS falls below the voltage VSEN. Transistor 51 remains in the off state as long as the voltage of the bus LBUS is maintained above the voltage VSEN. Voltage VSEN is the voltage of the bus LBUS when the voltage of node SEN1 is at the determination level when node SEN1 and the bus LBUS are capacitively coupled.

[0120] During the period from time t15 to t17, the sequencer 15 sets signal XXL to the "H" level. As a result, transistor 35 is turned on during the period from time t15 to t17. In this state, if the threshold voltage of the memory cell transistor MT that is the target of the verification operation is greater than or equal to voltage VH, the memory cell transistor MT is turned off. As a result, almost no current flows from the bit line BL corresponding to the memory cell transistor MT to the source line SL. Also, if the threshold voltage of the memory cell transistor MT is greater than or equal to voltage VL but less than voltage VH, the memory cell transistor MT is weakly turned on. In this case, only a small amount of current flows from the bit line BL corresponding to the memory cell transistor MT to the source line SL.

[0121] From the above, during the period from time t15 to t16, if the threshold voltage of the memory cell transistor MT is above voltage VL (off-cell 1 in Figure 9), the charge stored in node SEN1 is hardly discharged. As a result, the bus LBUS, which is in a floating state, remains almost unchanged, similar to node SEN1. Therefore, transistor 51 is kept in the off state, and the data stored in the latch circuit TDL is maintained as "1" data. Also, if the threshold voltage of the memory cell transistor MT, which is the target of the verification operation, is below voltage VL (on-cell 1 in Figure 9), the memory cell transistor MT enters a strong ON state, and a significant current flows from the corresponding bit line BL to the source line SL. As a result, the voltage of node SEN1 falls below the judgment level. Furthermore, due to the capacitive coupling effect between the floating bus LBUS and node SEN1, the voltage of bus LBUS falls below voltage VSEN. As a result, transistor 51 changes from the off state to the ON state. Consequently, the data stored in the latch circuit TDL changes from "1" data to "0" data. While transistor 51 is ON, the bus LBUS is connected to the latch circuit TDL. However, in Figure 9, for the sake of simplicity, the voltage of the bus LBUS is shown as a dashed line instead of a solid line.

[0122] At time t16, the sequencer 15, for example, changes the voltage of the signal TTL from voltage (VSEN+VT) to voltage VSS. As a result, transistor 51 is turned off regardless of the data stored in the latch circuit TDL. That is, bus LBUS is set to a floating state regardless of the data stored in the latch circuit TDL. In this way, the result of determining whether the threshold voltage of the memory cell transistor MT has reached voltage VL is stored in the latch circuit TDL.

[0123] During the period from time t16 to t17, if the threshold voltage of the memory cell transistor MT is above voltage VH (off-cell 2 in Figure 9), the charge stored in node SEN1 is hardly discharged. Also, if the threshold voltage of the memory cell transistor MT subject to verification is below voltage VH (on-cell 2 in Figure 9), current flows from the bit line BL corresponding to the ON-state memory cell transistor MT to the source line SL, causing the voltage of node SEN1 to fall below the judgment level. Furthermore, due to the capacitive coupling between the floating bus LBUS and node SEN1, the voltage of bus LBUS falls below voltage VSEN. Since the voltage of signal TTL is set to voltage VSS, transistor 51 remains in the OFF state. Therefore, the data of latch circuit TDL is maintained.

[0124] At time t17, the sequencer 15 changes the signal XXL from "H" level to "L" level. This causes transistor 35 to switch from the ON state to the OFF state.

[0125] At time t18, for example, the sense amplifier module 18 performs LBUS pre-charging. As a result, the voltage of the bus LBUS becomes, for example, voltage VPC, regardless of the voltage of node SEN1 corresponding to the bus LBUS.

[0126] At time t19, the sequencer 15 changes the signal STB from "L" level to "H" level. This turns on transistor 38, causing the voltage of node SEN1 to strobe. If the voltage of node SEN1 is higher than the judgment level (off-cell 2 in Figure 9), transistor 39 is turned on. This causes bus LBUS to conduct to node LOP, and the voltage of bus LBUS drops to, for example, voltage VLOP. Note that in the verify operation, voltage VLOP is lower than voltage VSEN. On the other hand, if the voltage of node SEN1 falls below the judgment level (on-cell 2 in Figure 9), transistor 39 is turned off. This maintains the voltage of bus LBUS.

[0127] During the period from time t19 to t20, data based on the voltage of bus LBUS is stored in a latch circuit different from the latch circuit TDL. For example, this data is stored in the latch circuit SDL. More specifically, in storing data in the latch circuit SDL, the sequencer 15 sets the signal STI to the "H" level, for example. As a result, the data "0" is stored in the latch circuit SDL corresponding to on-cell 2 in Figure 9. Also, the data "1" is stored in the latch circuit SDL corresponding to off-cell 2 in Figure 9. In this way, the result of whether the threshold voltage of the memory cell transistor MT has reached voltage VH is stored in the latch circuit SDL.

[0128] At time t20, for example, the sense amplifier module 18 performs LBUS pre-charging.

[0129] At time t21, a recovery process is performed. As a result, the voltage of each wire is set to, for example, voltage VSS.

[0130] The sense amplifier module 18 uses the data stored in the latch circuits TDL and SDL, respectively, to determine the program operation and program conditions based on the difference between the target level and the threshold voltage of the memory cell transistor MT. As a result, in the next program operation, it applies either the first program condition for "0" program operation, the second program condition for "0" program operation, or "1" program operation.

[0131] The verification process is now complete.

[0132] 1.3 Effects According to this embodiment, the operating speed of the semiconductor memory device 1 can be improved. The effects of this embodiment are described below.

[0133] The semiconductor memory device 1 according to this embodiment includes a bit line BL, a memory cell transistor MT, and a sense amplifier module 18. The sense amplifier module 18 reads data from the memory cell transistor MT via the bit line BL. The sense amplifier module 18 includes a node SEN1 that can be electrically connected to the bit line BL, and a bus LBUS that is capacitively coupled to node SEN1. During a verify operation in which a voltage VCGRV is applied to the gate of the memory cell transistor MT and first data and second data are read in succession, the sense amplifier module 18 is configured to determine the first data based on the voltage of the bus LBUS that has decreased during the first sense period TSL, and to determine the second data based on the voltage of node SEN1 that has decreased during the second sense period TSH, which is continuous with the first sense period TSL, through capacitive coupling between node SEN1 and bus LBUS. With this configuration, the write speed of the semiconductor memory device 1 can be improved.

[0134] To elaborate, in the sense operation during the verify operation, if the bus LBUS is not in a floating state (as in the comparative example), the bus LBUS is not affected by capacitive coupling with the node in the sense circuit (sense node). As a result, the voltage of the bus LBUS does not change in accordance with the voltage of the sense node. Therefore, in the comparative example, the sense node voltage is strobed twice to store the results of the first sense operation and the second sense operation ("0" data or "1" data) in the latch circuit. During each strobe, the bus voltage drops from the "H" level to the "L" level or is maintained at the "H" level. Therefore, in the comparative example, a reset process is performed before the second sense operation, for example, to set the bus LBUS voltage to the "H" level.

[0135] According to this embodiment, during the verify operation, the bus LBUS is set to a floating state, so that the bus LBUS is affected by capacitive coupling with node SEN1. As a result, the voltage of the bus LBUS decreases in accordance with the voltage of node SEN1 that has decreased due to the first sense operation. Therefore, the result of the first sense operation can be stored in the latch circuit based on the voltage of the bus LBUS without performing a strobe. Furthermore, the second sense operation can be executed consecutively with the first sense operation without performing a process to reset the voltage of the bus LBUS between the first and second sense operations. Therefore, according to this embodiment, the speed of the verify operation, and consequently the speed of the write operation, can be improved.

[0136] 2 Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0137] 1...Semiconductor memory device, 2...Memory controller, 3...Memory system, 4...Host device, 10...Memory cell array, 11...Input / output circuit, 12...Logic control circuit, 13...Address register, 14...Command register, 15...Programmable logic controller, 16...Driver module, 17...Raw decoder module, 18...Sense amplifier module, 21...Processor, 22...Internal memory, 23...Buffer memory, 24...NAND I / F, 25...Host I / F, BLK...Block, SU...String unit, NS...NAND string, MT...Memory cell transistor, ST1, ST2...Selection transistor, BL...Bit line, WL...Word line, SGS, SGD...Selection gate line, SL...Source line, SAU...Sense amplifier unit, SA...Sense circuit, TDL, SDL, ADL, BDL, CDL, XDL...Latch circuit, LBUS...Bus.

Claims

1. Bit lines and, A memory cell transistor electrically connected to the aforementioned bit line, A sense amplifier module that reads data from the memory cell transistor via the bit line, Equipped with, The aforementioned sense amplifier module is A first node electrically connectable to the bit line, A second node is provided that can be capacity-coupled with the first node, Includes, The sense amplifier module, while applying a first voltage to the gate of the memory cell transistor, performs a read operation in which it reads out the first data and the second data in succession. In the first period of the consecutive first and second periods, the voltage of the second node decreases in accordance with the decrease in the voltage of the first node due to the capacitive coupling of the first node and the second node. Based on the voltage of the second node that decreased during the first period, the first data is determined. The second data is determined based on the voltage of the first node that decreased during the second period. It is configured in such a way. Semiconductor memory device.

2. The aforementioned sense amplifier module is A first transistor including a first end connected to the first node and a second end connected to the bit line, Furthermore, The aforementioned sense amplifier module is Throughout the first and second periods, the first transistor is turned on. It is configured in such a way. The semiconductor memory device according to claim 1.

3. The first data is determined based on whether the voltage of the second node is maintained at a higher voltage than the second voltage during the first period. The second data is determined based on whether the voltage of the first node is maintained at a higher voltage than the fourth voltage during the second period. The semiconductor memory device according to claim 2.

4. The aforementioned sense amplifier module is A first latch circuit having a second transistor with one end connected to the second node, Furthermore, The aforementioned sense amplifier module is During the first period, the second transistor is turned off when the voltage of the second node is higher than the second voltage, and the second transistor is turned on when the voltage of the second node is less than or equal to the second voltage, thereby determining the first data. The determined first data is stored in the first latch circuit. It is configured in such a way. The semiconductor memory device according to claim 3.

5. During the first period, a third voltage is applied to the gate of the second transistor, which is the second voltage plus the threshold voltage of the second transistor. The semiconductor memory device according to claim 4.

6. The aforementioned sense amplifier module is A third transistor having one end connected to the second node, A fourth transistor having a gate connected to the first node, one end connected to the other end of the third transistor, and the other end connected to the third node, The second latch circuit connected to the second node is Further including, The semiconductor memory device according to claim 5.

7. The sense amplifier module, in the read operation, after the second period has elapsed, When the third transistor is switched from the off state to the on state, the second node and one end of the fourth transistor are electrically connected. The system is configured to determine the second data by turning on the fourth transistor when the voltage of the first node is higher than the fourth voltage, and turning off the fourth transistor when the voltage of the first node is lower than or equal to the fourth voltage. The determined second data is stored in the second latch circuit. It is configured in such a way. The semiconductor memory device according to claim 6.

8. The aforementioned sense amplifier module is At the first time when the second period ends, if the voltage of the second node is maintained higher than the second voltage, the voltage of the first node becomes higher than the fourth voltage. At the first time step, if the voltage of the second node becomes less than or equal to the second voltage, the voltage of the first node becomes less than or equal to the fourth voltage. It is configured in such a way. The semiconductor memory device according to claim 7.

9. The sense amplifier module, in the read operation, before the first period, The voltage at the second node is set to a fifth voltage that is higher than the voltage at the third node. When the third transistor is switched from the off state to the on state, the second node and one end of the fourth transistor are electrically connected, and the voltage at the second node decreases. Data corresponding to the voltage of the second node is stored in the first latch circuit in advance. It is configured in such a way. The semiconductor memory device according to claim 6.

10. During the second period, a voltage lower than the third voltage is applied to the gate of the second transistor. The semiconductor memory device according to claim 9.

11. The capacitive coupling between the first node and the second node is due to the capacitance between the wires. The semiconductor memory device according to claim 1.

12. The first node and the second node are connected via a capacitive element. The semiconductor memory device according to claim 1.

13. The sense amplifier module uses the first data and the second data to determine whether to increase the threshold voltage of the memory cell transistor in the next program operation, and, if so, the amount by which the threshold voltage of the memory cell transistor should be increased. The semiconductor memory device according to claim 1.

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