Package-on-package structure

Abstract

The utility model discloses a package-on-package structure. The package-on-package structure comprises a substrate; the chip stacking structure is located on the upper surface of the substrate and comprises a plurality of first semiconductor chips stacked in sequence, each first semiconductor chip comprises a first surface, a second surface and a side face located between the first surface and the second surface, the first surface and the second surface are opposite, an internal heat dissipation metal layer is arranged in each first semiconductor chip, and part of the outer side face of the internal heat dissipation metal layer is exposed out of the side face; the edge of the first surface is provided with a groove, and the groove exposes a part of the upper surface of the internal heat dissipation metal layer and penetrates through a part of the side surface of the first semiconductor chip; the heat conduction metal sheets are mounted in the groove, on the outer side surface of the internal heat dissipation metal layer and on the side surface of the first semiconductor chip; the heat dissipation covers are mounted on the top surface and the side surface of the chip stacking structure, and the heat dissipation covers are in contact with the heat conduction metal sheets. The heat dissipation efficiency of the first semiconductor chip located in the middle of the chip stacking structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to a stacked packaging structure. Background Technology

[0002] To achieve better performance, maintain a smaller size, and lower power consumption, existing packaging technologies have evolved from early 2D packaging towards 2.5D stacked packaging and 3D stacked packaging.

[0003] In 2.5D and 3D stacked packaging, chip stacking presents a significant challenge to heat dissipation. This is because a chip stack structure contains multiple semiconductor chips arranged from bottom to top, and each semiconductor chip dissipates heat when it is working. This leads to heat accumulation and a significant increase in heat flux density per unit area. If heat dissipation cannot be effectively achieved, it will inevitably lead to problems with the thermal reliability of the semiconductor chips.

[0004] The current mainstream heat dissipation method involves attaching a heat sink or heat plate to the top of the chip stack structure. However, this method is only highly efficient at dissipating heat from the semiconductor chips at the top of the stack. It is less efficient at dissipating heat from the semiconductor chips in the middle of the stack, preventing the heat generated by these chips from being effectively dissipated. This reduces the overall heat dissipation efficiency of the stack and affects the performance of the packaging structure. Summary of the Invention

[0005] The problem this application aims to solve is how to improve the heat dissipation efficiency of semiconductor chips in the middle of a chip stack structure.

[0006] To address the above problems, this application provides a stacked packaging structure, including:

[0007] A substrate, the substrate including opposing upper and lower surfaces;

[0008] A chip stack structure located on the upper surface of the substrate and electrically connected to the substrate, the chip stack structure comprising a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the upper surface of the substrate, each first semiconductor chip comprising a first surface and a second surface opposite to each other and a side surface located between the first surface and the second surface, each first semiconductor chip having an internal heat dissipation metal layer, and the side surface of the first semiconductor chip exposing the outer side surface of the internal heat dissipation metal layer, the edge of the first surface of the first semiconductor chip having a groove, the groove exposing a portion of the upper surface of the internal heat dissipation metal layer and penetrating a portion of the side surface of the first semiconductor chip; each first semiconductor chip further comprising a thermally conductive metal sheet attached to the groove, the outer side surface of the internal heat dissipation metal layer, and the side surface of the first semiconductor chip;

[0009] A heat dissipation cover is attached to the top surface and side surface of the chip stack structure, and the heat dissipation cover is in contact with the thermally conductive metal sheet.

[0010] In one optional embodiment, the first semiconductor chip includes a semiconductor substrate, a device layer located on the upper surface of the semiconductor substrate, and a wiring layer located on the upper surface of the device layer. The device layer includes a semiconductor device, and the wiring layer includes metal lines electrically connected to the semiconductor device. The upper surface of the wiring layer is a first surface of the first semiconductor chip, and the lower surface of the semiconductor substrate is a second surface of the first semiconductor chip.

[0011] In one optional embodiment, the internal heat dissipation metal layer is located in the semiconductor substrate, or in the device layer, or in the wiring layer.

[0012] In an optional embodiment, the internal heat dissipation metal layer is located in at least two of the semiconductor substrate, the device layer, and the wiring layer.

[0013] In one optional embodiment, the semiconductor substrate has a via connection structure, and the lower surface of the semiconductor substrate exposes the lower end surface of the via connection structure; the device layer further includes a bottom dielectric layer located on the upper surface of the semiconductor substrate, the semiconductor device is located in the bottom dielectric layer, and the bottom dielectric layer also has a metal connection structure electrically connected to the semiconductor device; the wiring layer further includes an interlayer dielectric layer, the metal lines are located in the interlayer dielectric layer, and a portion of the metal lines are electrically connected to the metal connection structure and the via connection structure, and the interlayer dielectric layer and the metal lines are a multilayer stacked structure.

[0014] In one alternative embodiment, the semiconductor device is one or a combination of several of the following: bipolar transistors, field-effect transistors, insulated-gate bipolar transistors, and memory cells or memory arrays.

[0015] In an optional embodiment, the semiconductor device further includes one or a combination of diodes, resistors, capacitors, and inductors.

[0016] In an optional embodiment, in addition to being attached to the groove, the outer surface of the inner heat dissipation metal layer, and the side surface of the first semiconductor chip, the thermally conductive metal sheet is also attached to a portion of the first surface of the first semiconductor chip; the thermally conductive metal sheet is attached to the groove, the outer surface of the inner heat dissipation metal layer, and the side surface and portion of the first surface of the first semiconductor chip through a first thermal interface material or a first thermally conductive welding material.

[0017] In an optional embodiment, the upper surface or first surface of the interlayer dielectric layer has a welding protrusion, which is electrically connected to the metal circuit. The thermally conductive metal sheet mounted on a portion of the first surface of the first semiconductor chip is located on the upper surface of the interlayer dielectric layer on one side of the welding protrusion, and the upper surface of the portion of the thermally conductive metal sheet is lower than the top surface of the welding protrusion before welding. When multiple first semiconductor chips are stacked sequentially in the chip stacking structure along a direction perpendicular to the upper surface of the substrate, the first surface of each first semiconductor chip or the upper surface of the interlayer dielectric layer faces downward. The welding protrusion on the first surface of the upper first semiconductor chip is welded to the corresponding through-hole connection structure exposed on the second surface of the adjacent lower first semiconductor chip. The chip stacking structure also includes a bottom filler layer filled between the upper and lower first semiconductor chips.

[0018] In an optional embodiment, the thermally conductive metal sheet is only attached to the groove, the outer surface of the inner heat dissipation metal layer, and the side surface of the first semiconductor chip; the thermally conductive metal sheet is attached to the groove, the outer surface of the inner heat dissipation metal layer, and the side surface of the first semiconductor chip through a first thermal interface material or a first thermally conductive welding material.

[0019] In an optional embodiment, the heat sink is attached to the top surface and side surface of the chip stack structure by means of a second thermal interface material or a second thermally conductive soldering material; the heat sink includes a first part and a second part protruding from the lower surface of the first part, the lower surface of the first part is attached to the top surface of the chip stack structure, and the inner surface of the second part is attached to the side surface of the chip stack structure.

[0020] In an optional embodiment, the plurality of first semiconductor chips in the chip stack structure may have the same or different functions.

[0021] In an optional embodiment, the device further includes a second semiconductor chip mounted on the upper surface of a substrate on one side of the chip stack structure, the second semiconductor chip being electrically connected to the substrate.

[0022] The advantages of the technical solution in this application are:

[0023] In the stacked packaging structure described in the foregoing embodiments of this application, each of the first semiconductor chips in the chip stack structure has an internal heat dissipation metal layer, and the side of the first semiconductor chip exposes the outer side of the internal heat dissipation metal layer. The edge of the first surface of the first semiconductor chip has a groove, which exposes a portion of the upper surface of the internal heat dissipation metal layer and penetrates a portion of the side surface of the first semiconductor chip. Each first semiconductor chip also includes a thermally conductive metal sheet attached to the groove, the outer side surface of the internal heat dissipation metal layer, and the side surface of the first semiconductor chip. Therefore, whether it is the first semiconductor chip located at the top of the chip stack structure or the first semiconductor chip located in the middle or bottom of the chip stack structure... The heat generated inside the chip can be transferred to the heat sink for release through the internal heat dissipation metal layer and the thermally conductive metal sheet (in particular, through the cooperation of the internal heat dissipation metal layer and the thermally conductive metal sheet, the area of ​​the heat conduction channel or heat dissipation channel of the first semiconductor chip gradually increases from the inside to the outside, so that the heat generated inside the first semiconductor chip can be released effectively and quickly. At the same time, the internal heat dissipation metal layer and the thermally conductive metal sheet are set at the edge or blank area of ​​the first semiconductor chip, without occupying too much of the effective area of ​​the first semiconductor chip), thereby improving the overall heat dissipation efficiency of the chip stack structure, especially improving the heat dissipation efficiency of the first semiconductor chip located in the middle of the chip stack structure, and improving the performance of the packaging structure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the stacked packaging structure in one embodiment of this application;

[0025] Figures 2-5 This is a schematic diagram of the structure of the first semiconductor chip formation process in one embodiment of this application;

[0026] Figures 6-7 This is a schematic diagram of the magnified structure of the first semiconductor chip in one embodiment of this application;

[0027] Figure 8 This is an enlarged structural diagram of the first semiconductor chip in another embodiment of this application;

[0028] Figure 9 This is an enlarged structural schematic diagram of the first semiconductor chip in yet another embodiment of this application;

[0029] Figure 10 This is an enlarged structural schematic diagram of the first semiconductor chip in yet another embodiment of this application;

[0030] Figure 11 This is a top view of the structure of the first semiconductor chip in another embodiment of this application;

[0031] Figure 12 for Figure 11 Schematic diagram of the cross-sectional structure along the cutting line AA1;

[0032] Figure 13 for Figure 11 Schematic diagram of the cross-sectional structure along the cutting line BB1;

[0033] Figures 14-15 This is a schematic diagram of the stacked packaging structure in another embodiment of this application. Detailed Implementation

[0034] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and thickness should be included.

[0035] This application first provides a stacked packaging structure according to an embodiment, referencing... Figure 1 and combined Figure 4 and Figure 5 ,in, Figure 4 for Figure 1 A cross-sectional view of a first semiconductor chip 201 without a heat-conducting metal sheet attached. Figure 5 for Figure 1 A cross-sectional view of a first semiconductor chip 201 after mounting a thermally conductive metal sheet 203. The stacked package structure includes:

[0036] Substrate 101, the substrate 101 includes opposing upper and lower surfaces;

[0037] A chip stacking structure 20 is located on the upper surface of the substrate 101. The chip stacking structure 20 includes a plurality of first semiconductor chips 201 stacked sequentially along a direction perpendicular to the upper surface of the substrate 101. Each first semiconductor chip 201 includes a first surface and a second surface opposite to each other, and a side surface located between the first surface and the second surface. Each first semiconductor chip 201 has an internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201 exposes the outer side surface of the internal heat dissipation metal layer 203. The edge of the first surface of the first semiconductor chip 201 has a groove 213 (see reference). Figure 4 The groove 213 exposes a portion of the upper surface of the internal heat dissipation metal layer 203 and extends through a portion of the side surface of the first semiconductor chip 201; each of the first semiconductor chips 201 also includes a thermally conductive metal sheet 209 attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201 (see reference). Figure 1 and Figure 5 );

[0038] A heat dissipation cover 301 is attached to the top surface and side surface of the chip stack structure 20, and the heat dissipation cover 301 is in contact with the thermally conductive metal sheet 209.

[0039] Specifically, the substrate 101 serves as a support and connection carrier in the packaging process. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure), and the lower surface of the substrate 101 has a plurality of discrete second pads (not shown in the figure). The substrate 101 has connection lines (not shown in the figure). Some of the connection lines can be used for electrical connections between the first pads on the upper surface of the substrate 101 and the corresponding second pads on the lower surface of the substrate 101. Some of the connection lines can also be used for electrical connections between some of the first pads on the upper surface of the substrate 101, and some of the connection lines can also be used for electrical connections between some of the second pads on the lower surface of the substrate 101. The first pads on the upper surface of the substrate 101 can be electrically connected to a chip stack structure or other devices mounted on the substrate. External protrusions 102 can be formed on the second pads on the lower surface of the substrate 101. The external protrusions 102 are used for connection with other devices, other substrates, or packaging structures. In one embodiment, the first pad, the second pad, and the connecting line are made of metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The external protrusion 102 is made of tin or a tin alloy, specifically one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. In one embodiment, the substrate 101 can be a silicon substrate, an RDL (Re-distribution Layer) substrate, a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a flexible printed circuit board (FPC). In one embodiment, the substrate 101 can be a single-layer board or a multilayer board. In one embodiment, the substrate 101 can serve as an interposer.

[0040] The chip stacking structure 20 includes a plurality of first semiconductor chips 201 stacked sequentially along a direction perpendicular to the upper surface of the substrate 101. The number of first semiconductor chips 201 can be two, three, four or more. Figure 1 The example described uses a chip stack structure 20 having four first semiconductor chips 201 as an example.

[0041] In one embodiment, the bottommost first semiconductor chip 201 of the chip stack structure 20 is electrically connected to the substrate 101, and the upper first semiconductor chip 201 of the chip stack structure 20 is electrically connected to the lower first semiconductor chip 201.

[0042] The plurality of first semiconductor chips 201 in the chip stack structure 20 may have the same or different functions. In one embodiment, when the plurality of first semiconductor chips 201 have the same function, the plurality of first semiconductor chips 201 have the same internal structure. In another embodiment, when the plurality of first semiconductor chips 201 have the same function, the plurality of first semiconductor chips 201 have different internal structures.

[0043] Depending on their functions, the first semiconductor chip 201 may include logic chips and / or memory chips. In some embodiments, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), resistive random access memory (RRAM), or non-volatile memory chips (such as flash memory).

[0044] In one embodiment, all the first semiconductor chips 201 in the chip stack structure 20 have the same function. In a specific embodiment, all the first semiconductor chips 201 in the chip stack structure 20 are memory chips, such as... Figure 1 In the chip stack structure 20 described herein, all four first semiconductor chips 201 are memory chips. In other embodiments, all first semiconductor chips 201 in the chip stack structure 20 may also be logic chips.

[0045] In another embodiment, the functions of some of the first semiconductor chips 201 in the chip stack structure 20 differ from the functions of other first semiconductor chips 201. In a specific embodiment, one or two first semiconductor chips 201 located at the bottom layer of the chip stack structure 20 are logic chips, while the other first semiconductor chips located at the upper layers of the chip stack structure 20 are memory chips. The logic chips are used to control and manage the data storage, reading (and deletion) processes of the memory chips, for example... Figure 1 In the chip stacking structure 20 described above, the bottommost first semiconductor chip 201 is a logic chip, and the three upper first semiconductor chips 201 are memory chips.

[0046] In this application, each of the first semiconductor chips 201 has an internal heat dissipation metal layer 203, and the side of the first semiconductor chip 201 exposes the outer side of the internal heat dissipation metal layer 203. The edge of the first surface of the first semiconductor chip 201 has a groove 213 (see reference). Figure 4 The groove 213 exposes a portion of the upper surface of the internal heat dissipation metal layer 203 and extends through a portion of the side surface of the first semiconductor chip 201; each of the first semiconductor chips 201 also includes a thermally conductive metal sheet 209 attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201 (see reference). Figure 1 and Figure 5 Therefore, the heat generated inside the first semiconductor chip 201 located at the top of the chip stack structure 20 or in the middle and bottom of the chip stack structure 20 can be transferred to the heat sink 301 for release through the internal heat dissipation metal layer 203 and the thermally conductive metal sheet 209. (In particular, through the cooperation of the internal heat dissipation metal layer 203 and the thermally conductive metal sheet 209, the area of ​​the heat conduction channel or heat dissipation channel of the first semiconductor chip 201 gradually increases from the inside to the outside, so that the heat generated inside the first semiconductor chip 201 can be released effectively and quickly. At the same time, the internal heat dissipation metal layer 203 and the thermally conductive metal sheet 209 are set at the edge or blank area of ​​the first semiconductor chip, and will not occupy too much of the effective area of ​​the first semiconductor chip.) This improves the overall heat dissipation efficiency of the chip stack structure, especially the heat dissipation efficiency of the first semiconductor chip located in the middle of the chip stack structure, and improves the performance of the packaging structure.

[0047] The heat sink 301 is formed of a material with high thermal conductivity. In one embodiment, the material with high thermal conductivity includes metals (e.g., copper, aluminum, gold, nickel, steel, or stainless steel) or carbon-containing materials (e.g., graphite, graphene, or carbon nanotubes). In one embodiment, the heat sink 301 is attached to the top and side surfaces of the chip stack structure 20 via a second thermal interface material or a second thermally conductive soldering material 302. The second thermal interface material (TIM) can be thermally conductive silicone grease, thermally conductive gel, thermosetting polymer, thermally conductive pad, or thermally conductive phase change material, and the second thermally conductive soldering material can be solder. In one embodiment, continuing to refer to... Figure 1 The heat sink 301 includes a first part 301a and a second part 301b protruding from the lower surface of the first part 301a. The lower surface of the first part 301a is attached to the top surface of the chip stack structure 20, and the inner surface of the second part 301b is attached to the side surface of the chip stack structure 20.

[0048] The first semiconductor chip 201 is fabricated using semiconductor integration technology to improve manufacturing efficiency. In a specific embodiment, the fabrication process of the first semiconductor chip 201 includes: firstly, referring to... Figure 2 A wafer 220 (or semiconductor substrate) is provided, the wafer 220 including a plurality of chip regions 21 and dicing regions 22 located between adjacent chip regions 21, the plurality of chip regions 21 being arranged in rows and columns. Figure 2 The example uses two chip regions 21 and a dicing channel region 22 between two adjacent chip regions 21 as illustrations; please refer to [link / reference] for further details. Figure 2 A first semiconductor chip is fabricated on the chip region 21. In a specific embodiment, refer to... Figure 6 , Figure 6 This is an enlarged structural schematic diagram of the first semiconductor chip 201. The first semiconductor chip 201 fabricated on the chip region 21 may include: a semiconductor substrate 200 (the semiconductor substrate 200 is the aforementioned wafer 220), a device layer formed on the upper surface of the semiconductor substrate 200, and a wiring layer formed on the upper surface of the device layer. The device layer includes a bottom dielectric layer 204 and a semiconductor device 202 formed in the bottom dielectric layer 204. The wiring layer includes an interlayer dielectric layer 206 and metal lines 207 formed in the interlayer dielectric layer 206. The metal lines 207 are electrically connected to the semiconductor device 202. An internal heat dissipation metal layer 203 is also formed in the interlayer dielectric layer 206 of the wiring layer. The internal heat dissipation metal layer 203 is located in the edge region of the chip region 21 and spans the dicing area 22 (reference). Figure 2 Next, refer to Figure 3A first cut is performed, forming a groove 213 in the interlayer dielectric layer. The groove 213 exposes the entire upper surface of the portion of the internal heat dissipation metal layer 203 above the cut channel area 22 and a portion of the upper surface of the internal heat dissipation metal layer 203 above the chip areas 21 on both sides of the cut channel area 22; then, referring to... Figure 4 A second dicing is performed, cutting the wafer along dicing zone 22 to form a plurality of discrete first semiconductor chips 201. The edges of the first surfaces of the first semiconductor chips 201 have grooves 213 (see reference). Figure 6 (The first surface is the side where the interlayer dielectric layer 206 is located), the groove 213 exposes part of the upper surface of the internal heat dissipation metal layer 203 and penetrates part of the side surface of the first semiconductor chip 201; Reference Figure 5 or Figure 7 A thermally conductive metal sheet 209 is attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201. The thermally conductive metal sheet 209 is made of a high thermal conductivity metal or alloy, such as one or more of copper, aluminum, gold, nickel, steel, or stainless steel. In one embodiment, the thermally conductive metal sheet 209 is attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201 via a first thermal interface material or a first thermally conductive soldering material (not shown in the figure). The first thermal interface material can be thermally conductive silicone grease, thermally conductive gel, thermosetting polymer material, thermally conductive pad, or thermally conductive phase change material, and the first thermally conductive soldering material can be solder.

[0049] In one embodiment, the wafer 220 or the semiconductor substrate 200 is made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi) and silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other group III-V compounds. The semiconductor substrate 200 can also be implanted with certain dopant ions to change its electrical parameters according to design requirements. In one embodiment, a shallow trench isolation structure is also formed within the semiconductor substrate 200. This shallow trench isolation structure is used to isolate different semiconductor devices 202 and prevent electrical connections between different semiconductor devices 202. The material of the shallow trench isolation structure can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0050] In one embodiment, reference continues Figure 6 or Figure 7The semiconductor substrate 200 has a through-hole connection structure 208, such as a through-silicon via (TSV) structure. The lower surface of the semiconductor substrate 200 exposes the lower end surface of the through-hole connection structure 208, and the upper end surface of the through-hole connection structure 208 is electrically connected to the semiconductor device 202 or the metal line 207.

[0051] In one embodiment, reference continues Figure 6 or Figure 7 The bottom dielectric layer 204 further includes a metal connection structure 205 electrically connected to the semiconductor device 202. The bottom dielectric layer 204 can be a single-layer or multi-layer stacked structure. The material of the bottom dielectric layer 204 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The material of the metal connection structure 205 is one or more (at least two) of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. It should be noted that, in one embodiment, in addition to being located in the bottom dielectric layer 204, a portion of the semiconductor device 202 may also be located in the semiconductor substrate 200.

[0052] The semiconductor device 202 can be any of the various devices fabricated using existing semiconductor integration processes, including passive and / or active devices. In one embodiment, the semiconductor device 202 is one or a combination of several of the following: bipolar transistors, field-effect transistors, insulated-gate bipolar transistors, and memory cells or memory arrays. In other embodiments, the semiconductor device 202 further includes one or a combination of several of the following: diodes, resistors, capacitors, and inductors.

[0053] In one specific embodiment, the semiconductor device 202 is a field-effect transistor (FET). The FET includes a gate 202a located on the upper surface of the semiconductor substrate 200, and a source 202b and a drain 202c located on both sides of the gate 202a in the semiconductor substrate 200. The FET also includes sidewalls located on the sidewall surface of the gate 202a. The FET may include a metal-oxide-semiconductor field-effect transistor (MOSFET) or a fin field-effect transistor (FinFET). The MOSFET may include PMOS transistors and NMOS transistors. In one embodiment, when the underlying dielectric layer 204 also has a metal connection structure 205 electrically connected to the semiconductor device 202, the metal connection structure 205 can be a metal wire or metal plug electrically connected to the gate 202a, source 202b or drain 202c of the field-effect transistor.

[0054] In another specific embodiment, the semiconductor device 202 is a bipolar junction transistor (BJT), commonly known as a transistor, which is an electronic device with three terminals. It is made of three semiconductors with different doping levels in a semiconductor substrate, including an emitter, a base, and a collector. The base has a different doping type than the emitter and collector. For example, in an NPN transistor, the base is P-type doped, while the emitter and collector are N-type doped. In one embodiment, when the bottom dielectric layer 204 also has a metal connection structure 205 electrically connected to the semiconductor device 202, the metal connection structure 205 can be a metal wire or metal plug electrically connected to the emitter, base, or collector of the bipolar transistor.

[0055] In another specific embodiment, the semiconductor device 202 is an Insulated-Gate Bipolar Transistor (IGBT). The IGBT includes a gate, collector, and emitter with different doping levels. The gate has a different doping type than the emitter and collector. For example, in an N-type IGBT, if the gate is P-type, the emitter and collector are N-type doped. In one embodiment, when the underlying dielectric layer 204 also has a metal connection structure 205 electrically connected to the semiconductor device 202, the metal connection structure 205 can be a metal wire or metal plug electrically connected to the gate, collector, or emitter of the bipolar transistor.

[0056] In another specific embodiment, the semiconductor device 202 is a memory cell or memory array, which includes a memory cell or memory array of Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Magnetoresistive Random Access Memory (MRAM), Phase-change Memory (PRAM), Resistive Random Access Memory (RRAM), or a non-volatile memory chip (such as flash memory). In one embodiment, when the underlying dielectric layer 204 also has a metal connection structure 205 electrically connected to the semiconductor device 202, the metal connection structure 205 can be one or more of word lines, bit lines, source lines, or other functional connection lines electrically connected to the memory cell or memory array.

[0057] In another specific embodiment, when the semiconductor device 202 is a diode, resistor, capacitor, or inductor, the diode, resistor, capacitor, and inductor may each include a first terminal and a second terminal. For example, the P-terminal of a diode is the first terminal, and the N-terminal is the second terminal; similarly, the two plates of a capacitor are the first terminal and the second terminal, respectively. In one embodiment, when the underlying dielectric layer 204 also has a metal connection structure 205 electrically connected to the semiconductor device 202, the metal connection structure 205 may be a metal wire or a metal plug electrically connected to the first terminal or the second terminal.

[0058] In one embodiment, reference continues Figure 6 or Figure 7The interlayer dielectric layer 206 and the metal circuit 207 are multi-layer (≥ two-layer) stacked structures, and the number of layers of the metal circuit 207 is the same as the number of layers of the interlayer dielectric layer 206, for example, as Figure 6 or Figure 7 As shown, the interlayer dielectric layer 206 has a two-layer stacked structure, and the corresponding metal circuit 207 also has a two-layer stacked structure. In one embodiment, the metal circuit 207 may include one or more of the following: metal wire, metal plug, damask structure, or double damask structure. In one embodiment, the material of the interlayer dielectric layer 206 is one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, or low dielectric constant material; and the material of the metal circuit 207 is one or more (two or more) of the following: Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0059] In one specific embodiment, reference continues to be made to Figure 6 The internal heat-dissipating metal layer 203 is formed in the interlayer dielectric layer 206. The side surface of the interlayer dielectric layer 206 exposes the outer side surface of the internal heat-dissipating metal layer 203. The groove 213 is formed in the interlayer dielectric layer 206, exposing a portion of the upper surface of the internal heat-dissipating metal layer 203 and penetrating a portion of the side surface of the interlayer dielectric layer 206. (Reference) Figure 7 Thermally conductive metal sheets 209 are attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surfaces of the first semiconductor chip 201 (the side surfaces of the bottom dielectric layer 204 and the semiconductor substrate 200, and part of the interlayer dielectric layer 206). On one hand, the combination of the internal heat dissipation metal layer 203 and the thermally conductive metal sheets 209 effectively and quickly transfers the heat generated inside the first semiconductor chip 201 to the heat sink 301 for release. On the other hand, the thickness of the internal heat dissipation metal layer 203 in the interlayer dielectric layer 206 is the same as the thickness of the metal circuit 207 in the interlayer dielectric layer 206, and both have the same structure (e.g., both are one or a combination of metal wires, metal plugs, damask structures, or double damask structures). Therefore, during the fabrication of the first semiconductor chip 201, the internal heat dissipation metal layer 203 and the metal circuit 207 can be formed simultaneously using semiconductor fabrication processes, eliminating the need for additional processes, saving process steps, and reducing costs.

[0060] The internal heat dissipation metal layer 203 is a metal with high thermal conductivity. In one embodiment, the material of the internal heat dissipation metal layer 203 is one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0061] In a specific embodiment, when the first semiconductor chip 201 is square, the first semiconductor chip 201 includes four sides, and the internal heat dissipation metal layer 203 is exposed from one or more of the sides. Specifically, the internal heat dissipation metal layer 203 can be exposed from one, two, three or four of the sides.

[0062] The specific distribution and structure of the internal heat dissipation metal layer 203 in the first semiconductor chip 201 can vary in several ways. The specific distribution and structure of the internal heat dissipation metal layer 203 in the first semiconductor chip 201 will be described in different embodiments below.

[0063] In one specific embodiment, reference is made to Figure 8 The internal heat dissipation metal layer 203 is formed in the semiconductor substrate 203 of the first semiconductor chip 201. The lower surface and side surface of the semiconductor substrate 203 expose the lower surface and outer surface of the internal heat dissipation metal layer 203. The groove 213 is formed in the interlayer dielectric layer 206 and the bottom dielectric layer 204. The groove 213 exposes part of the upper surface of the internal heat dissipation metal layer 203 and penetrates part of the side surface of the interlayer dielectric layer 206 and the bottom dielectric layer. Thermally conductive metal sheets are mounted in the groove 213, on the outer surface of the internal heat dissipation metal layer 203, and on the side surface of the first semiconductor chip 201. Figure 7 (Similar to the illustration, no further illustration is needed). On one hand, the combination of the internal heat dissipation metal layer 203 and the heat-conducting metal sheet can effectively and quickly transfer the heat generated inside the first semiconductor chip 201 to the heat sink 301 for release. On the other hand, the thickness of the internal heat dissipation metal layer 203 on the semiconductor substrate 203 is the same as the thickness of the through-hole connection structure 208 on the semiconductor substrate 203, and both have the same structure (e.g., both are through-hole structures). Therefore, when manufacturing the first semiconductor chip 201, the internal heat dissipation metal layer 203 and the through-hole connection structure 208 can be formed simultaneously through semiconductor manufacturing processes, without the need for additional processes, saving process steps and costs.

[0064] In another specific embodiment, please refer to Figure 9The internal heat dissipation metal layer 203 is formed in the device layer of the first semiconductor chip 201, specifically in the bottom dielectric layer 204 of the device layer. The side surface of the bottom dielectric layer 204 exposes the outer surface of the internal heat dissipation metal layer 203. A groove 213 is formed in the interlayer dielectric layer 206, exposing a portion of the upper surface of the internal heat dissipation metal layer 203 and penetrating a portion of the side surface of the interlayer dielectric layer 206. Thermally conductive metal sheets are mounted in the groove 213, on the outer surface of the internal heat dissipation metal layer 203, and on the side surface of the first semiconductor chip 201. Figure 7 (Similar to the illustration, no further illustration is needed). On one hand, the combination of the internal heat dissipation metal layer 203 and the heat-conducting metal sheet can effectively and quickly transfer the heat generated inside the first semiconductor chip 201 to the heat sink 301 for release. On the other hand, the thickness of the internal heat dissipation metal layer 203 in the bottom dielectric layer 204 is the same as the thickness of the metal connection structure 205 in the bottom dielectric layer 204, and both have the same structure (e.g., both are metal plug structures). Therefore, when manufacturing the first semiconductor chip 201, the internal heat dissipation metal layer 203 and the metal connection structure 205 can be formed simultaneously through semiconductor manufacturing processes, without the need for additional processes, saving process steps and costs.

[0065] In other embodiments, the internal heat dissipation metal layer 203 may be located in at least two of the semiconductor substrate 200, the device layer, and the wiring layer. In addition to achieving the technical effects of the foregoing embodiments (such as saving process steps and reducing costs), since the internal heat dissipation metal layer 203 may be located in at least two of the semiconductor substrate 200, the device layer, and the wiring layer, the internal heat dissipation metal layer 203 can simultaneously remove most of the heat generated in the semiconductor substrate 200, the device layer, and the wiring layer, thereby further improving the heat dissipation efficiency of the first semiconductor chip 201.

[0066] In one specific embodiment, please refer to Figure 10The internal heat dissipation metal layer 203 is formed in the semiconductor substrate 200, the device layer, and the wiring layer. Specifically, the internal heat dissipation metal layer 203 includes a first internal heat dissipation metal layer 203a formed in the semiconductor substrate 200, a second internal heat dissipation metal layer 203b formed in the device layer, and a third internal heat dissipation metal layer 203c formed in the wiring layer. Specifically, the outer side and lower surface of the first internal heat dissipation metal layer 203a are exposed on the side and lower surface of the semiconductor substrate 200. The second internal heat dissipation metal layer 203b is formed in the bottom dielectric layer 204 in the device layer, and the side of the bottom dielectric layer 204 exposes the outer side of the second internal heat dissipation metal layer 203b. The third internal heat dissipation metal layer 203c is formed in the interlayer dielectric layer 206 in the wiring layer, and the side of the interlayer dielectric layer 206 exposes the outer side of the third internal heat dissipation metal layer 203c. The groove 213 is formed in the interlayer dielectric layer 206, exposing a portion of the upper surface of the inner heat dissipation metal layer 203 and penetrating a portion of the side surface of the interlayer dielectric layer 206. Thermally conductive metal sheets are mounted in the groove 213, on the outer surface of the inner heat dissipation metal layer 203, and on the side surface of the first semiconductor chip 201. Figure 7 (Similar to the illustration, no further illustration is needed). On one hand, the combination of the internal heat dissipation metal layer 203 and the heat-conducting metal sheet can effectively and quickly transfer the heat generated inside the first semiconductor chip 201 to the heat sink 301 for release; on the other hand, the through-hole connection structure 208, the second internal heat dissipation metal layer 203b, and the third internal heat dissipation metal layer 203c can be formed simultaneously with the through-hole connection structure 208, the metal connection structure 205, and the metal line 207 through semiconductor manufacturing processes, respectively, without the need for additional processes, saving process steps and costs.

[0067] In another specific embodiment, the internal heat dissipation metal layer 203 may consist only of a first internal heat dissipation metal layer 203a located in the semiconductor substrate 200 and a second internal heat dissipation metal layer 203b located in the device layer.

[0068] In another specific embodiment, the internal heat dissipation metal layer 203 may include only a first internal heat dissipation metal layer 203a located in the semiconductor substrate 200 and a third internal heat dissipation metal layer 203c located in the wiring layer.

[0069] In another specific embodiment, the internal heat dissipation metal layer 203 may consist only of a second internal heat dissipation metal layer 203b located in the device layer and a third internal heat dissipation metal layer 203c located in the wiring layer.

[0070] In one embodiment, reference continues Figure 1 The upper surface of the substrate 101 is further mounted with a second semiconductor chip 401. The second semiconductor chip 401 can be a logic chip (such as a GPU chip or CPU disk) or a memory chip. The second semiconductor chip 401 is electrically connected to the substrate 101. Specifically, the second semiconductor chip 401 is soldered to and electrically connected to the substrate 101 through solder bumps 402. The second semiconductor chip 401 can also be electrically connected to the chip stack structure 20. In a specific embodiment, the second semiconductor chip 401 can be electrically connected to the first semiconductor chip 201 at the bottom layer of the chip stack structure 20 through some connection lines in the substrate 101.

[0071] In one embodiment, reference continues Figure 1 When several first semiconductor chips 201 are stacked to form a chip stack structure 20, the upper first semiconductor chip 201 and the lower first semiconductor chip 201 are soldered and electrically connected through solder balls 210 (micro solder balls), and the bottom first semiconductor chip 201 is soldered and electrically connected to the substrate 101 through solder balls 210 (C4 solder balls). A bottom filler layer 211 may also be filled between the upper and lower first semiconductor chips 201 and between the bottom first semiconductor chip 201 and the upper surface of the substrate 101.

[0072] In one embodiment, the material of the bottom filler layer 211 is a liquid epoxy molding compound (LMC). In other embodiments, the material of the bottom filler layer 211 may also be other liquid resin molding compounds, such as liquid polyimide resin molding compound, liquid benzocyclobutene resin molding compound, or liquid polybenzoxazole resin molding compound. In other embodiments, the material of the bottom filler layer 211 may also be a non-conductive film.

[0073] It should be noted that in the foregoing embodiments, the thermally conductive metal sheet 209 is only attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201. The upper surface of the thermally conductive metal sheet 209 is flush with the first surface of the first semiconductor chip 201 (or the upper surface of the interlayer dielectric layer 206).

[0074] In another embodiment, please refer to [the relevant documentation]. Figures 11-15 ,in Figure 11 Schematic diagram 201 shows the top view of the first semiconductor chip. Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 13 for Figure 11 Schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 14 for Figure 12 The diagram shows a stacked package structure formed by sequentially stacking the first semiconductor chips along the AA1 cutting line. Figure 14 for Figure 13 The schematic diagram shown illustrates the structure of the stacked package formed by sequentially stacking the first semiconductor chips along the cutting line BB1. The main difference between this embodiment and the previous embodiment is that, in addition to being attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface of the first semiconductor chip 201, the thermally conductive metal sheet 209 is also attached to a portion of the first surface of the first semiconductor chip 201. On one hand, the mounting area of ​​the thermally conductive metal sheet 209 is increased, further improving the heat conduction efficiency; on the other hand, the portion of the thermally conductive metal sheet 209 located on the first surface of the first semiconductor chip 201 will not deform during the sequential stacking of several first semiconductor chips 201 (the melting point of the thermally conductive metal sheet 209 is greater than that of the solder ball 210), effectively supporting the upper and lower layers of the first semiconductor chips 201 and preventing short circuits caused by deformation of adjacent solder balls 210 between the upper and lower layers due to excessive pressure during the soldering process.

[0075] In one embodiment, the thermally conductive metal sheet 209 is attached to the groove 213, the outer surface of the internal heat dissipation metal layer 203, and the side surface and part of the first surface of the first semiconductor chip 201 by means of a first thermal interface material or a first thermally conductive welding material (not shown in the figure).

[0076] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A stacked package structure, characterized by, The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof.

2. The stacked package structure of claim 1, wherein, The application relates to a chip stack structure and a heat dissipation method thereof.

3. The stacked package structure of claim 2, wherein, The application relates to a chip stack structure and a heat dissipation method thereof.

4. The stacked package structure of claim 2, wherein, The application relates to a chip stack structure and a heat dissipation method thereof.

5. The stacked package structure of claim 2 or 3 or 4, wherein, The application relates to a chip stack structure and a heat dissipation method thereof.

6. The stacked package structure of claim 5, wherein, The application relates to a chip stack structure and a heat dissipation method thereof.

7. The stacked package structure of claim 6, wherein, The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. The application relates to a chip stack structure and a heat dissipation method thereof. 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8. The stacked package structure of claim 5, wherein, The heat-conducting metal sheet is attached to the first surface of the first semiconductor chip, in addition to being attached to the recess, the outer side surface of the inner heat-dissipating metal layer, and the side surface of the first semiconductor chip; the heat-conducting metal sheet is attached to the recess, the outer side surface of the inner heat-dissipating metal layer, and the side surface and the first surface of the first semiconductor chip through the first heat interface material or the first heat-conducting welding material.

9. The stacked package structure of claim 8, wherein, The upper surface or the first surface of the interlayer dielectric layer has a welding bump, which is electrically connected to the metal circuit; the heat-conducting metal sheet attached to the first surface of the first semiconductor chip is located on the upper surface of the interlayer dielectric layer on the side of the welding bump, and the upper surface of the heat-conducting metal sheet is lower than the top surface of the welding bump before welding; In the chip stack structure, the first surfaces or the upper surfaces of the interlayer dielectric layers of the first semiconductor chips are stacked in sequence in the direction perpendicular to the upper surface of the substrate; the welding bump on the first surface of the upper first semiconductor chip is welded to the corresponding via connection structure exposed on the second surface of the adjacent lower first semiconductor chip; and the chip stack structure further comprises a bottom filling layer filled between the upper and lower first semiconductor chips.

10. The stacked package structure of claim 1, wherein, The heat-conducting metal sheet is attached to the recess, the outer side surface of the inner heat-dissipating metal layer, and the side surface of the first semiconductor chip; the heat-conducting metal sheet is attached to the recess, the outer side surface of the inner heat-dissipating metal layer, and the side surface of the first semiconductor chip through the first heat interface material or the first heat-conducting welding material.

11. The stacked package structure of claim 1, wherein, The heat-dissipating cover is attached to the top surface and the side surface of the chip stack structure through the second heat interface material or the second heat-conducting welding material; the heat-dissipating cover comprises a first part and a second part protruding from the lower surface of the first part; the lower surface of the first part is attached to the top surface of the chip stack structure, and the inner side surface of the second part is attached to the side surface of the chip stack structure.

12. The stacked package structure of claim 1, wherein, The functions of the first semiconductor chips in the chip stack structure are the same or different.

13. The stacked package structure of claim 1, wherein, The chip stack structure further comprises a second semiconductor chip attached to the upper surface of the substrate on one side of the chip stack structure, which is electrically connected to the substrate.

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