Multi-layer chip stacking packaging structure

Abstract

The utility model relates to the field of semiconductor packaging, in particular to a multi-layer chip stacking packaging structure. Comprising a positioning bump and an elastic support frame, and the elastic support frame is matched with the positioning bump, so that on one hand, the stacking precision is improved, the electrical connection problem caused by inaccurate alignment is reduced, and on the other hand, chip displacement caused by external force or vibration in the packaging structure stacking process is prevented; supporting and alignment in the chip stacking process are both considered, and poor electrical connection caused by deformation and collapse of the electrical bumps due to excessive extrusion is prevented. Meanwhile, the elastic supporting frame has elasticity, mechanical stress borne by the chips in the stacking process is effectively relieved, therefore, the chips are prevented from being damaged due to uneven stress, the reliability of chip stacking is improved, and the service life of the chips is prolonged.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging, and in particular to a multi-layer chip stacking packaging structure. Background Technology

[0002] As electronic devices evolve towards miniaturization and higher performance, higher demands are placed on chip packaging technology. However, in existing chip stacking processes, insufficient pressure can lead to poor soldering, such as solder ball detachment and interface peeling, severely impacting the electrical connections and structural stability between chips. Excessive pressure, on the other hand, can cause excessive deformation of the solder balls, affecting soldering quality and potentially damaging the chip. Furthermore, when stacking multiple layers of chips, the differences in solder bump sizes and temperatures between layers further complicate pressure control. Therefore, achieving reasonable and precise structural stability during chip stacking remains a highly challenging problem. Utility Model Content

[0003] To solve the above-mentioned technical problems, this utility model provides a multi-layer chip stacking packaging structure.

[0004] This application provides a multi-layer chip stacking package structure, including:

[0005] A multi-layer chip packaging structure consisting of a substrate and several layers of chip structure;

[0006] The multilayer chip packaging structure is located on the first surface of the substrate;

[0007] The chip structure includes a chip, an elastic support frame, electrical bumps, and positioning bumps;

[0008] The positioning bump is located on the first surface of the chip and is used to align with the first surface of the substrate or the second surface of the chip in the next layer of the chip structure; the electrical bump is located on the first surface of the chip and is used to electrically connect to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure.

[0009] The elastic support frame includes an elastic support frame through hole, and the positioning bump is located in the elastic support frame through hole. The positioning bump and the elastic support frame cooperate to support and align each layer of the chip structure.

[0010] Optionally, the first surface of the chip includes an electrical connection region, and both the electrical bump and the positioning bump are located in the electrical connection region of the first surface of the chip.

[0011] Optionally, the positioning bump is a conductive positioning bump and is electrically connected to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure.

[0012] Optionally, the first surface of the chip further includes a non-electrical connection area, and the positioning bump is located in the non-electrical connection area of ​​the first surface of the chip.

[0013] Optionally, the positioning bump is a non-conductive positioning bump or a conductive positioning bump.

[0014] Optionally, the positioning bump and the elastic support frame are located in the edge region of the first surface of the chip or in the middle region of the first surface of the chip.

[0015] Optionally, the elastic support frame includes an elastic support body portion and an outer latching portion. The elastic support body portion includes an elastic support frame through hole. The support body portion is located on opposite sides of the first surface of the chip. The outer latching portion of the support frame is located outside the chip and is used to latch the chip in the next layer of the chip structure.

[0016] Optionally, the elastic support body portion is an arched elastic sheet.

[0017] Optionally, the elastic support frames corresponding to the chip structures on the same layer are arranged in an axisymmetric manner.

[0018] Optionally, the elastic support frame is a spring or an arched elastic sheet.

[0019] Optionally, the chip includes through-silicon vias (TSVs), and the TSVs of the chip are electrically connected to the electrical bumps to achieve electrical connection between upper and lower layer chips.

[0020] Optionally, the substrate includes conductive lines, and the conductive lines of the substrate are electrically connected to the multilayer chip packaging structure on the first surface of the substrate.

[0021] Optionally, the substrate further includes a heat dissipation channel located directly below the positioning bump.

[0022] Optionally, the multilayer chip stacked packaging structure further includes a molding compound layer located between the chips, between the chips and the substrate, and on the surface of the multilayer chip packaging structure.

[0023] Optionally, the second surface of the substrate has conductive bumps for electrical connection between the multilayer chip stacked package structure and external devices.

[0024] In summary, the advantages and beneficial effects of this utility model are as follows:

[0025] This application provides a multilayer chip stacking package structure, including,

[0026] A multilayer chip packaging structure comprising a substrate and several chip layers; the multilayer chip packaging structure is located on a first surface of the substrate; the chip structure includes a chip, a flexible support frame, electrical bumps, and positioning bumps; the positioning bumps are located on the first surface of the chip and are used to align with the first surface of the substrate or the second surface of the chip in the next layer of the chip structure; the electrical bumps are located on the first surface of the chip and are used to electrically connect to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure; the flexible support frame includes a through-hole, and the positioning bumps are located within the through-hole, the positioning bumps and the flexible support frame cooperating to support and align each layer of the chip structure.

[0027] The positioning bumps ensure precise alignment of the chips during stacking, while the elastic support frame provides support during chip stacking, preventing the electrical bumps from being excessively compressed, deformed, or collapsed, which could lead to poor electrical connections. It also prevents chip displacement caused by external forces or vibrations. By combining the elastic support frame and the positioning bumps, stacking accuracy is improved, reducing electrical connection problems caused by inaccurate alignment. Furthermore, it prevents chip displacement caused by external forces or vibrations during the stacking process, achieving a balance between support and alignment during chip stacking. This prevents the electrical bumps from being excessively compressed, deformed, or collapsed, which could lead to poor electrical connections, and also prevents chip displacement during stacking, ensuring the stability of the package structure. Simultaneously, the elastic support frame's elasticity effectively alleviates the mechanical stress on the chips during stacking, preventing damage due to uneven stress, improving the reliability of chip stacking, and extending chip lifespan. Attached Figure Description

[0028] Figures 1-5 This is a schematic diagram of a multi-layer chip stacking packaging structure provided for an embodiment of the present utility model. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solution of this utility model will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0030] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0031] This utility model provides a multi-layer chip stacking packaging structure, such as Figure 1 As shown, it includes:

[0032] A multi-layer chip packaging structure 200 consisting of a substrate 100 and several layers of chip structures;

[0033] The multilayer chip packaging structure 200 is located on the first surface of the substrate 100;

[0034] The chip structure includes a chip 10, an elastic support frame 20, an electrical bump 30, and a positioning bump 40.

[0035] The positioning bump 40 is located on the first surface of the chip and is used to align with the first surface of the substrate or the second surface of the chip in the next layer of the chip structure; the electrical bump 30 is located on the first surface of the chip and is used to electrically connect to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure.

[0036] The elastic support frame 20 includes an elastic support frame through hole, and the positioning bump is located in the elastic support frame through hole. The positioning bump and the elastic support frame cooperate to support and align each layer of the chip structure.

[0037] Specifically, in this embodiment, the substrate 100 is a silicon substrate, a silicon carbide substrate, a sapphire substrate, a copper-clad laminate, a redistribution layer, or other suitable packaging substrate. The substrate 100 includes a first surface and a second surface. The multilayer chip packaging structure 200 is located on the first surface of the substrate 100. The second surface of the substrate 100 has conductive bumps for electrically connecting the multilayer chip stacking packaging structure 200 to external devices.

[0038] In this embodiment, an adhesive layer (not shown) is provided between the positioning bump and the first surface of the substrate or the second surface of the chip, so that the positioning bump is attached to the first surface of the substrate or the second surface of the chip. The positioning bump is used to ensure the precise alignment between chips of different layers when the chips are stacked.

[0039] In this embodiment, as Figure 1As shown, the chip 10 includes a first surface and a second surface opposite to the first surface. The first surface of the chip includes a non-electrical connection region 11 and an electrical connection region 12. The non-electrical connection region 11 is located at the edges of opposite sides of the first surface of the chip, and the electrical connection region 12 is located in the area of ​​the first surface of the chip other than the non-electrical connection region 11.

[0040] By placing the non-electrical connection areas on the opposite edges of the chip, the elastic support frame and the positioning bumps are located on the opposite edges of the chip. This not only provides stable support for the chip but also does not affect the flow of the molding compound between subsequent chips, thereby improving the reliability of the packaging structure.

[0041] In this embodiment, as Figure 1 As shown, the electrical bump 30 is located in the electrical connection area 12 on the first surface of the chip, and is used to electrically connect the first surface of the substrate 100 or the second surface of the chip in the next layer chip structure. The positioning bump 40 is located in the non-electrical connection area 11 on the first surface of the chip, and is used to align the first surface of the substrate 100 or the second surface of the chip in the next layer chip structure.

[0042] In this embodiment, the positioning bump 40 is a non-conductive positioning bump.

[0043] In other embodiments, the positioning bumps located in the non-electrical connection area on the first surface of the chip can also be non-conductive positioning bumps.

[0044] In one embodiment, such as Figure 2 As shown, the electrical bump 30 and the positioning bump 40 are both located in the electrical connection area 12 of the first surface of the chip. At this time, the positioning bump 40 is a conductive positioning bump, used to align with the first surface of the substrate 100 or the second surface of the chip in the next layer chip structure, and electrically connects the first surface of the substrate 100 or the second surface of the chip in the next layer chip structure. The positioning bump 40 is a conductive positioning bump.

[0045] In one embodiment, the positioning bump and the elastic support frame are located in the edge region of the first surface of the chip or in the middle region of the first surface of the chip.

[0046] By placing the elastic support frame and the positioning bumps on opposite edges of the chip, the chip can be stably supported without affecting the flow of the molding compound between subsequent chips, thus improving the reliability of the packaging structure.

[0047] The elastic support frame 20 is used for support during chip stacking, preventing the electrical bumps from being excessively squeezed, deformed, or collapsed, which could lead to poor electrical connections. It also prevents chip displacement caused by external forces or vibrations. Simultaneously, the elastic support frame is elastic, effectively alleviating the mechanical stress on the chips during stacking, thereby preventing damage due to uneven stress, improving the reliability of chip stacking, and extending the chip's lifespan. The elastic support frame includes an elastic support frame through-hole, and the positioning bump 40 is located within the elastic support frame through-hole. The positioning bump 40 and the elastic support frame 20 cooperate to support and align each layer of the chip structure.

[0048] In one embodiment, when the multilayer chip package structure includes two chip structures, the electrical bumps on the first surface of the top layer chip are electrically connected to the second surface of the next layer chip, and the electrical bumps on the first surface of the next layer chip are electrically connected to the first surface of the substrate.

[0049] In one embodiment, such as Figure 3 As shown, the elastic support frame includes an elastic support body portion and an outer latching portion. The elastic support body portion includes an elastic support frame through hole. The support body portion is located on opposite sides of the first surface of the chip. The outer latching portion of the support frame is located outside the chip and is used to latch the chip in the next layer of the chip structure, further improving the stability of the support structure.

[0050] In this embodiment, the elastic support frames on the same layer are arranged axially symmetrically.

[0051] In this embodiment, the elastic support frame is a spring.

[0052] In other embodiments, the elastic support frame is an arched elastic sheet or other suitable elastic support frame, which can reduce the stress on the chip during chip stacking and prevent chip damage.

[0053] This application, by setting the positioning bump 40 inside the through hole of the support frame, allows the support frame 20 and the positioning bump 40 to cooperate, thereby improving the stacking accuracy and reducing the problem of poor electrical connection caused by inaccurate alignment. On the other hand, it prevents the electrical bump 40 from being excessively squeezed, deformed, or collapsed during stacking, which could lead to poor electrical connection and chip displacement during stacking, thus ensuring the stability of the packaging structure and achieving a balance between support and alignment during the chip stacking process.

[0054] In addition, by placing the support frame 20 and the positioning bumps 40 on the opposite edges of the chip, the chip can be stably supported without affecting the flow of the encapsulation material between subsequent chips, thus improving the reliability of the packaging structure.

[0055] In this embodiment, the electrical bump 30 is located on the first surface of the chip, and the electrical connection between the chips is achieved through the electrical bump 30.

[0056] In this embodiment, the material of the electrical bump 30 is tin, gold, or other suitable conductive material.

[0057] In this embodiment, the electrical bump 30 is a solder ball.

[0058] In other embodiments, the electrical bump is a gold bump or other suitable conductive bump.

[0059] In this embodiment, the chip 10 includes a through-silicon via 60, and the through-silicon via of the chip 10 is electrically connected to the electrical bumps on the first surface of the chip, thereby realizing the electrical connection between the upper and lower layers of the chip.

[0060] In this embodiment, the substrate 100 includes conductive lines, and the conductive lines of the substrate are electrically connected to the multilayer chip packaging structure on the first surface of the substrate.

[0061] In one embodiment, such as Figure 4 As shown, the substrate also includes a heat dissipation channel 70, which is located directly below the positioning bump. The heat dissipation channel 70 is used to dissipate heat from the multilayer chip packaging structure.

[0062] Specifically, the positioning bumps and the elastic support frame are located on opposite sides of the first surface of the chip, and the heat dissipation channel and the positioning bumps are distributed along the same straight line.

[0063] In other embodiments, the positioning bumps in different layers may not be distributed along the same straight line.

[0064] In this embodiment, as Figure 4 As shown, when the substrate has a heat dissipation channel, the second surface of the substrate and the position of the heat dissipation channel have conductive bumps for connecting with an external heat dissipation structure to dissipate heat for the support frame.

[0065] In another embodiment, the heat dissipation channel material and the substrate conductive circuit material are the same and are formed in the same manufacturing process.

[0066] In other embodiments, the materials and manufacturing processes of the heat dissipation channel and the conductive lines of the substrate may also be different.

[0067] In this embodiment, as Figures 1-5 As shown, the second surface of the substrate 100 has conductive bumps for electrical connection between the multilayer chip stacking package structure and external devices.

[0068] In this embodiment, as Figure 5 As shown, the multilayer chip stacked packaging structure also includes a molding compound layer 300, which is located between the chips, between the chips and the substrate, and on the surface of the multilayer chip packaging structure.

[0069] When the chips are stacked and encapsulated using molding compound to form the multi-layer chip stacking package structure, the elastic support frame and positioning bumps are located on opposite sides of the chips. Injecting molding compound from the other two sides of the chips does not affect the flow of molding compound between chips or between the chips and the substrate, thus ensuring the reliability of the molding.

[0070] The multi-layer chip stacking packaging structure, through the cooperation of the elastic support frame and the positioning bumps, improves the precise positioning and support between the chips in each layer of the multi-layer chip structure, improves the performance and integration of the packaging structure, and meets the requirements of modern electronic devices for miniaturization and high performance.

[0071] This utility model also provides a method for preparing a multilayer chip stacked packaging structure, including:

[0072] Step S10: Provide a substrate, a plurality of chips with electrically formed bumps, positioning bumps, and an elastic support frame. The first surface of the chip includes an electrically connected region and a non-electrically connected region. The non-electrically connected region is located at the edges of opposite sides of the first surface of the chip. The electrically connected region is located in the region other than the non-electrically connected region. The electrically formed bumps are located in the electrically connected region of the chip. The elastic support frame has an elastic support frame through hole.

[0073] In this embodiment, the non-electrical connection area is selected to be located on the edges of opposite sides of the chip, so that the subsequent elastic support frame and the positioning bump are located on the edges of opposite sides of the chip. This can not only stably support the chip, but also not affect the flow of the molding compound between chips and between the chip and the substrate, thereby improving the reliability of the packaging structure.

[0074] Step S20: A positioning bump is formed in the non-electrical connection area on the first surface of the substrate, the positioning bump being used for precise alignment of the chip;

[0075] In this embodiment, the positioning bumps are formed on the first surface of the substrate by adhesive bonding. The positioning bumps are used to ensure the precise alignment between the chips when they are stacked.

[0076] Step S30: The through hole of the elastic support frame is engaged with the positioning bump to place the elastic support frame on the surface of the substrate, and the support frames corresponding to the chip structure in the same layer are arranged opposite to each other;

[0077] In this embodiment, the elastic support frame is fitted onto the positioning protrusion through the through hole of the elastic support frame, so that the positioning protrusion and the elastic support frame cooperate.

[0078] In this embodiment, the elastic support frame is used for support during chip stacking, preventing the electrical bumps from being excessively squeezed, deformed, or collapsed, which could lead to poor electrical connections. It also prevents chip displacement caused by external forces or vibrations. Simultaneously, the elastic support frame is elastic, effectively alleviating the mechanical stress on the chips during stacking, thereby preventing damage to the chips due to uneven stress, improving the reliability of chip stacking, and extending the chip's lifespan.

[0079] In this embodiment, the elastic support frame and the positioning bump are located on opposite sides of the first surface of the subsequent chip, which can stably support the chip without affecting the flow of the molding material between the subsequent chips, thereby improving the reliability of the packaging structure.

[0080] Step S40: Place the non-electrical connection area of ​​the first surface of the chip on the surface of the positioning bump, wherein the electrical bump of the first surface of the chip is located on the first surface of the substrate;

[0081] Step S50: The substrate on which the elastic support frame, the positioning bumps and the chip are formed are fixedly welded to form the first layer chip structure.

[0082] In this embodiment, after soldering, the chip and the substrate are fixed and electrically connected to form a first-layer chip structure.

[0083] By placing the positioning bumps within the through-holes of the elastic support frame, the elastic support frame and the positioning bumps cooperate, improving stacking accuracy and reducing electrical connection problems caused by inaccurate alignment. Furthermore, it prevents the electrical bumps from being excessively squeezed, deformed, or collapsed, which could lead to poor electrical connections. It also prevents the chip from shifting during stacking, ensuring the stability of the package structure and achieving a balance between support and alignment during chip stacking. Simultaneously, the elastic support frame's elasticity effectively alleviates the mechanical stress on the chip during stacking, preventing damage due to uneven stress, improving the reliability of chip stacking, and extending chip lifespan.

[0084] Step S60: Repeat the above steps to complete the stacking of several layers of chip structure to form a multi-layer chip package structure;

[0085] Step S70: Molding material is injected between the chips, between the chips and the substrate, and around the multi-layer chip packaging structure to form a multi-layer chip stacked packaging structure.

[0086] When the chips are stacked and encapsulated using molding compound to form the multi-layer chip stacking package structure, the elastic support frame and positioning bumps are located on opposite sides of the chips. Injecting molding compound from the other two sides of the chips does not affect the flow of molding compound between the chips, thus ensuring the reliability of the molding.

[0087] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features made based on the technical solution of the present utility model device structure and the described embodiments, without departing from the corresponding technical solution of the present utility model, shall fall within the patent scope of the present utility model device structure and the described implementation.

Claims

1. A multi-layer chip stacked packaging structure, characterized in that, include: A multi-layer chip packaging structure consisting of a substrate and several layers of chip structure; The multilayer chip packaging structure is located on the first surface of the substrate; The chip structure includes a chip, an elastic support frame, electrical bumps, and positioning bumps; The positioning bump is located on the first surface of the chip and is used to align with the first surface of the substrate or the second surface of the chip in the next layer of the chip structure; the electrical bump is located on the first surface of the chip and is used to electrically connect to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure. The elastic support frame includes an elastic support frame through hole, and the positioning bump is located in the elastic support frame through hole. The positioning bump and the elastic support frame cooperate to support and align each layer of the chip structure.

2. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The first surface of the chip includes an electrical connection region, and both the electrical bump and the positioning bump are located in the electrical connection region of the first surface of the chip.

3. The multilayer chip stacking packaging structure as described in claim 2, characterized in that, The positioning bump is a conductive positioning bump and is electrically connected to the first surface of the substrate or the second surface of the chip in the next layer of the chip structure.

4. The multilayer chip stacking packaging structure as described in claim 2, characterized in that, The first surface of the chip also includes a non-electrical connection area, and the positioning bump is located in the non-electrical connection area of ​​the first surface of the chip.

5. The multilayer chip stacking packaging structure as described in claim 4, characterized in that, The positioning bump is either a non-conductive positioning bump or a conductive positioning bump.

6. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The positioning bump and the elastic support frame are located in the edge region of the first surface of the chip or in the middle region of the first surface of the chip.

7. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The elastic support frame includes an elastic support body portion and an outer latching portion. The elastic support body portion includes an elastic support frame through hole. The support body portion is located on opposite sides of the first surface of the chip. The outer latching portion of the support frame is located outside the chip and is used to latch the chip in the next layer of the chip structure.

8. The multilayer chip stacking packaging structure as described in claim 7, characterized in that, The elastic support body is an arched elastic sheet.

9. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The elastic support frames corresponding to the chip structures on the same layer are arranged symmetrically.

10. A multilayer chip stacking packaging structure as described in claim 1, characterized in that, The elastic support frame is a spring or an arched elastic sheet.

11. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The chip includes through-silicon vias (TSVs), and the TSVs and electrical bumps are electrically connected to achieve electrical connection between upper and lower chip layers.

12. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, The substrate includes conductive lines, and the conductive lines of the substrate are electrically connected to the multilayer chip packaging structure on the first surface of the substrate.

13. The multilayer chip stacking packaging structure as described in claim 12, characterized in that, The substrate also includes a heat dissipation channel located directly below the positioning bump.

14. The multilayer chip stacking packaging structure as described in claim 1, characterized in that, It also includes a molding compound layer located between the chips, between the chips and the substrate, and on the surface of the multilayer chip package structure.

15. A multilayer chip stacking packaging structure as described in claim 1, characterized in that, The second surface of the substrate has conductive bumps for electrical connection between the multilayer chip stacking package structure and external devices.

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