Interposer module and package structure

Abstract

The utility model relates to a mediator module, which comprises a mediator. A semiconductor die on the interposer, wherein the semiconductor die includes an equipotential pad and a passivation layer on the equipotential pad; and a plurality of connection structures connecting the equipotential pads to the interposer, in which the passivation layer is located on the equipotential pads between the plurality of connection structures. By providing a passivation layer (surface passivation layer) in the interposer module, solder bridging on an equipotential pad circuit can be suppressed (e.g., prevented). The passivation layer may avoid increasing the total thickness of the package structure (package).

Description

Technical Field

[0001] This utility model relates to an intermediary module and its packaging structure. Background Technology

[0002] Equipotential pads may comprise conductive surfaces or electrodes designed to maintain a consistent potential or voltage over a specific area. Equipotential pads can be used in a variety of applications where it is necessary to ensure that there is no potential difference between different points on a surface.

[0003] During operation, equipotential bonding pads create a path for charge, distributing it evenly across the applied surface. This uniform potential distribution helps ensure that all points in contact with the equipotential bonding pad have the same potential, reducing the risk of electric shock or discomfort due to potential differences.

[0004] Equipotential bonding pads can be made of metal or other conductive materials. Depending on the specific application, equipotential bonding pads can come in various shapes and sizes. Equipotential bonding pads play an important role in maintaining a uniform electric field throughout the structure to provide accurate measurements or safe operation. Utility Model Content

[0005] One aspect of this utility model relates to an intermediary module, comprising an intermediary; a semiconductor die located on the intermediary, wherein the semiconductor die includes an equipotential pad and a passivation layer located on the equipotential pad; and a plurality of connection structures connecting the equipotential pad to the intermediary, wherein the passivation layer is located on the equipotential pad between the plurality of connection structures.

[0006] Another aspect of this utility model relates to a method for forming an intermediary module, comprising: forming a semiconductor die including an equipotential pad, a passivation layer located on the equipotential pad, and a plurality of metal pillars located on the equipotential pad; forming an intermediary including a plurality of metal bumps; and forming a plurality of connection structures by respectively bonding the plurality of metal pillars to the plurality of metal bumps, and attaching the semiconductor die to the intermediary, wherein the passivation layer is located on the equipotential pad between the plurality of connection structures.

[0007] Another aspect of this utility model relates to a packaging structure including a packaging substrate, an intermediate module, and a packaging cap. The intermediate module is located on the packaging substrate and includes an intermediate; a semiconductor die located on the intermediate, wherein the semiconductor die includes an equipotential pad and a passivation layer located on the equipotential pad; and a plurality of connection structures connecting the equipotential pad to the intermediate, wherein the passivation layer is located on the equipotential pad between the plurality of connection structures. The packaging cap is located on the intermediate module and attached to the packaging substrate.

[0008] Several problems may arise during the formation of equipotential pad circuits. In particular, solder wetting issues may occur due to the continuous metal layers of the equipotential pad circuit and solder bridging in fine-pitch areas. One or more embodiments of this invention may include an interposer module comprising a passivation layer (surface passivation layer) that helps suppress (e.g., prevent) solder bridging on the equipotential pad circuit. The passivation layer avoids increasing the overall thickness of the package structure (package body). Interposer modules including passivation layers may be particularly useful in portable and wearable applications. Attached Figure Description

[0009] The best understanding of the present invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of explanation. Furthermore, it should be noted that the drawings illustrate only representative embodiments of the present invention and therefore should not be construed as limiting the scope. The present invention should be equally applicable to other embodiments. Moreover, the drawings may implicitly depict features not explicitly described herein.

[0010] Figure 1A It is a vertical cross-sectional view of an intermediary module according to one or more embodiments.

[0011] Figure 1B It is a plan view (e.g., top view) of the mediator module according to one or more embodiments.

[0012] Figure 1C It is a detailed vertical cross-sectional view of the mediator module according to one or more embodiments.

[0013] Figure 2A It is a plan view (top view) of equipotential pads and silicon vias according to one or more embodiments.

[0014] Figure 2B It is a perspective view of equipotential pads and silicon vias with alternative designs according to one or more embodiments.

[0015] Figure 2C It is a perspective view of equipotential pads and silicon vias with alternative designs according to one or more embodiments.

[0016] Figure 3A It is a vertical cross-sectional view of an intermediate structure including an equipotential pad according to one or more embodiments.

[0017] Figure 3B It is a vertical cross-sectional view of an intermediate structure including a passivation layer located on an equipotential pad, according to one or more embodiments.

[0018] Figure 3CIt is a vertical cross-sectional view of an intermediate structure including metal pillars according to one or more embodiments.

[0019] Figure 4A It is a vertical cross-sectional view of an intermediate structure comprising a portion of an intermediary (e.g., an organic intermediary) located on a second carrier substrate (e.g., a carrier wafer) according to one or more embodiments.

[0020] Figure 4B It is a vertical cross-sectional view of an intermediate structure comprising semiconductor grains located on an intermediary, according to one or more embodiments.

[0021] Figure 4C It is a vertical cross-sectional view of an intermediate structure including a bottom filling layer of an intermediary module according to one or more embodiments.

[0022] Figure 4D It is a vertical cross-sectional view of an intermediate structure including a molding material layer according to one or more embodiments.

[0023] Figure 4E It is a vertical cross-sectional view of an intermediate structure including a plurality of C4 bumps according to one or more embodiments.

[0024] Figure 5 This is a flowchart illustrating a method for creating an intermediary module according to one or more embodiments.

[0025] Figure 6 It is a vertical cross-sectional view of a package structure including an intermediary module according to one or more embodiments.

[0026] Figures 7A to 7G Various intermediate structures in a method of forming a package structure are shown according to one or more embodiments.

[0027] Figure 8 It is a detailed vertical cross-sectional view of an intermediary module having a first alternative design according to one or more embodiments. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the present invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] In addition, this document may use spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms to facilitate the explanation of the relationship between one component or feature shown in the figures and another component or feature. Spatially relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless explicitly stated otherwise, it is assumed that components with the same reference number have the same material composition and thickness within the same thickness range.

[0030] Equipotential pad circuits can be used to accommodate high current densities. Equipotential pad circuits can utilize microbumps with a single pitch, rather than other mixed-pitch microbumps, which may be challenged by the bump height difference between small-pitch and large-pitch bumps.

[0031] A method for fabricating an equipotential pad circuit may include forming a back-side redistribution layer on a wafer (e.g., a system-on-a-chip (SOC) wafer), which includes one or more through-silicon vias. Then, one or more metal pillars may be formed on the wafer (e.g., on the back-side redistribution layer). The wafer may then be separated into multiple dies.

[0032] Then, one or more metal bumps can be formed on the bottom wafer. Next, one or more dies can be connected to the bottom wafer by forming solder joints (such as SOC chip contacts) between metal pillars located on the die and metal bumps located on the bottom wafer.

[0033] Several problems may be encountered during the formation of equipotential bonding pad circuits. In particular, solder wetting problems may occur due to the continuous metal layers of the equipotential bonding pad circuit and the solder bridging caused in fine-pitch areas.

[0034] One or more embodiments of this invention may include an interposer module comprising a passivation layer (surface passivation layer) that helps suppress (e.g., prevent) solder bridging on equipotential pad circuitry. The passivation layer avoids increasing the overall thickness of the package structure (package body). Interposer modules including passivation layers may be particularly useful in portable and wearable applications.

[0035] A method of fabricating a dielectric module may include forming equipotential pads on a wafer comprising one or more through-silicon vias (TSVs). The equipotential pads may be included in a back-side redistribution layer on the back side of the wafer. A passivation layer may then be formed on the surface of the equipotential pads. The thickness of the passivation layer may be less than about 1 micrometer. In at least one embodiment, the thickness of the passivation layer may be between 10 nanometers and 1000 nanometers, but thicker or thinner passivation layers may be used.

[0036] A photomask layer (photomask structure) can be formed on the passivation layer. The photomask layer may include one or more openings. The passivation layer can be etched through the openings to expose the surface of the equipotential pad. Then, one or more metal pillars can be formed on the surface of the equipotential pad through the openings in the photomask layer. Next, the circle can be cut and separated into multiple grains.

[0037] One or more metal bumps can be formed on the bottom wafer (e.g., an interposer). One or more dies can then be attached to the bottom wafer (e.g., a chip-on-wafer (CoW) process) by forming solder joints (e.g., SOC chip contacts) between metal pillars on the die and metal bumps on the bottom wafer.

[0038] Passivation layers can be formed on copper surfaces (e.g., the copper surface of equipotential bonding pads). For example, passivation layers can be formed via a coating process. Passivation layer coatings can also help provide a 40% to 50% improvement in shear stress between the copper surface and the underfill layer between the grain and the underlying wafer. Passivation layers can exhibit thermal stability and reliability. The interface between the passivation layer and the copper surface also exhibits high stability.

[0039] The interposer module may include several mental models. In particular, the interposer module may provide a novel structure for preventing solder bridging on equipotential pads (e.g., equipotential pad circuits) without increasing the overall thickness of the interposer module for portable and wearable applications.

[0040] The mediator module also offers several advantages and benefits. In particular, the mediator module can be a micro-bump contact (e.g., a CoW micro-bump contact) to provide good bonding yield. The mediator module can also help overcome the height control challenges between small-pitch and large-pitch bumps. The mediator module also provides a highly competitive product and is highly compatible with current benchmark processes.

[0041] For example, the intermediate module may include an electrostatic discharge (ESD) protection module. In this embodiment, one or more dies in the intermediate module may include ESD protection circuitry in the front-end process region of the die. For example, the ESD protection circuitry may include one or more ESD clamping diodes. The ESD protection circuitry may be electrically coupled to an equipotential pad through one or more silicon vias in the die.

[0042] In at least one embodiment, the electrostatic discharge (ESD) protection module may be included in a wearable device (and / or portable device). In this embodiment, the size and performance of the clamping diode may be optimized for wearable applications. Wearable devices are typically in contact with the human body and are therefore frequently susceptible to ESD. For example, the ESD protection module may be included in smartwatches, smart glasses, smart bracelets, smart necklaces, wearable medical products, and other wearable devices.

[0043] In at least one embodiment, the electrostatic discharge (ESD) protection module may have a maximum operating voltage of 3.3 volts or 5.0 volts and provide high ESD protection of ±30 kV and 8.2 amps. The ESD protection module may include a bidirectional clamping diode housed in an ultra-compact package. In particular, the ESD protection module can be used to protect touch panel human-machine interfaces, display and camera module interfaces, RF and near-field communication antennas, physical buttons (e.g., volume buttons, lock buttons, menu buttons, etc.), and user interfaces (e.g., headphone jacks, USB interfaces, SIM cards, TF cards, etc.). The ESD protection module can also be used in other ESD-sensitive applications such as HDMI, display ports, high-speed video input / output (I / O), USB input / output (I / O), industrial input / output (I / O), etc.

[0044] Figure 1A This is a vertical cross-sectional view of the mediator module 120 according to one or more embodiments. Figure 1B It is a plan view (e.g., top view) of the mediator module 120 according to one or more embodiments. Figure 1A The vertical cross-section in the diagram is along Figure 1B Line segment A-A' in the diagram. Figure 1C This is a detailed vertical cross-sectional view of the intermediary module 120 according to one or more embodiments. In at least one embodiment, the intermediary module 120 may include the electrostatic discharge protection module described above. The intermediary module 120 may be included in wearable devices, such as smartwatches, smart glasses, smart bracelets, smart necklaces, wearable medical products, and other wearable devices.

[0045] like Figure 1A As shown, the intermediate module 120 may include one or more semiconductor dies 140 on the intermediate 10. Although the intermediate module 120 is shown as including a specific number of semiconductor dies with a specific arrangement, the number and arrangement of the semiconductor dies are not limited to any specific number and arrangement. A more advanced semiconductor dies may be used than... Figure 1A The two semiconductor chips 140 shown may have more or fewer semiconductor chips. In particular, the intermediate module 120 may include any number and arrangement of semiconductor chips.

[0046] Intermediate 10 is not limited to any particular material or configuration. For example, intermediate 10 may include organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, such as Figure 1A As shown, the intermediate 10 may include a plurality of alternately stacked dielectric layers 12 and a plurality of redistribution layers 12a. The number of dielectric layers 12 and / or redistribution layers 12a in the intermediate 10 is not limited by the present invention. In at least one embodiment, the dielectric layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The thickness of the dielectric layer 12 may be between 4 micrometers and 60 micrometers. Other thicknesses of the dielectric layer 12 are within the range contemplated by the present invention.

[0047] The redistribution layer 12a may include a conductive material. For example, the conductive material may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0048] The redistribution layer 12a may include a metallic interconnect structure, i.e., a metallic structure providing electrical connections between nodes. The redistribution layer 12a may include a metal seed layer (not shown) and a metallic filler material (not shown) on the metal seed layer. For example, the metal seed layer may include a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may be between 50 nanometers and 500 nanometers, and the thickness of the copper seed layer may be between 50 nanometers and 500 nanometers, but smaller or larger thicknesses may also be used. The metallic filler material of the redistribution layer 12a may include copper, nickel, or a combination of copper and nickel. Other suitable metallic filler materials are within the scope of this invention. The thickness of the metallic filler material deposited on each redistribution layer 12a may be between 2 micrometers and 40 micrometers, for example from 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used.

[0049] In at least one embodiment, the redistribution layer 12a may include a plurality of lines 12a1 and a plurality of vias 12a2 connecting the plurality of lines 12a1 to each other. The lines 12a1 may be located on the dielectric layer 12 and may extend along the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the dielectric layer 12.

[0050] An upper passivation layer (not shown) may be selectively formed on the chip-side surface 10s1 of the interposer 10. The upper passivation layer may include silicon dioxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0051] Semiconductor die 140 can be connected to intermediate body 10 via one or more connection structures 128. In at least one embodiment, each connection structure 128 may include metal bump 128a, metal pillar 128b, and solder joint 128c connecting metal pillar 128b to metal bump 128a.

[0052] One or more metal bumps 128a may be attached to the chip-side surface 10s1 of the interposer 10. The metal bumps 128a may be formed in a passivation layer (if present) located on the chip-side surface of the interposer 10. The upper passivation layer (if present) may at least partially cover the metal bumps 128a. That is, the metal bumps 128a may at least partially expose the chip-side surface 10s1 of the interposer 10.

[0053] Metal bumps 128a may be connected to redistribution layer 12a. In at least one embodiment, metal bumps 128a may be formed on the upper surface of vias 12a2 in the uppermost dielectric layer 12 of the interposer 10. For example, metal bumps 128a may comprise one or more layers and may comprise metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0054] Metal pillar 128b may be attached to semiconductor die 140. Metal pillar 128b may be formed of substantially the same material as metal bump 128a. For example, metal pillar 128b may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0055] Solder joint 128c may include soldering materials comprising one or more of tin, copper, silver, bismuth, indium, zinc, and antimony. Specifically, the soldering material may include a tin-silver-copper alloy comprising about 3% to 4% silver, 0.5% to 0.7% copper, and the balance (95% or more) tin. A fourth metal, such as zinc or manganese, may be added to the tin-silver-copper alloy. The melting point of the soldering material is between 90 and 450 degrees Celsius, and more particularly, between about 220 and 260 degrees Celsius.

[0056] The lower passivation layer 14 may be formed on the plate-side surface 10s2 of the intermediate 10. The lower passivation layer 14 may also include silicon dioxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0057] One or more intermediary underlayer bonding pads (not shown) may be located on the plate-side surface 10s2 of the intermediary 10. The intermediary underlayer bonding pads may be bonded and electrically connected to the redistribution layer 12a. The intermediary underlayer bonding pads may be located in the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the intermediary underlayer bonding pads. That is, the intermediary underlayer bonding pads may at least partially expose the plate-side surface of the intermediary 10. For example, the intermediary underlayer bonding pads may also comprise one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0058] In at least one embodiment, one or more integrated passive components (IPDs) may be selectively located on the plate-side surface 10s2 of the interposer 10. The integrated passive components (not shown) may be bonded and electrically connected to the redistribution layer 12. The integrated passive components may be located in the lower passivation layer 14. The integrated passive components may include exposed portions protruding from the lower passivation layer 14. The integrated passive components may include one or more electronic components, such as resistors, capacitors, inductors, coils, chokes, microstrip lines, impedance matching components, filters, etc. The integrated passive components may be electrically coupled to the semiconductor die 140 through the interposer 10.

[0059] like Figure 1A As further shown, one or more C4 bumps 121 may be connected to the plate-side surface 10s2 of the interposer 10, respectively. The C4 bumps 121 may be connected to the redistribution layer 12a in the lowest dielectric layer 12 of the interposer 10. Alternatively, the C4 bumps 121 may be connected to the lower bonding pad of the interposer (if present).

[0060] In at least one embodiment, the C4 bump 121 may include an under-ball metal layer (not shown) located on the underlying bonding pad of the interposer. The C4 bump 121 may further include contact pads (e.g., copper / nickel contact pads) located on the under-ball metal layer and solder bumps (e.g., tin-silver solder bumps) located on the contact pads. The C4 bump 121 may allow the interposer module 120 to be connected to a substrate such as a package substrate.

[0061] like Figure 1A As shown, semiconductor dies 140 can be mounted on the interposer 10 such that the heights of the semiconductor dies 140 are substantially the same. Generally, the thickness of each semiconductor die 140 in the z-direction can be substantially the same. Therefore, the upper surfaces of each semiconductor die 140 can be substantially coplanar (e.g., formed in the same xy plane).

[0062] Semiconductor die 140 may include a back side 140b facing the interposer 10 and a front side 140f (e.g., the upper surface of the semiconductor die) facing away from the interposer 10. Semiconductor die 140 may include a front-end process online (FEOL) region 141 on its front side 140f. Semiconductor die 140 may also include a back-end process online (BEOL) region 142 (e.g., a bulk silicon region) on its back side 140b. Semiconductor die 140 may be electrically coupled to the redistribution layer 12a in the interposer 10 through the interconnect structure 128.

[0063] The bottom filler layer 229 of the interposer module may be formed below and around each semiconductor die 140 (e.g., individually or in connection). The bottom filler layer 229 of the interposer module may also be formed around the connection structure 128. The bottom filler layer 229 of the interposer module thereby secures each semiconductor die 140 to the interposer 10. The bottom filler layer 229 of the interposer module may be formed of an epoxy-based polymer material.

[0064] Semiconductor dies 140 may each have the same or different types. For example, each semiconductor die 140 may include a single semiconductor die, a system-on-a-chip (SoC) die, or a system-on-a-chip (SoIC) die, and may be implemented using CoWoS (Chip on Wafer on Substrate) technology or Integrated Fan-Out and Package-on-Site (INFO-oS) technology. Specifically, for example, each semiconductor die 140 may include semiconductor chips or dies, logic dies (e.g., mobile application processors, microcontrollers, etc.), or memory dies (e.g., high-bandwidth memory (HBM) dies, hybrid memory cubes (HMC), dynamic random access memory (DRAM) dies, widened bus dies, etc.) for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications. I / O chips, magnetoresistive random access memory chips, resistive memory chips, NAND chips, static random access memory (SRAM), etc., central processing unit chips, graphics processing unit chips, field-programmable gate array chips, network chips, application-specific integrated circuit chips, artificial intelligence / deep neural network accelerator chips, etc., coprocessors, accelerators, on-chip memory buffers, high data rate transceiver chips, I / O interface chips, integrated passive component chips, power management chips (e.g., power management integrated circuit chips), radio frequency chips, sensor chips, microelectromechanical systems (MEMS) chips, signal processing chips (e.g., digital signal processing chips), front-end chips (e.g., analog front-end chips), monolithic 3D heterogeneous chiplet stacking dies, etc. Other chips are also included within the scope of this invention.

[0065] In at least one embodiment, at least one semiconductor die 140 may include a master die (e.g., a system-on-a-chip die). Another semiconductor die 140 may include an auxiliary die (e.g., a memory / system-on-a-chip die, a high-bandwidth memory die, etc.).

[0066] In at least one embodiment, the intermediate module 120 may include an electrostatic discharge (ESD) protection module, and one or more semiconductor dies 140 may include ESD protection dies. The front-end process region 141 of the ESD protection die may include ESD protection circuitry, which includes one or more clamping diodes.

[0067] The semiconductor die 140 may also include an equipotential pad 200 on its back side 140b. The equipotential pad 200 may be included in a back side redistribution layer structure located on the back side 140b of the semiconductor die 140. A passivation layer 202 (surface passivation layer) may be located on the surface of the equipotential pad 200. A connection structure 128 may contact the surface of the equipotential pad 200 through an opening in the passivation layer 202. The equipotential pad 200 may be electrically coupled to the front-end process region 141 of the semiconductor die 140 through one or more through-silicon vias 201. If the front-end process region 141 includes an electrostatic discharge (ESD) protection circuit, the ESD protection circuit may be electrically coupled to the equipotential pad 200 through one or more through-silicon vias 201.

[0068] The equipotential bonding pad 200 may be formed of a conductive material, such as a metallic material. In at least one embodiment, the equipotential bonding pad 200 may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0069] The silicon through-hole 201 may also be formed of a conductive material, such as a metallic material. In at least one embodiment, the silicon through-hole 201 may be formed of the same material as the equipotential pad 200. In at least one embodiment, the silicon through-hole 201 may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0070] like Figure 1A As shown, in each semiconductor die 140, a passivation layer 202 may be formed on an equipotential pad 200 located between interconnect structures 128. The thickness of the passivation layer 202 may be less than about 1 micrometer. In at least one embodiment, the thickness of the passivation layer 202 may be between 10 nanometers and 1000 nanometers. Therefore, the passivation layer 202 avoids increasing the overall thickness of the interposer module 120. For example, the passivation layer 202 may be formed of aluminum oxide, silicon dioxide, and silicon nitride. In at least one embodiment, an organic self-assembled monolayer may be used in the passivation layer 202 in advanced packaging because of its highly selective growth and relatively low growth temperature.

[0071] In an embodiment where solder material overflows from between metal bump 128a and metal post 128b during solder reflow in solder joint 128c, passivation layer 202 can electrically insulate the equipotential pad 200 from the overflowing solder material. Therefore, passivation layer 202 can help suppress solder bridging on the equipotential pad 200.

[0072] The intermediate module 120 may also include a molding compound layer 127 formed around the semiconductor die 140. The molding compound layer 127 may also be formed on and around the bottom fill layer 229 of the intermediate module. The molding compound layer 127 may have an outer wall substantially aligned with the outer wall of the intermediate 10.

[0073] In at least one embodiment, a molding compound layer 127 may be formed on the sidewalls (inner and outer sidewalls) of each semiconductor die 140. The molding compound layer 127 may be formed between and bonded to the sidewalls of each semiconductor die 140. The molding compound layer 127 may also be bonded to the chip side surface of the interposer 10 and the bottom fill layer 229 of the interposer module.

[0074] like Figure 1A As shown, the molding material layer 127 may undergo a chemical mechanical polishing step to form a top surface coplanar with the semiconductor grain 140. After polishing, the molding material layer 127 may include a substantially uniform (e.g., flat) upper surface. The upper surface of the molding material layer 127 may alternatively or additionally include a recessed portion (not shown) recessed in the z-direction from the upper surface of the semiconductor grain 140.

[0075] In at least one embodiment, the molding material layer 127 may be formed of a curable material that can be cured to form a rigid solid structure. For example, the molding material layer 127 may include an epoxy molding compound (EMC). In at least one embodiment, the molding material layer 127 may include a material substantially similar to the bottom filler layer 229 of the intermediate module. In at least one embodiment, the molding material layer 127 may include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials are within the scope of the disclosure.

[0076] In at least one embodiment, the molding material layer 127 may have a coefficient of thermal expansion substantially similar to that of the intermediate 10. In at least one embodiment, the molding material layer 127 may include additive materials (e.g., filler materials) to improve the properties of the molding material layer 127 (e.g., thermal conductivity, coefficient of thermal expansion, etc.). Additive materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the molding material layer 127 are within the scope of this invention.

[0077] like Figure 1BAs shown, the shaded and dashed lines are used to indicate the location of the equipotential pad 200 and the silicon via 201 on the equipotential pad 200. Figure 1B As shown, semiconductor die 140 may include three equipotential pads 200. Within the scope of the disclosure, the number of equipotential pads 200 may be fewer or more. The equipotential pads 200 may have substantially the same size and shape. The equipotential pads 200 may also be substantially aligned in the y-direction. The equipotential pads 200 are connected to silicon vias 201 in the front-end process region 141 of semiconductor die 140 (see...). Figure 1A They can also have the same size and shape, and can be substantially aligned in the y-direction.

[0078] The equipotential bonding pad 200 may have a substantially rectangular shape and may be arranged longitudinally in the x-direction. Within the scope of the disclosed intentions, the equipotential bonding pad 200 may have other shapes and arrangements. For example... Figure 1B As shown, the silicon through-hole 201 may have a substantially circular cross-section. The silicon through-hole 201 may be substantially aligned in the x-direction on its respective equipotential pad 200. The silicon through-hole 201 may also be substantially aligned in the x-direction between semiconductor dies 140. Within the scope of the disclosed considerations, the silicon through-hole 201 may have other shapes and arrangements.

[0079] The number of equipotential pads 200 in semiconductor dies 140 may vary among semiconductor dies 140. That is, some semiconductor dies 140 may have three equipotential pads 200, other semiconductor dies 140 may have two equipotential pads 200, and so on. The size and shape of the equipotential pads 200 may vary among semiconductor dies 140.

[0080] The number of silicon vias 201 in semiconductor dies 140 can also vary among semiconductor dies 140. That is, some semiconductor dies 140 may have three silicon vias 201 for each equipotential pad 200, while other semiconductor dies 140 may have two silicon vias 201 for each equipotential pad 200, and so on. The size and shape of the silicon vias 201 can also vary among semiconductor dies 140.

[0081] like Figure 1B As further shown, the molding compound layer 127 can be formed over the entire periphery of each semiconductor die 140. The width of the molding compound layer 127 around the intermediate module 120 can be substantially uniform. The width of the molding compound layer 127 between the semiconductor dies 140 can be greater than the width of the molding compound layer 127 around the intermediate module 120.

[0082] Figure 1CThis is a detailed vertical cross-sectional view of a portion of the mediator module 120 according to one or more embodiments. In particular, Figure 1C The equipotential pad 200 and the passivation layer 202 on the equipotential pad 200 are shown. Figure 1C A connection structure 128 connected to the equipotential pad 200 is also shown.

[0083] like Figure 1C As shown, the silicon via 201 may have a substantially rectangular vertical cross-section. Alternatively, the vertical cross-sectional shape of the silicon via 201 may be substantially trapezoidal, with its width gradually decreasing in the z-direction away from the equipotential pad 200. Within the scope of the disclosed prospectus, the silicon via 201 may have other vertical cross-sectional shapes.

[0084] The silicon through-hole 201 may have a diameter D201 between 5 micrometers and 40 micrometers. The silicon through-hole 201 may include a pair of external silicon through-holes 201o and an internal silicon through-hole 201i located between the external silicon through-holes 201o. The outer sidewalls of the external silicon through-holes 201o may be spaced apart by a distance D1 between 50 micrometers and 500 micrometers. The inner sidewalls of the external silicon through-holes 201o may be spaced apart by a distance D2 between 20 micrometers and 400 micrometers. The inner sidewall of the external silicon through-hole 201o may be spaced apart from the inner sidewall of the metal pillar 128c by a distance D3 between 1 micrometer and 20 micrometers.

[0085] The width W200 of the equipotential pad 200 in the x-direction may be greater than the distance D1 between the outer walls of the external silicon via 201o. The width W200 may be substantially uniform over the entire area of ​​the equipotential pad 200. In at least one embodiment, the width W200 may be between 100 micrometers and 1000 micrometers. The equipotential pad 200 may have a thickness T200 between 5 micrometers and 40 micrometers.

[0086] The thickness of the passivation layer 202 may be less than the thickness T200 of the equipotential bonding pad 200. In at least one embodiment, the thickness of the passivation layer 202 may be less than 20% of the thickness T200 of the equipotential bonding pad 200. The thickness of the passivation layer 202 may be substantially uniform over the entire area of ​​the passivation layer 202. The passivation layer 202 may be continuously formed on the sidewalls and bottom surface of the equipotential bonding pad 200.

[0087] The back surface 140b of the semiconductor die 140 and the chip side surface 10s1 of the interposer 10 can be spaced apart by a distance D4 ranging from 10 micrometers to 150 micrometers. The thickness T200 of the equipotential pad 200 can be less than 30% of the distance D4. The equipotential pad 200 can extend in the x-direction (e.g., laterally) beyond the outer wall of the connection structure 128 (e.g., the outer wall of the metal pillar 128b) by a distance D5 ranging from 5 micrometers to 100 micrometers. The inner sidewalls of the connection structure 128 (e.g., the inner sidewalls of the metal pillar 128b) can be spaced apart by a distance D4 ranging from 5 micrometers to 150 micrometers. The distance D6 between the inner sidewalls of the connection structure 128 can be less than the distance D2 between the inner sidewalls of the external silicon via 201o.

[0088] The connection structure 128 may have a pitch P between 10 micrometers and 200 micrometers. The pitch of the external silicon via 201o may be substantially the same as the pitch P of the connection structure 128. In each connection structure 128, the metal bump 128a and the metal pillar 128b may be substantially aligned in the z-direction. The metal bump 128a may be spaced from the metal pillar 128b in the z-direction by a distance equal to the thickness T128c of the solder joint 128c. In at least one embodiment, the thickness T128c of the solder joint 128c may be less than the thickness T128b of the metal pillar 128b. In at least one embodiment, the thickness T128c of the solder joint 128c may be between 1 micrometer and 30 micrometers.

[0089] The metal bump 128a may have a diameter D128a between 2 micrometers and 50 micrometers and a thickness T128a between 5 micrometers and 40 micrometers. The metal pillar 128b may have a diameter D128b between 2 micrometers and 50 micrometers and a thickness T128b between 5 micrometers and 40 micrometers. In at least one embodiment, the diameter D128b of the metal pillar 128b may be larger than the diameter D201 of the through-silicon via 201. In at least one embodiment, the thicknesses T128a and T128b may be substantially the same, and the diameters D128a and D128b may be substantially the same. In at least one embodiment, the thickness T128a may be smaller than the thickness T128b.

[0090] Figure 2A This is a plan view (top view) of the equipotential pad 200 and the through-silicon via 201 according to one or more embodiments. Figure 2B It is a perspective view of an equipotential pad 200 and a through-silicon via 201 with alternative designs according to one or more embodiments. Figure 2C It is a perspective view of an equipotential pad 200 and a through-silicon via 201 with alternative designs according to one or more embodiments.

[0091] like Figure 2AAs shown, the equipotential bonding pad 200 may have sidewalls 200s around its entire periphery. A passivation layer 202 may be continuously and uniformly formed around the entire sidewalls 200s. The thickness of the passivation layer 202 may be substantially uniform over the entire sidewalls 200s.

[0092] The silicon via 201 may be located in the central region of the equipotential pad 200. On the surface of the equipotential pad 200, the silicon via 201 may occupy between approximately 5% and 30% of the total surface area of ​​the equipotential pad 200.

[0093] like Figure 2B As shown, the silicon through-hole 201 can have a substantially cylindrical shape. For example... Figure 2C As shown in the alternative design, the silicon via 201 may have a truncated tapered shape. Other shapes of the silicon via 201 are included within the scope of this invention.

[0094] Figures 3A to 3C This is a vertical cross-sectional view of an intermediate structure forming a semiconductor die 140 according to one or more embodiments. In particular, Figure 3A It is a vertical cross-sectional view of an intermediate structure including an equipotential bonding pad 200 according to one or more embodiments.

[0095] like Figure 3A As shown, a front-end process region 141 may be formed on a first carrier substrate 1. The first carrier substrate 1 may include a circular wafer or a rectangular wafer. The lateral dimension of the first carrier substrate 1 (e.g., the diameter of a circular wafer or one side of a rectangular wafer) may be between 100 mm and 500 mm, for example, from 200 mm to 400 mm, but smaller and larger lateral dimensions may also be used. The first carrier substrate 1 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 1 may be transparent or opaque. The thickness of the first carrier substrate 1 may be sufficient to provide mechanical support for the intermediate array to be formed thereon. For example, the thickness of the first carrier substrate 1 may be between 60 micrometers and 1 millimeter, but smaller and larger thicknesses may also be used.

[0096] An adhesive layer (not shown) may be applied to the top surface of a first carrier substrate 1. In one embodiment, the first carrier substrate 1 may comprise an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may comprise a light-to-heat conversion layer. The light-to-heat conversion layer is a solvent-based coating applied using a spin-coating method. The light-to-heat conversion layer may form a layer that converts ultraviolet light into heat, causing the light-to-heat conversion layer to lose its adhesiveness. Alternatively, the adhesive layer may comprise a thermally decomposable adhesive material. For example, the adhesive layer may comprise an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The debonding temperature of the thermally decomposable adhesive material may be between 150 and 400 degrees Celsius. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also included within the scope of this invention.

[0097] The front-end process region 141 can be formed in a series of front-end process steps. For example, the front-end process steps may include material deposition, photolithography, etc. The front-end process region 141 may include multiple individual components in one or more integrated circuits. The individual components in the front-end process region 141 may include, for example, transistors, capacitors, resistors, etc.

[0098] Back-end process region 142 may be formed on front-end process region 141 in a series of back-end process steps. Back-end process region 142 may include one or more interconnect layers for interconnecting individual components in front-end process region 141. The interconnect layers may include one or more dielectric material layers, metal wiring (e.g., traces, lines, etc.) on the dielectric material layers, and metal vias connecting the metal wiring between dielectric material layers. Back-end process region 142 may also include contact points and bonding locations for chip-to-package connections.

[0099] Through-silicon via 201 may include a back-end process through-silicon via formed in back-end process region 142 during back-end process processing. Through-silicon via 201 may additionally or alternatively include a post-BEOL through-silicon via formed in back-end process region 142 (e.g., in the bulk silicon region) after back-end process processing. Through-silicon via 201 may be formed as part of a 3D packaging connection process.

[0100] The process of forming the silicon through-hole 201 may include a photolithography process for forming the through-hole in the back-end process region 142. The photolithography process may include forming a patterned photoresist shield (not shown) on the back-end process region 142 and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the back-end process region 142 through openings in the photoresist shield. The photoresist shield can subsequently be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0101] Equipotential pads 200 may be formed together with through-silicon vias 201. A metal layer may be deposited on the back-end process region 142 using chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques. The metal layer may be deposited in the vias within the back-end process region 142 and on the surface of the back-end process region 142. The metal layer may fill the vias to form the through-silicon via 201. The metal layer may then be patterned using a photolithography process. The photolithography process may include forming a patterned photoresist shield (not shown) on the metal layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material layer through openings in the photoresist shield. The photoresist shield may subsequently be removed by ashing, dissolving, or consuming the photoresist shield during the etching process.

[0102] Figure 3B This is a vertical cross-sectional view of an intermediate structure including a passivation layer 202 located on an equipotential pad 200, according to one or more embodiments. The passivation material layer may be deposited on the downstream process region 142 and the equipotential pad 200, for example, by a wet deposition process. Alternatively, the passivation material layer may be formed by chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques.

[0103] In a wet coating process, a passivating material can be added to a solvent to form a passivating material solution suitable for coating. The passivating material solution can then be applied to the downstream process area 142 and the equipotential pad 200 via one or more methods such as spin coating, dip coating, or spray coating. The intermediate structure can then undergo a curing or drying process to remove the solvent and cure the passivating material.

[0104] The passivation material can then be patterned using a photolithography process. This process may include forming a patterned photoresist shield (not shown) on the passivation material and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist shield to passivate the exposed upper surface of the material. The photoresist shield can then be removed by ashing, dissolving, or consuming it during the etching process.

[0105] Figure 3CThis is a vertical cross-sectional view of an intermediate structure including metal pillars 128b according to one or more embodiments. After forming a passivation layer 202 on the equipotential pad 200, openings for the metal pillars 128b can be formed in the passivation layer 202. To form the openings, the passivation layer 202 can be patterned by a photolithography process. The photolithography process may include forming a patterned photoresist shield (not shown) on the passivation layer 202 and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the passivation layer 202 through the openings in the photoresist shield. The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0106] Then, metal pillars 128b can be formed on the surface of the equipotential pads 200 in the openings of the passivation layer 202. For example, the metal pillars 128b can be formed by electroplating, photolithography, or other suitable processes. In the photolithography process, a metal material layer can be deposited on the passivation layer 202 (by chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques), and then patterned by photolithography to form the metal pillars 128b.

[0107] Solder layers 128cL can then be formed on the metal pillars 128b. The solder layers 128cL can ultimately form solder joints 128c in the intermediate module 120. Therefore, the solder layers 128cL can include the materials described above for the solder joints 128c. The solder layers 128cL can be formed on the metal pillars 128b through one or more processes, including ball bonding, electroplating, solder printing, solder impregnation, and solder injection.

[0108] After forming a 128cm solder layer, a cutting process can be performed to remove... Figure 3C The intermediate structure is separated into individual semiconductor grains 140. The dicing process may include along... Figure 3C The dashed lines (cutting lines) in the diagram represent the cutting process areas 141 and 142.

[0109] Figures 4A to 4E It is a vertical cross-sectional view of an intermediate structure in a method of manufacturing a semiconductor module 120 according to one or more embodiments. Figure 4A This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, including a portion of an intermediary 10 (e.g., an organic intermediary) located on a second carrier substrate 2 (e.g., a carrier wafer). The lower passivation layer 14 in the intermediary 10 may be formed later in the method of forming the intermediary module 120. The second carrier substrate 2 may be substantially the same as the first carrier substrate 1 described above.

[0110] An adhesive layer (not shown) may be applied to the top surface of the second carrier substrate 2. The adhesive layer may be applied in conjunction with the aforementioned... Figure 3AThe adhesive layers are essentially the same (for example, the adhesive layer may include a photothermal conversion layer, a thermally decomposable adhesive material, etc.).

[0111] Multiple dielectric layers 12 and multiple redistribution layers 12a may be alternately formed on the second carrier substrate 2 (e.g., on an adhesive layer on the second carrier substrate 2). It should be noted that, although... Figure 4A Two dielectric layers 12 and two redistribution layers 12a are shown, but the present invention contemplates more or fewer dielectric layers 12 and redistribution layers 12a.

[0112] For example, each dielectric layer 12 can be formed by depositing (e.g., by chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques) a dielectric polymer layer such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable materials are within the scope of this invention. The thickness of the dielectric polymer layer can be between 4 micrometers and 60 micrometers, but smaller and larger thicknesses can also be used. The dielectric layer 12 can then be patterned by a photolithography process to form through-holes in the dielectric layer 12. The photolithography process may include forming a patterned photoresist shield (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric material through openings in the photoresist shield. The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0113] Then, a redistribution layer 12a (e.g., metal lines and metal vias) can be formed on the dielectric layer 12. For example, the redistribution layer 12a can be formed by depositing (e.g., by chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques) one or more layers of metal material (such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 12 and in the vias formed through the patterned dielectric layer 12. The metal material layer can then be patterned by a photolithography process to form the redistribution layer. The photolithography process may include forming a patterned photoresist shield (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material through openings in the photoresist shield. The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0114] like Figure 4AFurther, metal bumps 128a may then be formed on the uppermost dielectric layer 12 (e.g., on the chip-side surface 10s1 of the interposer 10). Each metal bump 128a may be formed to contact a corresponding via 12a2 in the uppermost dielectric layer 12. The metal bumps 128a may comprise any metallic material that can be bonded to a soldering material. The metal bumps 128a may be formed by depositing (e.g., by chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques) one or more metal layers comprising metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). The metal layers may then be patterned by a photolithography process to form the metal bumps 128a. The photolithography process may include forming a patterned photoresist shield (not shown) on the metallic material and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metallic material through openings in the photoresist shield. The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0115] In at least one embodiment, the metal bump 128a may comprise an under-ball metal layer stack deposited on the via 12a2. The material layers in the under-ball metal layer stack may be arranged such that solder material portions can subsequently be bonded to portions of the bottom surface of the under-ball metal layer stack. Layer stacks that can be used for the under-ball metal layer stack include, but are not limited to, stacks of chromium / chromium-copper / copper / gold, chromium / chromium-copper / copper, titanium-tungsten alloy / chromium / copper, titanium / nickel / gold, and chromium / copper / gold. Other suitable materials are within the scope of this invention. The thickness of the under-ball metal layer stack may be between 5 micrometers and micrometers, for example from 10 micrometers to 30 micrometers, but smaller and larger thicknesses may also be used. A photoresist layer may be coated on the under-ball metal layer stack and may be patterned by a photolithography process to form an array of discrete patterned photoresist material portions. An etching process may be performed to remove unmasked portions of the under-ball metal layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The remaining portion of the under-ball metal layer stack may form the metal bump 128a. In at least one embodiment, the metal bumps 128a can be arranged in a two-dimensional array, which can be a two-dimensional periodic array, such as a rectangular periodic array.

[0116] Figure 4BThis is a vertical cross-sectional view of an intermediate structure including semiconductor dies 140 located on an intermediary 10, according to one or more embodiments. For example, the semiconductor dies 140 can be placed on the intermediary 10 using an electromechanical pick-and-place machine. Each semiconductor die 140 can then be coupled to the intermediary 10 via one or more connection structures 128. In at least one embodiment, the connection structures 128 may comprise a two-dimensional array of connection structures 128.

[0117] Each semiconductor die 140 can be attached to a metal bump 128a via a C2 bonding process (e.g., solder bonding). During the C2 bonding process, each solder layer 128cL (located on a metal pillar 128b on an equipotential pad 200 in the semiconductor die 140) can be positioned on a corresponding metal bump 128a on the chip-side surface 10s1 of the interposer 10. The interposer can then be heated to resolder the solder layer 128cL onto the corresponding metal bump 128a, forming a solder joint 128c between the metal bump 128a and the metal pillar 128b. Other methods of bonding the semiconductor die 140 to the interposer 10 (e.g., hybrid bonding) are within the scope of this invention.

[0118] Figure 4C This is a vertical cross-sectional view of an intermediate structure including an underfill layer 229 of a mediator module according to one or more embodiments. The underfill layer 229 of the mediator module can be applied by depositing and / or injecting an underfill material (e.g., an epoxy-based polymer) onto the mediator 10. The underfill material can be applied to the mediator 10 to form below the semiconductor die 140 and around the connection structure 128. In at least one embodiment, the underfill material can substantially fill all gaps between the semiconductor die 140 and the mediator 10. The underfill material can then be cured to form the underfill layer 229 of the mediator module. For example, the underfill material can be cured in a box oven at a temperature between 120 and 180 degrees Celsius for 60 to 120 minutes to provide an underfill layer 229 of the mediator module with sufficient rigidity and mechanical strength.

[0119] Figure 4DThis is a vertical cross-sectional view of an intermediate structure including a molding compound layer 127 according to one or more embodiments. The molding compound layer 127 (e.g., an encapsulation layer) may be formed on the semiconductor die 140 and the interposer 10. In at least one embodiment, the molding compound layer 127 may be formed by processes such as overmolding and planarization. In particular, the molding compound layer 127 may include an epoxy polymer material (e.g., an epoxy molding compound). The molding compound layer 127 may be formed on the interposer 10 and fill the gaps between the semiconductor dies 140. The molding compound layer 127 may encapsulate (e.g., in the x and y directions) the semiconductor dies 140. For example, the molding compound layer 127 may be formed by a deposition process (e.g., chemical vapor deposition, plasma chemical vapor deposition, physical vapor deposition, spin coating, lamination, or other suitable deposition techniques).

[0120] A molding compound layer 127 may be deposited to completely cover the semiconductor die 140 and the bottom fill layer 229 of the intermediate module. After the molding compound layer 127 has cured, a planarization process may be used to make the upper surface of the molding compound layer 127 substantially coplanar with the upper surface of the semiconductor die 140. The planarization process may be performed on the upper surface of the molding compound layer 127 until the upper surface of the semiconductor die 140 is exposed. For example, the planarization process may include mechanical polishing and / or chemical mechanical polishing.

[0121] Figure 4E A vertical cross-sectional view of an intermediate structure comprising a plurality of C4 bumps 121 is shown according to one or more embodiments. After the molding material layer 127 has been cured and planarized (e.g., by grinding, chemical mechanical polishing, etc.), the intermediate structure can be attached to a third carrier substrate 3. The third carrier substrate 3 can be substantially similar to the first carrier substrate 1 and the second carrier substrate 2. In particular, the third carrier substrate 3 can be attached to the upper surface of the molding material layer 127 and the upper surface of the semiconductor die 140.

[0122] Figure 4D The intermediate structure can then be inverted, and the second carrier substrate 2 can be separated from the plate-side surface 10s2 of the intermediate 10. For example, the second carrier substrate 2 can be separated from the intermediate 10 by disabling the adhesive layer (not shown) that holds the second carrier substrate 2 to the intermediate 10. For example, the adhesive layer can be disabled by thermal annealing at elevated temperatures (e.g., for thermally deactivated adhesive materials) or by exposing the adhesive layer to ultraviolet light (e.g., for ultraviolet-deactivated adhesive materials).

[0123] Then, a lower dielectric bonding pad (if present) can be formed on the lower dielectric layer 12 of the intermediate 10. The lower dielectric bonding pad can be formed using substantially the same material and substantially the same photolithography process as the metal bump 128a described above. Then, a lower passivation layer 14 can be formed on the lower dielectric layer 12 of the intermediate 10 and on the lower dielectric bonding pad.

[0124] The lower passivation layer 14 can be formed by depositing one or more layers of passivation material (e.g., chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques), including silicon dioxide, silicon nitride, low dielectric constant materials (e.g., carbon-doped oxides), very low dielectric constant materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials. The passivation material can then be planarized (e.g., by wet etching, dry etching, chemical mechanical polishing, etc.) to form the lower passivation layer 14. The lower passivation layer 14 can then be etched using a suitable etching process (e.g., by wet etching, dry etching, etc.) to form openings on the redistribution layer 12a in the lower dielectric layer 12 (or on the underlying interposer bonding pad, if present).

[0125] Then, a plurality of C4 bumps 121 can be formed on the intermediate structure. For example, C4 bumps 121 may include solder balls formed in openings in the lower passivation layer 14. C4 bumps 121 can be formed by one or more processes, including balling, electroplating, solder printing, solder dipping, and solder implantation. C4 bumps 121 can contact the redistribution layer 12a (or the lower dielectric bonding pad, if present) in the lower dielectric layer 12 of the intermediate 10 through openings in the lower passivation layer 14. In at least one embodiment, C4 bumps 121 can be formed by forming one or more under-ball metal layers (not shown) on an exposed surface outside the redistribution layer 12a (or an exposed surface in the lower dielectric bonding pad, if present), forming contact pads on the under-ball metal layers, and then forming solder balls on the contact pads.

[0126] Figure 5 This is a flowchart illustrating a method for fabricating an interposer module 120 according to one or more embodiments. Step 510 includes forming a semiconductor die, wherein the semiconductor die includes an equipotential pad, a passivation layer on the equipotential pad, and a plurality of metal pillars on the equipotential pad. Step 520 includes forming an interposer including a plurality of metal bumps. Step 530 includes forming a plurality of connection structures by respectively bonding the plurality of metal pillars to the plurality of metal bumps, and attaching the semiconductor die to the interposer, wherein the passivation layer is located on the equipotential pad between the plurality of connection structures.

[0127] Figure 6 This is a vertical cross-sectional view of a package structure 100 including an intermediary module 120 according to another embodiment.

[0128] like Figure 6 As shown, the package structure 100 may include a package substrate 110 and an interposer module 120 on the package substrate 110. The package structure 100 may also include a package cover 130 on the interposer module 120. The package cover 130 may include a package cover foot 130a attached to the package substrate 110. The package cover 130 may also include a package cover plate portion 130p connected to the package cover foot 130a. The package structure 100 may also include a thermal interface material layer 170 between the interposer module 120 and the package cover plate portion 130p.

[0129] The packaging substrate 110 may include a cored or coreless substrate. For example, in at least one embodiment, the packaging substrate 110 may include a core layer 112, an upper dielectric layer 114 formed on the core layer 112 (e.g., a first side or chip side of the packaging substrate 110), and a lower dielectric layer 116 formed on the core layer 112 (e.g., a second side or circuit board side of the packaging substrate 110). In particular, the packaging substrate 110 may include an insulating build-up film substrate, such as an ABF substrate. That is, in at least one embodiment, both the upper dielectric layer 114 and the lower dielectric layer 116 of the packaging substrate can be interpreted as ABF layers.

[0130] The core layer 112 helps provide rigidity to the encapsulation substrate 110. For example, the core layer 112 may include an epoxy resin, such as bismaleimide-triazaphenyl epoxy (BT epoxy) and / or a braided glass laminate. The core layer 112 may alternatively or additionally include organic materials, such as polymeric materials. In particular, the core layer 112 may include dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are within the scope of this invention.

[0131] The core layer 112 may include one or more vias 112a. The vias 112a may extend from the lower surface of the core layer 112 to the upper surface of the core layer 112. The vias 112a may allow electrical connection between the upper dielectric layer 114 and the lower dielectric layer 116 of the package substrate. For example, the vias 112a may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, nickel, molybdenum, cobalt, ruthenium, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0132] The upper dielectric layer 114 of the packaging substrate may be formed on the upper surface of the core layer 112. The upper dielectric layer 114 of the packaging substrate may include multiple layers, particularly insulating build-up films (e.g., ABF). The upper dielectric layer 114 of the packaging substrate may also include organic materials, such as polymeric materials. Specifically, the upper dielectric layer 114 of the packaging substrate may include dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are within the scope of this invention.

[0133] The upper dielectric layer 114 of the package substrate may include one or more upper bonding pads 114a on the chip-side surface of the upper dielectric layer 114 of the package substrate. The upper bonding pads 114a may be exposed on the chip-side surface of the upper dielectric layer 114 of the package substrate. The upper dielectric layer 114 of the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structures 114b may electrically couple the upper bonding pads 114a of the package substrate to vias 112a in the core layer 112. The metal interconnect structures 114b may include metal layers (e.g., copper lines) and metal vias connecting the metal layers. For example, the upper bonding pads 114a and the metal interconnect structures 114b may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, molybdenum, cobalt, ruthenium, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0134] An upper passivation layer 110a on the package substrate may be formed on the chip-side surface of the upper dielectric layer 114 on the package substrate. The upper passivation layer 110a may at least partially cover the upper bonding pad 114a on the package substrate. The upper passivation layer 110a may include silicon dioxide, silicon nitride, a low dielectric constant material (such as carbon-doped oxide), an extremely low dielectric constant material (such as porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0135] A lower dielectric layer 116 of the packaging substrate may be formed on the lower surface of the core layer 112. The lower dielectric layer 116 may also comprise multiple layers, particularly including an insulating build-up film (e.g., ABF). The lower dielectric layer 116 may also comprise organic materials, such as polymeric materials. Specifically, the lower dielectric layer 116 may comprise dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are within the scope of this invention.

[0136] The lower dielectric layer 116 of the package substrate may include one or more lower bonding pads 116a on its side surface. The lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b can electrically couple the lower bonding pads 116a to vias 112a in the core layer 112. The metal interconnect structures 116b may include metal layers (e.g., copper lines) and metal vias connecting the metal layers. For example, the lower bonding pads 116a and the metal interconnect structures 116b may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper, aluminum, molybdenum, cobalt, ruthenium, tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.). Other suitable metallic materials are within the scope of this invention.

[0137] A lower passivation layer 110b of the package substrate may be formed on the board-side surface of the lower dielectric layer 116 of the package substrate. The lower passivation layer 110b of the package substrate may at least partially cover the lower bonding pad 116a of the package substrate. The lower passivation layer 110b of the package substrate may include silicon dioxide, silicon nitride, a low dielectric constant material (such as carbon-doped oxide), an extremely low dielectric constant material (such as porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0138] The ball grid array (BGA) includes a plurality of solder balls 110c that can be formed on the board-side surface of the package substrate 110. The solder balls 110c securely mount the package structure 100 onto a substrate (e.g., a printed circuit board) and electrically couple it to the printed circuit board. The solder balls 110c can contact the lower bonding pad 116a of the package substrate. Therefore, the solder balls 110c can be electrically connected to the upper bonding pad 114a of the package substrate through metal interconnect structures 116b, vias 112a, and metal interconnect structures 114b. The solder balls 110c in the ball grid array can form a two-dimensional array on the board-side surface of the package substrate 110. For example, the solder balls 110c can be located below the package cover pins 130a and below the intermediate module 120.

[0139] like Figure 6 As shown, the width of the packaging substrate 110 in the x-direction can be greater than the width of the interposer module 120 in the x-direction. The length of the packaging substrate 110 in the y-direction can also be greater than the length of the interposer module 120 in the y-direction. The interposer module 120 can be located at the center of the packaging substrate 110.

[0140] Intermediate module 120 can be attached to upper bonding pad 114a of package substrate 110 via C4 bump 121. C4 bump 121 may include metal pillars (not shown) and solder bumps (e.g., tin-silver solder bumps) on the metal pillars. The solder bumps may collapse to bond the metal pillars of C4 bump 121 to upper bonding pad 114a of package substrate.

[0141] An underfill layer 129 can be formed on the package substrate 110 and can be formed below and around the intermediate module 120. The underfill layer 129 can also be formed around the C4 bump 121. The underfill layer 129 can thereby securely attach the intermediate module 120 to the package substrate 110. The underfill layer 129 can be formed of an underfill material, such as an epoxy-based polymer. Other suitable materials can also be used for the underfill layer 129.

[0142] A thermal interface material layer 170 may be located on the intermediary module 120. The thermal interface material layer 170 may include one or more layers. In at least one embodiment, the center of the thermal interface material layer 170 may be substantially aligned with the center of the intermediary module 120. In at least one embodiment, the thermal interface material layer 170 may extend laterally (e.g., in the xy plane) beyond the outer sidewall 127a of the molding material layer 127.

[0143] The thermal interface material layer 170 can have low volumetric thermal resistance and high thermal conductivity. The thermal interface material layer 170 can cover the entire area of ​​the upper surface of the interposer module 120. The thermal interface material layer 170 can be attached to the upper surface of the interposer module 120 using a thermally conductive adhesive.

[0144] In at least one embodiment, the thermal interface material layer 170 may include one or more metals. For example, the thermal interface material layer 170 may include a low-melting-point metal thermal interface material or a liquid metal thermal interface material. The thermal interface material layer 170 may include one or more metals, such as indium, tin, gallium, silver, etc. For example, the thermal interface material layer 170 may include gallium-based, indium-based, silver-based, solder-based, etc. The solder base may include tin and one or more other elements, such as copper, silver, bismuth, indium, zinc, antimony, etc.

[0145] The thermal interface material layer 170 may alternatively or additionally include thermally conductive paste, thermally conductive adhesive, thermally conductive film, thermally conductive adhesive, thermally conductive gap filler, thermally conductive pad (e.g., silicone), thermally conductive tape, or gel-type thermal interface material (e.g., cross-linked polymer film). In at least one embodiment, the thermal interface material layer 170 may include graphite, carbon nanotubes, phase change materials, etc. For example, the phase change material may include a polymer-based phase change material. In at least one embodiment, the phase of the phase change material can change from a solid state to a high-viscosity semi-liquid state at approximately 60 degrees Celsius. Other materials in the thermal interface material layer 170 are also contemplated within the scope of this invention.

[0146] like Figure 6 As further shown, the encapsulation cover 130 can be located on the thermal interface material layer 170 and can provide a cover for the intermediate module 120. For example, the encapsulation cover 130 can be formed of a metal, ceramic, or polymer material. Other suitable materials for the encapsulation cover 130 can also be used.

[0147] The package cover foot 130a of the package cover 130 can be attached to the package substrate 110. The package cover foot 130a can extend from the package cover portion 130p in a substantially vertical direction. The package cover foot 130a can be connected to the package substrate 110 via an adhesive layer 160. For example, the adhesive layer 160 may include an epoxy adhesive or a silicone adhesive. Other adhesives are included within the scope of this invention.

[0148] The encapsulation cover portion 130p (e.g., the body of the encapsulation cover 130) can be connected to the encapsulation cover foot portion 130a (e.g., the upper end of the encapsulation cover foot portion 130a). In at least one embodiment, the encapsulation cover portion 130p can be integrally formed with the encapsulation cover foot portion 130a as a single unit. Alternatively, the encapsulation cover portion 130p can be formed separately from the encapsulation cover foot portion 130a and attached to the encapsulation cover foot portion 130a by an adhesive (not shown). This adhesive can be substantially similar to the adhesive layer 160 described above.

[0149] For example, the 130p package cover can be... Figure 6 The package cover portion 130p extends in a plate-like shape within the xy-plane. The periphery of the package cover portion 130p may be substantially aligned with the periphery of the package cover foot portion 130a. The package cover portion 130p may be substantially parallel to the upper surface of the package substrate 110. The package cover portion 130p may include a central region formed above the interposer module 120. In at least one embodiment, the center point of the central region (in the xy-plane) may be substantially aligned with the center point of the interposer module 120 and / or the center point of the thermal interface material layer 170.

[0150] The encapsulation substrate 110 may have a substantially rectangular shape, with its length in the x-direction greater than its width in the y-direction. The encapsulation substrate 110 may also have a substantially square shape. The encapsulation cap foot 130a and the interposer module 120 may each have a substantially identical shape to the encapsulation substrate 110. Other shapes of the encapsulation substrate 110, encapsulation cap 130, and interposer module 120 are also considered within the scope of this invention. The interposer module 120 may be arranged at the center of the encapsulation substrate 110 such that the space between the interposer module 120 and the encapsulation cap foot 130a is substantially uniform around the periphery of the interposer module 120.

[0151] Figures 7A to 7F Various intermediate structures in a method of forming a package structure 100 according to one or more embodiments are shown. Figure 7A This is a vertical cross-sectional view of an intermediate structure of a package substrate 110 including an upper bonding pad 114a and a lower bonding pad 116a of a package substrate, according to one or more embodiments. A package substrate 110 including a core layer 112, an upper dielectric layer 114, and a lower dielectric layer 116 can be provided.

[0152] For example, the upper bonding pad 114a of the package substrate can be formed on the uppermost dielectric layer of the upper dielectric layer 114 of the package substrate. The upper bonding pad 114a of the package substrate can be formed to contact the metal interconnect structure 114b. The upper bonding pad 114a of the package substrate can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the upper dielectric layer 114 of the package substrate. The metal layer can then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the upper bonding pad 114a of the package substrate. Other suitable metal layer materials and etching processes may be included within the scope of this invention.

[0153] For example, the lower bonding pad 116a of the package substrate can be formed on the bottommost dielectric layer of the lower dielectric layer 116 of the package substrate. The lower bonding pad 116a of the package substrate can be formed to contact the metal interconnect structure 116b. The lower bonding pad 116a of the package substrate can be formed in a similar manner to the formation of the upper bonding pad 114a of the package substrate (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0154] Following formation, the upper bonding pad 114a and the lower bonding pad 116a of the package substrate may optionally undergo surface roughening treatment (e.g., copper zarazara (CZ) treatment). In the surface roughening treatment, the surfaces of the upper bonding pad 114a (e.g., copper surface) and the lower bonding pad 116a (e.g., copper surface) can be etched using an organic acid-based micro-etching solution to create an ultra-rough surface (e.g., copper surface). The unique rough copper surface topography in the upper bonding pad 114a and the lower bonding pad 116a can contribute to achieving high copper-resin adhesion.

[0155] Then, an upper passivation layer 110a and a lower passivation layer 110b of the package substrate can be formed on the upper bonding pad 114a and the lower bonding pad 116a of the package substrate, respectively. In at least one embodiment, the upper passivation layer 110a and the lower passivation layer 110b of the package substrate may each include a solder resist layer (e.g., a polymer material), also referred to as a solder resist film. The upper passivation layer 110a of the package substrate may also be referred to as the upper solder resist layer 110a, and the lower passivation layer 110b of the package substrate may also be referred to as the lower solder resist layer 110b.

[0156] The upper passivation layer 110a and the lower passivation layer 110b of the packaging substrate can be applied simultaneously. For example, the upper passivation layer 110a and the lower passivation layer 110b of the packaging substrate can be applied as liquid photosensitive films. For example, the liquid photosensitive film can be applied by screen printing or spraying onto the surface of the packaging substrate 110. The liquid photosensitive film can be applied to the upper bonding pad 114a and the lower bonding pad 116a of the packaging substrate. Alternatively, the upper passivation layer 110a and the lower passivation layer 110b of the packaging substrate can be applied as dry film liquid photosensitive films, which can be vacuum-laminated onto the surface of the packaging substrate 110 and the upper bonding pad 114a and the lower bonding pad 116a of the packaging substrate, respectively. The upper passivation layer 110a and the lower passivation layer 110b of the packaging substrate may be formed alternatively or additionally, for example, by chemical vapor deposition, physical vapor deposition, spin coating, lamination or other suitable deposition techniques.

[0157] The upper passivation layer 110a and the lower passivation layer 110b of the package substrate can be applied to have a thickness slightly larger than that of the upper bonding pad 114a and the lower bonding pad 116a of the package substrate, respectively. Alternatively, the upper passivation layer 110a and the lower passivation layer 110b of the package substrate can be applied to have an upper surface that is substantially coplanar with the upper surfaces of the upper bonding pad 114a and the lower bonding pad 116a of the package substrate, respectively.

[0158] Then, an opening O110a can be formed in the upper passivation layer 110a of the package substrate to expose the upper surface of the upper bonding pad 114a of the package substrate. An opening O110b can be formed in the lower passivation layer 110b of the package substrate to expose the upper surface of the lower bonding pad 116a of the package substrate. For example, the openings O110a and O110b can be formed using a photolithography process. In at least one embodiment, the openings O110a and O110b can be formed in a separate photolithography process.

[0159] The photolithography process (e.g., a process) used to form the opening O110a may include forming a patterned photoresist shield (not shown) on the upper passivation layer 110a of the packaging substrate, and etching the exposed upper surface of the upper passivation layer 110a of the packaging substrate through the opening in the photoresist shield (e.g., wet etching, dry etching, etc.). The photoresist shield can then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0160] The photolithography process for forming the opening O110b (e.g., a process) may include forming a patterned photoresist shield (not shown) on the lower passivation layer 110b of the packaging substrate, and etching the opening in the photoresist shield (e.g., wet etching, dry etching, etc.) to expose the upper surface of the lower passivation layer 110b of the packaging substrate. The photoresist shield may then be removed by ashing, dissolving the photoresist shield, or by consuming the photoresist shield during the etching process.

[0161] After forming an opening O110a in the upper passivation layer 110a of the packaging substrate and an opening O110b in the lower passivation layer 110b of the packaging substrate, the upper passivation layer 110a (upper solder resist layer) and the lower passivation layer 110b (lower solder resist layer) of the packaging substrate can be cured, for example by thermal curing or ultraviolet curing.

[0162] Figure 7B A vertical cross-sectional view of an intermediate structure according to one or more embodiments, in which an interposer module 120 can be mounted on a package substrate 110, is shown. For example, the interposer module 120 can be mounted on the package substrate 110 via a flip-chip bonding process. For example, the interposer module 120 can be positioned above the package substrate 110 using an electromechanical pick-and-place machine. Then, C4 bumps 121 (e.g., solder bumps) on the interposer module 120 can be passed through openings O110a in the upper passivation layer 110a of the package substrate (see [link to documentation]). Figure 7AThe intermediate structure, including the intermediate module 120 and the package substrate 110, is then lowered onto the upper bonding pad 114a of the package substrate. The intermediate structure can then be heated to cause the C4 bump 121 to collapse and solder to the upper bonding pad 114a of the package substrate. In at least one embodiment, laser-assisted bonding can be used to reflow the C4 bump 121 to attach the intermediate module 120 to the upper bonding pad 114a of the package substrate.

[0163] Figure 7C A vertical cross-sectional view is shown of an intermediate structure on a package substrate 110, according to one or more embodiments, where a package underfill layer 129 can be formed. The package underfill layer 129 can be formed by coating a liquid material (e.g., an epoxy-based polymer) onto the surface of the package substrate 110. Figure 7C As shown, the underfill layer 129 can be formed (e.g., injected) below and around the intermediate module 120 and the C4 bump 121 and the package substrate 110. The underfill layer 129 can then be cured in a box oven at a temperature between 120 degrees Celsius and 740 degrees Celsius for 60 to 120 minutes to provide a package underfill layer 129 with sufficient rigidity and mechanical strength.

[0164] After the bottom filler layer 129 of the package has cured, a test procedure can be performed to test the intermediate structures (e.g., the interposer module 120 and the package substrate 110). After the test procedure is completed, optional surface-mount components (not shown), such as dynamic random access memory (DRAM) components and multilayer ceramic capacitor (MWC) components, can be mounted on the surface of the package substrate 110 adjacent to the interposer module 120. In one embodiment, a 3D template can be used to define which areas can be covered by solder paste, and the DRAM components and MWC components can be attached to the package substrate 110 via solder bumps (e.g., a reflow process). The process for attaching the DRAM components and MWC components can be substantially similar to the process described above for attaching the interposer module 120 to the package substrate 110.

[0165] Figure 7D A vertical cross-sectional view is shown of an intermediate structure, according to one or more embodiments, on which a thermal interface material layer 170 may be formed (e.g., attached to) an intermediary module 120. The thermal interface material layer 170 may be coated to have a width in the x-direction and a length in the y-direction, and less than the full width and length of the thermal interface material layer 170, because the pressure of the encapsulation cap 130 will cause deformation of the thermal interface material layer 170 and lateral expansion of the thermal interface material layer 170 in the x and y directions.

[0166] In at least one embodiment, depending on the type of thermal interface material layer 170 used, a thermally conductive adhesive may or may not be applied to the upper surface of the intermediary module 120. The material of the thermal interface material layer 170 may be dispensed onto the upper surface of the intermediary module 120 in the form of a fluid (e.g., paste, gel, gruel, etc.) (or dispensed onto the thermally conductive adhesive, if present). In embodiments where the thermal interface material layer 170 comprises a solid material, the thermal interface material layer 170 may be pressed onto the intermediary module 120 or pressed onto the adhesive, if present.

[0167] After the thermal interface material layer 170 is formed on the interposer module 120, additional processes can be performed to prepare for attaching the package cap 130 to the package substrate. For example, these processes may include flux cleaning, pre-baking, and plasma processes.

[0168] Figure 7E A vertical cross-sectional view of an intermediate structure according to one or more embodiments, in which an adhesive layer 160 can be coated onto a package substrate 110, is shown. The adhesive layer 160 can be dispensed onto the package substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The dispensing tool can dispense the adhesive layer 160 in a frame shape around the intermediate module 120. During coating, the adhesive layer 160 can be sufficiently rigid to form semi-solid beads on the surface of the package substrate 110. In at least one embodiment, the viscosity of the adhesive layer 160 during coating can be 50,000 centipoise or greater. The shape of the semi-solid beads can remain substantially unchanged between the time of coating by the dispensing tool and the time of subsequent attachment of the package cap 130. The position of the frame shape of the adhesive layer 160 can correspond to the position of the package cap foot 130a of the package cap 130. Pressing the package cap 130 onto the adhesive layer 160 can deform the adhesive layer 160.

[0169] Figure 7F A vertical cross-sectional view is shown of an intermediate structure according to one or more embodiments, to which a package cap 130 may be attached (e.g., mounted) to a package substrate 110. In at least one embodiment, the package substrate 110 having an intermediary module 120 may be placed on a surface. The package cap 130 may then be positioned above the package substrate 110, for example, by an electromechanical pick-and-place mechanism. The package cap 130 may then be lowered above the intermediary module 120 and onto the package substrate 110. The package cap foot 130a of the package cap 130 may then be aligned with an adhesive layer 160 formed on the package substrate 110.

[0170] Then, by applying downward pressure to the package cover 130, the package cover 130 can be pressed down onto the thermal interface material layer 170, such that the package cover foot 130a of the package cover 130 can be attached to the package substrate 110 via the adhesive layer 160. In at least one embodiment, the downward pressure may cause the package cover plate portion 130p to press against the thermal interface material layer 170. The package cover 130 can then be clamped onto the package substrate 110 for a sufficient period of time to allow the adhesive layer 160 to cure and form a strong connection between the package substrate 110 and the package cover 130. In at least one embodiment, the adhesive layer 160 is a fast-curing adhesive that can be cured by exposure to ultraviolet light.

[0171] Clamping the package cap 130 onto the package substrate 110 may be performed additionally or alternatively, for example, by using a heat clamp module. The heat clamp module can apply a uniform force to the upper surface of the package cap 130. In one or more embodiments, the heat clamp module can apply downward pressure to the package cap 130. The adhesive layer 160 may be additionally or alternatively cured, for example, in a box oven, to provide an adhesive layer 160 with sufficient rigidity and mechanical strength.

[0172] Figure 7G A vertical cross-sectional view is shown of an intermediate structure in which a plurality of solder balls 110c are formed on a package substrate 110 according to one or more embodiments. The plurality of solder balls 110c can be formed on a lower bonding pad 116a of the package substrate through an opening O110b in the lower passivation layer 110b of the package substrate (see [link]). Figure 7A Solder balls 110c can be formed, for example, by an electroplating process. For instance, solder balls 110c can be formed below and between the package lead 130a and the intermediate module 120. Multiple solder balls 110c can form a ball grid array, which allows the package structure 100 to be securely mounted (e.g., by surface mount technology) on a substrate such as a printed circuit board and electrically coupled to the substrate.

[0173] At this point, one or more optional integrated passive components (e.g., passive components) (not shown) can be mounted on the board-side surface of the package substrate 110. The optional integrated passive components can be mounted using a mounting process similar to that described above for surface-mount components. Specifically, the mounting process may include a solder reflow process for electrically coupling the integrated passive components to the package substrate 110. After the optional integrated passive components are mounted to the package substrate 110, additional processes can be used to clean the package substrate 110 and maintain its surface. These integrated passive components may include, for example, flux cleaning, pre-baking, and plasma processes. An integrated passive component underfill layer (e.g., passive component underfill) can then be applied to the package substrate 110 and to the area beneath and around the integrated passive components. The integrated passive component underfill layer may include a material substantially the same as that used for the package underfill layer 129. The integrated passive component underfill layer can also be applied and cured in a manner substantially similar to that described above for coating and curing the package underfill layer 129.

[0174] After the optional integrated passive component underfill layer has cured, one or more procedures can be performed prior to final testing. These procedures may include, for example, one or more checks, such as checks performed using an optical inspection system (e.g., ICOS, HEXA, etc.) and a final visual inspection. These checks can provide a plausibility check of the completed package structure 100 (e.g., checking z-axis height, package appearance, etc.). The final testing procedures can then be performed on the package structure 100.

[0175] Figure 8 This is a detailed vertical cross-sectional view of an intermediary module 120 having a first alternative design according to one or more embodiments. (See attached image.) Figure 8 As shown, the mediator module 120 with the first alternative design can be connected with... Figures 1A to 1C The intermediate module 120 shown is substantially similar. Specifically, the passivation layer 202 in the first alternative design can correspond to the one described above. Figures 1A to 1C The two statements are essentially the same.

[0176] However, in the intermediate module 120 with the first alternative design, the passivation layer 202 may not be formed on the equipotential pads 200 outside the connection structure 128. That is, the passivation layer 202 may only be formed on the equipotential pads 200 between the connection structures 128. In particular, the outermost end of the passivation layer 202 may contact the inner sidewall of the connection structure 128. Therefore, the length of the passivation layer 202 in the x-direction may be substantially equal to the distance D6 between the inner sidewalls of the connection structures 128 (e.g., between 5 micrometers and 150 micrometers).

[0177] Reference Figures 1A to 7GThe intermediate module 120 may include an intermediate 10; a semiconductor die 140 located on the intermediate 10, wherein the semiconductor die 140 may include an equipotential pad 200 and a passivation layer 202 located on the equipotential pad 200; and a plurality of connection structures 128 connecting the equipotential pad 200 to the intermediate 10, wherein the passivation layer 202 may be located on the equipotential pad 200 between the plurality of connection structures 128.

[0178] In one embodiment, the thickness T202 of the passivation layer 202 may be less than 1 micrometer. In one embodiment, the plurality of connection structures 128 may include metal pillars 128b on the equipotential pad 200, metal bumps 128a on the interposer 10, and solder joints 128c between the metal pillars 128b and the metal bumps 128a. In one embodiment, the thickness of the equipotential pad 200 may be less than the thickness of the metal pillars 128b. In one embodiment, the thickness of the metal pillars 128b may be between 5 micrometers and 50 micrometers. In one embodiment, the spacing P between the plurality of connection structures 128 may be between 10 micrometers and 200 micrometers. In one embodiment, the semiconductor die 140 may include a plurality of through-silicon vias 201 electrically coupled to the equipotential pad 200. In one embodiment, the equipotential pad 200 may be located on the back side 140b of the semiconductor die 140, which may include a front-end process region 141 located on the front side of the semiconductor die 140, and a through-silicon via 201 may extend from the equipotential pad 200 to the front-end process region 141. In one embodiment, the number of the plurality of connection structures 128 may be less than the number of the plurality of through-silicon vias 201. In one embodiment, the plurality of connection structures 128 may include a pair of connection structures 128, and the plurality of through-silicon vias 201 may include a pair of external through-silicon vias 201o located above the pair of connection structures 128 and an internal through-silicon via 201i located between the external through-silicon vias 201o. In one embodiment, the internal through-silicon via 201i may protrude from the equipotential pad 200 located between the plurality of connection structures 128. In one embodiment, the thickness T200 of the equipotential pad 200 may be less than 30% of the distance D4 between the semiconductor die 140 and the interposer 10.

[0179] Refer again Figures 1A to 7GThe method of forming the intermediate module 120 may include forming a semiconductor die 140 including an equipotential pad 200, a passivation layer 202 on the equipotential pad 200, and a plurality of metal pillars 128b on the equipotential pad 200; forming an intermediate 10 including a plurality of metal bumps 128a; and forming a plurality of connection structures 128 by bonding the plurality of metal pillars 128b to the plurality of metal bumps 128a respectively, and attaching the semiconductor die 140 to the intermediate 10, wherein the passivation layer 202 may be located on the equipotential pad 200 between the plurality of connection structures 128.

[0180] In one embodiment, forming a semiconductor die 140 may include forming a passivation layer 202 with a thickness of less than 1 micrometer. In one embodiment, bonding a plurality of metal pillars 128b to a plurality of metal bumps 128a may include forming a plurality of solder joints 128c between the plurality of metal pillars 128b and the plurality of metal bumps 128a. In one embodiment, forming a semiconductor die 140 may include forming a plurality of solder layers 128cL on the plurality of metal pillars 128b, and forming a plurality of solder joints 128c may include reflowing the plurality of solder layers 128cL. In one embodiment, forming a semiconductor die 140 may further include forming a plurality of through-silicon vias 201, and forming equipotential pads 200 on the plurality of through-silicon vias 201 on the back side 140b of the semiconductor die 140, wherein the plurality of through-silicon vias 201 extend from the equipotential pads 200 to the front-end process region of the semiconductor die 140. The plurality of connection structures 128 may include a pair of connection structures 128, and forming a plurality of through-silicon vias 201 may include forming a pair of external through-silicon vias 201o located above the pair of connection structures 128, and forming internal through-silicon vias 201i located between the external through-silicon vias 201o.

[0181] Refer again Figures 1A to 7G The package structure 100 may include a package substrate 110, an interposer module 120, and a package cap 130. The interposer module 120 is located on the package substrate 110 and includes an interposer 10, a semiconductor die 140 located on the interposer 10, and a plurality of connection structures 128. The semiconductor die 140 may include an equipotential pad 200, a passivation layer 202 located on the equipotential pad 200, and a plurality of connection structures 128 connecting the equipotential pad 200 to the interposer 10, wherein the passivation layer 202 may be located on the equipotential pad 200 between the plurality of connection structures 128. The package cap 130 is located on the interposer module 120 and attached to the package substrate 110.

[0182] In one embodiment, the package structure 100 may further include a thermal interface material layer 170 located on the intermediary module 120, wherein the package cover 130 may include a package cover portion 130p located on the thermal interface material layer 170 and a package cover foot portion 130a protruding from the package cover portion 130p and attached to the package substrate 110.

[0183] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that they can readily use this invention as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this invention.

Claims

1. An interposer module, comprising: an interposer; a semiconductor die on the interposer, wherein the semiconductor die includes an equipotential pad and a passivation layer on the equipotential pad; and a plurality of connection structures connecting the equipotential pad to the interposer, wherein the passivation layer is on the equipotential pad between the plurality of connection structures.

2. The interposer module of claim 1, wherein a thickness of the passivation layer is less than 1 micrometer.

3. The interposer module of claim 1, wherein the plurality of connection structures includes: a metal stud on the equipotential pad; a metal bump on the interposer; and a solder joint between the metal stud and the metal bump.

4. The interposer module of claim 3, wherein a thickness of the equipotential pad is less than a thickness of the metal stud.

5. The interposer module of claim 1, wherein the semiconductor die includes a plurality of through silicon vias electrically coupled to the equipotential pad.

6. The interposer module of claim 5, wherein the equipotential pad is on a backside of the semiconductor die, the semiconductor die includes a front-end-of-line region on a frontside thereof, and the plurality of through silicon vias extend from the equipotential pad to the front-end-of-line region.

7. The interposer module of claim 5, wherein a number of the plurality of connection structures is less than a number of the plurality of through silicon vias.

8. The interposer module of claim 5, wherein the plurality of connection structures includes a pair of connection structures, and the plurality of through silicon vias includes a pair of outer through silicon vias above the pair of connection structures and an inner through silicon via between the pair of outer through silicon vias.

9. The interposer module of claim 8, wherein the inner through silicon via protrudes from the equipotential pad at a location between the plurality of connection structures.

10. A package structure, comprising: a package substrate; an interposer module on the package substrate, comprising: an interposer; a semiconductor die on the interposer, wherein the semiconductor die includes an equipotential pad and a passivation layer on the equipotential pad; and a plurality of connection structures connecting the equipotential pad to the interposer, wherein the passivation layer is on the equipotential pad between the plurality of connection structures; and a package cap on the interposer module and attached to the package substrate. ​ ​

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