Chip sorting equipment

Abstract

The embodiment of the utility model provides chip sorting equipment. The chip sorting equipment comprises a buffer station module, a first station and a plurality of second stations, the first station is used for placing a target wafer; a plurality of chips are cut on the target wafer; the buffer station module and the plurality of second stations are arranged around the first station and are used for placing carriers; each second station is used for placing a carrier, and each carrier is used for loading chips of the same grade; wherein when the chips of the same level are transferred from the target wafer to one carrier corresponding to the multiple second stations, the carriers in the buffer station module are replaced to the other second stations.

Description

Technical Field

[0001] This disclosure relates to the field of chip processing equipment, and includes, but is not limited to, a chip sorting device. Background Technology

[0002] Advanced packaging technologies not only enable tighter connections between chips but also allow for a greater number of input / output (I / O) ports, improving the performance and functionality of the package structure. Classifying chips by grade ensures that chips within the package structure are of similar grade, thereby reducing chip waste.

[0003] In related technologies, chips are sorted by grade using single or dual stations in chip sorting equipment; however, as the number of chip grades increases, sorting by single or dual stations can easily lead to low sorting efficiency and reduce production efficiency. Utility Model Content

[0004] In view of this, the present disclosure provides a chip sorting device, including: a buffer station module, a first station, and a plurality of second stations;

[0005] The first workstation is used to place the target wafer; the target wafer has multiple chips diced on it;

[0006] The buffer station module and multiple second stations are arranged around the first station and are all used to place carriers; each second station is used to place one carrier, and each carrier is used to load the chip of the same grade.

[0007] When a chip of the same grade is transferred from the target wafer to a carrier corresponding to one of the plurality of second workstations, the carrier in the buffer workstation module is replaced on the remaining second workstations.

[0008] In some embodiments, the chip sorting device includes two second stations; wherein...

[0009] When the chip of the same grade is transferred from the target wafer to the carrier at one of the second workstations, the carrier in the buffer workstation module is replaced at another of the second workstations.

[0010] In some embodiments, the buffer station module includes a support column, multiple buffer stations, and multiple fixed structures;

[0011] Multiple fixed structures are arranged sequentially and fixed to the support column from the extension direction of the support column;

[0012] Each of the aforementioned buffer stations is connected to the corresponding fixed structure for placing a spare carrier.

[0013] In some embodiments, the chip sorting device further includes: a transfer arm;

[0014] The transmission arm is used to hold the carrier in the buffer station module and place it on the empty second station, or to hold the carrier on the second station and place it in the buffer station module.

[0015] In some embodiments, the transfer arm includes: a robotic arm and a picking structure;

[0016] The picking structure is located at the end of the robotic arm and is used to pick up the carrier and move the carrier under the drive of the robotic arm.

[0017] In some embodiments, the chip sorting device further includes: a transmission probe;

[0018] The transmission probe is used to transfer chips of the same grade from the target wafer to one of the carriers corresponding to the plurality of second workstations, based on the qualified chip distribution map corresponding to the target wafer.

[0019] In some embodiments, the chip sorting device further includes: a driving device;

[0020] The driving device is used to drive the transmission probe and the transmission arm to move, and the movement accuracy of the transmission probe is greater than that of the transmission arm.

[0021] In some embodiments, the carrier includes: a frame and a cutting membrane;

[0022] The dicing film is attached to the frame and is used to fix the chip transferred from the target wafer onto the frame.

[0023] In some embodiments, the chip sorting device further includes: a cell;

[0024] The cassette contains multiple wafers and is used to provide one of the multiple wafers as the target wafer to the first work station.

[0025] In some embodiments, the total number of the second workstation and the buffer workstation is greater than or equal to the number of carriers + 1, and the number of carriers is greater than or equal to the number of chip classification levels.

[0026] This disclosure provides a chip sorting device, including: a buffer station module, a first station, and a plurality of second stations; the first station is used to place a target wafer; a plurality of chips are diced on the target wafer; the buffer station module and the plurality of second stations are all disposed around the first station and are all used to place carriers; each second station is used to place one carrier, and each carrier is used to load chips of the same grade; wherein, when chips of the same grade are transferred from the target wafer to a corresponding carrier on one of the plurality of second stations, the carrier in the buffer station module is replaced on the remaining second stations.

[0027] Because the chip sorting equipment is equipped with a buffer station module, when transferring chips of the same grade on the target wafer to corresponding carriers on multiple second stations, a carrier can be retrieved from the buffer station module and exchanged with the other carriers (e.g., carriers that have already been loaded with chips) on multiple second stations. In other words, by setting up the buffer station module, chip sorting (transfer) and carrier replacement operations can be performed simultaneously on multiple second stations, thereby ensuring the continuity and efficiency of chip sorting. Attached Figure Description

[0028] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0029] Figure 1 This is a single-station chip sorting device in related technologies;

[0030] Figure 2 A schematic diagram of the structure of a chip sorting device provided in this embodiment of the present disclosure. Figure 1 ;

[0031] Figure 3 A schematic diagram of the structure of a chip sorting device provided in this embodiment of the present disclosure. Figure 2 ;

[0032] Figure 4 A schematic diagram of the structure of a chip sorting device provided in this embodiment of the present disclosure. Figure 3 ;

[0033] Figure 5 A schematic diagram of the structure of a chip sorting device provided in this embodiment of the present disclosure. Figure 4 ;

[0034] Figure 6 This is a schematic diagram of the structure of a buffer station module provided in an embodiment of the present disclosure;

[0035] Figure 7This is a schematic diagram of the structure of a carrier provided in an embodiment of the present disclosure;

[0036] Figure 8 This is a schematic diagram of the structure of a transmission arm provided in an embodiment of the present disclosure;

[0037] Figure 9 This is a schematic diagram of the structure of a transmission probe provided in an embodiment of this disclosure. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] Currently, wafer-to-wafer (W2W) bonding and chip-to-wafer (D2W) bonding are two commonly used bonding technologies. Compared to W2W bonding, D2W bonding allows for flexible selection of chip grades, ensuring that the chips bonded to each other have similar grades, thereby reducing chip waste.

[0044] Figure 1 This is a single-station chip sorting device 10 in related technologies. The chip sorting device 10 includes a first station 11 and a second station 12, which are used to place wafers and carriers, respectively. The wafers are diced with chips of different grades (i.e., chips 13a to 13d). The working process of the chip sorting device 10 is as follows: multiple chips 13a of the same grade on the first station 11 (i.e., the wafer) are transferred to the carrier on the second station 12 (e.g., ...). Figure 1 As shown, the carrier on the second station 12 is replaced, and then multiple chips of the next level (such as chip 13b) are transferred. This process is repeated until all the chips on the wafer are transferred to the corresponding carrier, thereby completing the sorting of chips of different levels.

[0045] Since the chip sorting device 10 only includes one second station 12, after sorting chips of one grade, the carrier needs to be changed before sorting can continue, resulting in low chip sorting efficiency. Furthermore, although the chip sorting efficiency can be increased by increasing the number of second stations (e.g., a dual-station chip sorting device), as the number of chip grades increases, the carrier change time at the second station will still affect the chip sorting efficiency.

[0046] Based on this, the present disclosure provides a chip sorting device; by setting a buffer station module in the chip sorting device, both chip sorting (transfer) and carrier replacement operations can be performed simultaneously, thereby ensuring the continuity and efficiency of chip sorting.

[0047] The chip sorting device in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0048] Please refer to Figure 2 This disclosure provides a chip sorting device 100, including: a buffer station module 110, a first station 120, and a plurality of second stations 130; the first station 120 is used to place a target wafer 150; a plurality of chips are diced on the target wafer 150; the buffer station module 110 and the plurality of second stations 130 are disposed around the first station 120 and are all used to place carriers 140; each second station 130 is used to place one carrier 140, and each carrier 140 is used to load chips of the same grade; wherein, when chips of the same grade are transferred from the target wafer 150 to a corresponding carrier 140 on the plurality of second stations 130, the carrier 140 in the buffer station module 110 is replaced on the remaining second stations 130.

[0049] In this embodiment of the disclosure, the chips on the target wafer 150 can be classified into multiple levels based on visual inspection, electrical performance testing, reliability testing, etc.; for example, the chips on the target wafer 150 can be classified into two, three, or four levels, etc. Figure 2 The diagram shows the known good die map (KGD map) of target wafer 150. It can be seen that the chips in target wafer 150 are divided into four grades (distinguished by different fillers), namely chip 151a, chip 151b, chip 151c and chip 151d.

[0050] In this embodiment, the first station 120 can be understood as the location where the target wafer 150 is placed; similarly, the second station 130 can be understood as the location where the carrier 140 is placed; the buffer station module 110 is used to place multiple spare carriers 140. To facilitate the distinction between the stations in the figure and the carriers / target wafers placed on the stations, the area of ​​the stations shown in the figure is larger than that of the carriers / target wafers.

[0051] In this embodiment, each carrier 140 is used to load chips of the same grade to ensure that the chips are classified and stored in an orderly manner. The spare carriers 140 placed in the buffer station module 110 are carriers that have not undergone the loading process, i.e., carriers not placed on the second station 130; wherein, any spare carrier 140 may hold multiple chips of the same grade, or it may be empty (i.e., a blank carrier). Furthermore, the shape of the carrier 140 can be any suitable shape; for example, circular (e.g.,...). Figure 2 (as shown), rectangles, etc.

[0052] In this embodiment of the disclosure, the buffer station module 110 includes multiple buffer stations, each buffer station being used to place a spare carrier; wherein the number of buffer stations is greater than or equal to the number of spare carriers 140 plus one. For example, Figure 2The chips in the target wafer 150 are divided into four levels, which requires four carriers to carry the chips of these four levels respectively. At this time, the number of buffer stations is at least more than three. This is because when two carriers are located on two second stations 130, two idle carriers can be placed on two buffer stations, and at least one additional buffer station is reserved to temporarily store the chips when the carriers are replaced.

[0053] In this embodiment of the disclosure, the number and position of the second workstation 130 can be set according to actual needs; for example... Figure 2 and Figure 3 The number of the second workstation 130 is two; among them, Figure 2 The two second stations 130 are located on both sides of the first station, which reduces the distance during chip transfer and improves the accuracy of transfer. Figure 3 The two second workstations 130 are located on one side of the first workstation 120, thus allowing for a more flexible layout of the workstations. For example, Figure 4 The number of the second workstation 130 is three, of which, Figure 4 The three second stations 130 are located on the three sides of the first station, which reduces the distance the chip is transferred and improves the accuracy of the transfer. Similarly, the position of the buffer station module 110 can be set according to actual needs.

[0054] It should be noted that the distance between the second station 130 and the first station 120 does not exceed the maximum distance that can be reached when transferring chips, and the distance between the buffer station module 110 and the first station 120 does not exceed the maximum distance that can be reached when changing the carrier.

[0055] In this embodiment of the disclosure, when the chip sorting device 100 is operating, the number of second workstations 130 (or carriers 140) used can be selected according to actual needs. For example, Figures 2 to 4 The number of second workstations 130 (or carriers 140) used is two. Further, "when chips of the same grade are transferred from the target wafer 150 to a corresponding carrier 140 on multiple second workstations 130, the carrier 140 in the buffer workstation module 110 is replaced on the remaining second workstations 130" means that when chips of the same grade are transferred from the target wafer 150 to a carrier 140 located on a second workstation 130, the carrier 140 in the buffer workstation module 110 can be replaced with a carrier 140 that has already been transferred on the remaining second workstations 130, or the carrier 140 in the buffer workstation module 110 can be placed on an empty second workstation 130.

[0056] It should be noted that after all the chips in the target wafer 150 have been transferred, the target wafer 150 on the first station 120 can be replaced, and the chip-level sorting can continue on the newly replaced wafer.

[0057] In this embodiment of the disclosure, since the chip sorting equipment is equipped with a buffer station module, when transferring chips of the same grade on the target wafer to the corresponding carriers on multiple second stations, a spare carrier can be retrieved from the buffer station module and replaced with the remaining carriers (e.g., carriers that have already been loaded with chips) on multiple second stations. In other words, by setting up the buffer station module, chip sorting (transfer) and carrier replacement operations can be performed simultaneously on multiple second stations, thereby ensuring the continuity and efficiency of chip sorting.

[0058] In some embodiments, while a greater number of second workstations increases chip sorting efficiency, the footprint (or space) of the chip sorting equipment 100 also increases, leading to higher manufacturing costs. Therefore, please refer to... Figure 5 The chip sorting equipment 100 may include two second stations 130; wherein, when a chip 151 of the same grade is transferred from the target wafer 150 to a carrier 140 on one second station 130, the carrier 140 in the buffer station module 110 is replaced on the other second station 130.

[0059] For details, please continue to refer to [the website / information]. Figure 5 The first station 120 is used to place the target wafer 150. The chips in the target wafer 150 are divided into four levels (distinguished by different fill types), namely chip 151a, chip 151b, chip 151c, and chip 151d. Each of the two second stations 130 holds a carrier 140. First, all chips 151b of the same level can be transferred to carrier 140 on the left second station 130; next, chips 151a of the same level can be transferred to carrier 140 on the right second station 130 (e.g., ...). Figure 5 (As shown by the dashed arrow in the middle), and the carrier 140 in the buffer station module 110 can be replaced with the carrier 140 on the second station 130 on the left (e.g., Figure 5 (As shown by the solid arrow in the middle), and so on, until all levels of chips have been transferred to the corresponding carrier 140.

[0060] It should be noted that, Figure 5 The diagram shows the chip sorting (transfer) and carrier replacement process.

[0061] In this embodiment of the disclosure, when performing both chip sorting (transfer) and carrier replacement operations simultaneously, the minimum number of second workstations 130 is two. Therefore, setting two second workstations 130 can not only minimize the manufacturing cost of the chip sorting equipment 100, but also ensure the continuity and efficiency of chip sorting.

[0062] In some embodiments, please refer to Figure 6 The buffer station module 110 includes a support column 111, multiple buffer stations 112 and multiple fixed structures 113; the multiple fixed structures 113 are arranged and fixed to the support column 111 in sequence from the extension direction of the support column 111 (as shown in the Z-axis direction); each buffer station 112 is connected to a fixed structure 113 and is used to place a spare carrier 140.

[0063] It should be noted that, Figure 6 The front and side views of the buffer station module 110 are shown. Figures 2 to 5 A top view of the buffer station module 110 is shown.

[0064] In this embodiment, multiple buffer stations 112 are arranged sequentially along the extension direction of the support column 111 (as shown in the Z-axis direction). This improves space utilization and maximizes the number of buffer stations 112 within the limited space of the chip sorting equipment 100. As a result, the more carriers 140 placed in the buffer station module 110, the better the continuity of the process flow when sorting chips from multiple wafers sequentially.

[0065] In some embodiments, please combine Figure 5 and Figure 6 The total number of the second station 130 and the buffer station 112 is greater than or equal to the number of carriers 140 + 1, and the number of carriers 140 is greater than or equal to the number of chip classification levels.

[0066] This is because: First, when the number of carriers 140 is greater than or equal to the number of chip classification levels, each carrier 140 can hold chips of the same level; for example, if the chips in the target wafer 150 are divided into four levels, the number of carriers 140 must be greater than or equal to 4, thus ensuring that chips of the same level are placed on the same carrier 140. Second, when the total number of second workstations 130 and buffer workstations 112 is greater than or equal to the number of carriers 140 + 1, when all second workstations 130 and all buffer workstations 112 hold one carrier 140, at least one additional buffer workstation 112 can be reserved for temporary storage when carriers 140 are replaced, avoiding production interruptions caused by having nowhere to put the replaced carriers 140, and ensuring the continuity of the process flow; for example, if the number of carriers 140 is 4 and the number of second workstations 130 is two, then the number of buffer workstations 112 must be greater than or equal to 5. Figure 6 (As shown, there are 13).

[0067] In this embodiment, the number of fixing structures 113 and buffer stations 112 are the same, used to fix the corresponding buffer stations 112 to the support columns 111. It should be noted that the buffer station 112 can be understood as the position for placing the spare carrier 140.

[0068] In some embodiments, please combine Figure 5 and Figure 7 The carrier 140 includes a frame 141 and a dicing film 142; the dicing film 142 is attached to the frame 141 (or the frame is placed on the dicing film) and is used to fix the chip 151 transferred from the target wafer 150 onto the frame 141.

[0069] In this embodiment of the disclosure, the frame 141 can be, for example, a metal frame, a plastic polymer frame, or a metal-coated (ceramic) frame, etc.; the frame 141 provides a stable support platform; wherein... Figure 7 An optional frame 141 is shown; in other embodiments, the shape of the frame 141 can be any suitable shape, such as a circle, a rectangle, etc.

[0070] In this embodiment of the disclosure, the cutting film 142 can be any suitable fixing material; for example, it can be an ultraviolet (UV) light-irradiated film. The UV light-irradiated film has greater adhesion before light irradiation, so the chip can be fixed on the UV light-irradiated film. It is understood that the carrier 140 placed on the second station 130 and the buffer station 112 has a UV light-irradiated film that has not been irradiated, thus having adhesion, which can be used to fix the chip.

[0071] In addition, the UV light-illuminated film has reduced its adhesion to 1 / 1000 of its original value after light irradiation; the target wafer 150 is placed on the first station 120 through a carrier, wherein the UV light-illuminated film in the carrier has been irradiated, resulting in lower adhesion, so that the chip on the target wafer can be removed from the UV light-illuminated film.

[0072] In some embodiments, please combine Figure 5 and Figure 8 The chip sorting equipment 100 also includes: a transfer arm 160 (i.e., a chip carrier transfer arm); the transfer arm 160 is used to hold the carrier 140 on the buffer station module 110 (i.e., the buffer station) and place it on an empty second station 130, or to hold the carrier 140 on the second station 130 and place it in the buffer station module 110 (e.g., ...). Figure 5 (As indicated by the solid arrow).

[0073] For specific details, please refer to... Figure 5 and Figure 8 The transfer arm 160 places the carrier 140 on the second station 130 on the left into an empty buffer station in the buffer station module 110; then, the transfer arm 160 attaches a spare carrier 140 to the buffer station module 110 and places it on the second station 130 on the left; thus, the replacement of the carrier 140 on the second station 130 and the carrier 140 in the buffer station module 110 is completed. The replacement (or placement) of the carrier at any station is similar and will not be described in detail here.

[0074] In this embodiment of the disclosure, by setting up the transmission arm 160, the carrier can be replaced during the chip sorting process, that is, the carrier replacement step is independent of the chip sorting step, making the chip sorting process more efficient.

[0075] In some embodiments, please refer to Figure 8 The transfer arm 160 includes a robotic arm 161 and a picking structure 162. The picking structure 162 is located at the end of the robotic arm 161 and is used to pick up the carrier 140 and move the carrier 140 under the drive of the robotic arm.

[0076] It should be noted that, Figure 8 The diagram illustrates one alternative structure of the robotic arm 161. In other embodiments, the robotic arm 161 may have other suitable structures, and this disclosure is not limiting in this regard. The grasping structure 162 can grasp the carrier 140 by any grasping method (such as clamping, adsorption, etc.); the grasping structure 162 may be any suitable shape, for example... Figure 8 The fork-shaped structure shown facilitates the forking of the carrier 140 (or frame 141).

[0077] In this embodiment of the disclosure, the robotic arm 161 can flexibly adjust the picking angle of the picking structure 162, making the operation more flexible; for example, when handling the carriers 140 densely arranged in the buffer station module 110 (or buffer station 112), it can adapt to multiple angles and reduce the risk of damage.

[0078] In some embodiments, please combine Figure 5 and Figure 9 The chip sorting equipment 100 also includes: a transfer probe 170 (i.e., a chip transfer probe); the transfer probe 170 is used to transfer chips 151 of the same grade from the target wafer 150 to a carrier 140 corresponding to multiple second workstations 130 according to the qualified chip distribution map corresponding to the target wafer 150.

[0079] Specifically, the transmission probe 170 includes a probe body 171, a gas cavity 172, and a dielectric layer 173. The probe body 171 can be made of stainless steel, high-strength steel, etc., to ensure the strength and stability of the transmission probe 170 during operation. The gas cavity 172 is used for evacuation to achieve vacuum adsorption. The dielectric layer 173 is made of polymer materials, ceramic materials, etc., to ensure stable contact with the chip during vacuum adsorption and to ensure the chip remains intact.

[0080] Please combine Figure 5 and Figure 9 The transmission probe 170 picks up the chip via vacuum adsorption and transfers the chip 151a of the same grade to the carrier 140 on the second station 130 on the right (e.g., Figure 5 (As shown by the dashed arrow). The transfer method for chips of any level is similar, and will not be elaborated further here.

[0081] It should be noted that the transmission probe 170 does not need to identify the chip's grade; it only receives instructions to pick up the chip for transfer.

[0082] In this embodiment of the disclosure, since the chip transfer process requires high precision (e.g., ±30μm), the chip transfer process can be precisely controlled by setting the transfer probe 170, thereby reducing errors and ensuring product efficiency.

[0083] In some embodiments, the chip sorting device 100 further includes: a driving device (not shown); the driving device is used to drive the transmission probe 170 and the transmission arm 160 to move, wherein the movement accuracy of the transmission probe 170 is greater than the movement accuracy of the transmission arm 160.

[0084] In this embodiment, the transfer probe 170 is used to transfer chips, therefore, the transfer probe 170 requires high precision, for example, ±30μm. The transfer arm 160 is used to replace the carrier 140, therefore, compared to the precision required by the transfer probe 170, the precision requirement of the transfer arm 160 is lower. That is, because the transfer arm 160 has lower precision requirements, its movement amplitude and speed can be increased, thereby completing the replacement of the carrier 140 in a short time and reducing replacement waiting time. At the same time, the high precision of the transfer probe 170 ensures the accuracy and reliability of chip transfer, avoiding chip damage due to insufficient precision. This makes the resource allocation in the chip sorting device 100 reasonable and avoids resource waste.

[0085] In some embodiments, the chip sorting device 100 further includes: a wafer cassette (not shown); the wafer cassette being loaded with a plurality of wafers for providing one of the plurality of wafers as a target wafer 150 to a first station 120.

[0086] In this embodiment, after all chips in the target wafer 150 have been transferred, the target wafer 150 on the first station 120 is replaced by a wafer from the wafer cassette, and the newly replaced wafer continues to be sorted at the chip level. This results in a high degree of automation and continuous operation of the chip sorting equipment, ensuring both continuity and efficiency in chip sorting.

[0087] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0088] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0089] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip sorting apparatus, characterized by comprising: The chip sorting device comprises: a buffer station module, a first station and a plurality of second stations; the first station is used for placing a target wafer, and the target wafer is cut with a plurality of chips; the buffer station module and the plurality of second stations are arranged around the first station, and each is used for placing a carrier; each second station is used for placing a carrier, and each carrier is used for loading the chips of the same grade; wherein, when the chips of the same grade are transferred from the target wafer to the corresponding carrier on the second station, the carriers in the buffer station module are replaced to the remaining second stations.

2. The chip sorting apparatus according to claim 1, wherein The chip sorting device comprises two second stations; wherein, when the chips of the same grade are transferred from the target wafer to the carrier on one second station, the carriers in the buffer station module are replaced to the other second station.

3. The chip sorting apparatus according to claim 1, wherein The buffer station module comprises a support column, a plurality of buffer stations and a plurality of fixing structures; a plurality of fixing structures are arranged in sequence on the support column from the extension direction of the support column; each buffer station is connected with the corresponding fixing structure and is used for placing a carrier.

4. The chip sorting apparatus according to claim 1, wherein The chip sorting device further comprises a transmission arm; the transmission arm is used for holding and placing the carrier in the buffer station module on the idle second station, or holding and placing the carrier on the second station in the buffer station module.

5. The chip sorting apparatus according to claim 4, wherein The transmission arm comprises a mechanical arm and a taking structure; the taking structure is located at the end of the mechanical arm and is used for taking the carrier and carrying the carrier under the driving of the mechanical arm.

6. The chip sorting apparatus according to claim 4, wherein The chip sorting device further comprises a transmission probe; the transmission probe is used for transferring the chips of the same grade from the target wafer to the corresponding carrier on the second station according to the distribution map of the qualified chips corresponding to the target wafer.

7. The chip sorting apparatus according to claim 6, wherein The chip sorting device further comprises a driving device; the driving device is used for driving the transmission probe and the transmission arm to move, and the movement precision of the transmission probe is greater than that of the transmission arm.

8. The chip sorting apparatus according to claim 1, wherein The carrier comprises a frame and a cutting film; the cutting film is attached to the frame and is used for fixing the chips transferred from the target wafer on the frame.

9. The chip sorting apparatus according to claim 1, wherein The chip sorting device further comprises a wafer box; the wafer box is loaded with a plurality of wafers and is used for providing one of the plurality of wafers as the target wafer to the first station.

10. The chip sorting apparatus according to claim 2, wherein The total number of the second stations and the buffer stations is greater than or equal to the number of carriers + 1, and the number of carriers is greater than or equal to the number of chip grades.

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