Steel rail eddy current flaw detection circuit

Abstract

The utility model discloses an eddy current flaw detection circuit for a steel rail. The eddy current flaw detection circuit comprises a control CPU, an excitation pulse generator, an excitation pulse voltage regulation module, an eddy current sensor and a signal demodulation module, wherein the control CPU is connected with the excitation pulse generator and executes commands issued by a computer, the excitation pulse generator generates excitation pulses, the excitation pulse generator is connected with the excitation pulse voltage adjusting module, and the amplitude value of the excitation pulses is adjusted through the excitation pulse voltage adjusting module. The excitation pulse voltage regulation module is connected with the eddy current sensor, and an alternating electromagnetic field generated by an excitation unit in the eddy current sensor acts on the steel rail; the eddy current sensor is connected with a signal demodulation module, a receiving unit in the eddy current sensor receives an electromagnetic signal fed back by the steel rail, the signal demodulation module carries out amplitude demodulation and phase demodulation, and an analog signal is output to reflect a defect characteristic value. The device is high in detection sensitivity and stability, and the type and frequency of excitation pulses can be flexibly set.

Description

Technical Field

[0001] This utility model belongs to the field of non-destructive testing technology and relates to the detection circuit of a rail eddy current flaw detection device. Background Technology

[0002] As a crucial load-bearing component of railway transportation, rails directly withstand the pressure and impact of train wheels. Damage frequently occurs on the railheads, affecting train stability and passenger comfort. Severe rail damage can pose a significant safety hazard. Therefore, regular rail inspections are necessary.

[0003] Eddy current testing is a common non-destructive testing method, ideally suited for detecting defects on the outer surface of rails. The eddy current testing probe does not require direct contact with the rail and no coupling agent is needed, enabling high-speed, automated testing. Utility Model Content

[0004] To address the aforementioned problems, this invention proposes a rail eddy current flaw detection circuit that can effectively detect minor defects on the rail surface, such as cracks, fish scale patterns, pits, chips, and scratches.

[0005] This utility model relates to a rail eddy current flaw detection circuit, which includes a control CPU, an excitation pulse generator, an excitation pulse voltage adjustment module, an eddy current sensor, and a signal demodulation module.

[0006] Among them, the control CPU connects to the excitation pulse generator, executes commands issued by the computer, and controls the excitation pulse generator to generate excitation pulses.

[0007] The excitation pulse generator is connected to the excitation pulse voltage adjustment module, which adjusts the amplitude of the excitation pulse.

[0008] The excitation pulse voltage adjustment module is connected to the excitation unit in the eddy current sensor, and the alternating electromagnetic field generated by the excitation unit acts on the rail. The receiving unit in the eddy current sensor is connected to the signal demodulation module. The receiving unit in the eddy current sensor receives the electromagnetic signal fed back from the rail, and the amplitude demodulation module and phase demodulation module in the signal demodulation module perform amplitude demodulation and phase demodulation, outputting an analog signal reflecting the defect characteristic value.

[0009] The advantages of this utility model are:

[0010] 1. The rail eddy current flaw detection circuit of this utility model has high detection sensitivity, strong stability, and the excitation pulse type and frequency can be flexibly set;

[0011] 2. The eddy current testing circuit for rails of this utility model is suitable for eddy current testing of various metal materials and can also be widely used in the testing of steel pipes, steel plates and other metal structural components. Attached Figure Description

[0012] Figure 1 This is a block diagram of the overall structure of the rail eddy current flaw detection circuit of this utility model;

[0013] Figure 2 This is a structural diagram of the control CPU circuit in the rail eddy current flaw detection circuit of this utility model;

[0014] Figure 3 This is a circuit diagram of the excitation pulse generation module in the rail eddy current flaw detection circuit of this utility model;

[0015] Figure 4 This is a circuit diagram of the excitation pulse voltage adjustment module in the rail eddy current flaw detection circuit of this utility model;

[0016] Figure 5 This is a circuit diagram of the amplitude signal demodulation module in the rail eddy current flaw detection circuit of this utility model;

[0017] Figure 6 This is a circuit diagram of the phase signal demodulation module in the rail eddy current flaw detection circuit of this utility model.

[0018] In the picture:

[0019] 1-Control CPU; 2-Excitation pulse generation module; 3-Excitation pulse voltage adjustment module

[0020] 4-Eddy current sensor; 5-Amplitude signal demodulation module; 6-Phase signal demodulation module Detailed Implementation

[0021] This utility model relates to a rail eddy current flaw detection circuit, comprising a control CPU 1, an excitation pulse generation module 2, an excitation pulse voltage adjustment module 3, an eddy current sensor 4, an amplitude signal demodulation module 5, and a phase signal demodulation module 6, as follows: Figure 1 As shown.

[0022] like Figure 2 As shown, the control CPU1 (U0) uses an STM32F103 microcontroller and establishes communication with the computer via the TCP / IP communication protocol. The computer can send parameter setting commands to the control CPU1 (U0), including the type, frequency, and amplitude of the excitation pulse, as well as the signal amplification gain and A / D sampling rate. The control CPU1 (U0) executes the parameter setting commands sent by the computer, controlling the coordinated operation of each functional module of the eddy current detection circuit. The excitation pulse generation module (U_3) is used to generate the excitation pulse required for eddy current detection, specifying the pulse type, frequency, and amplitude. The amplitude of the pulse, i.e., the intensity of the pulse signal, is adjusted by the excitation pulse voltage adjustment module 3; the higher the voltage value, the stronger the pulse signal.

[0023] like Figure 3 As shown, the excitation pulse generation module (U_3) is model AD9833, a low-power, programmable waveform generator capable of producing sine, triangle, and square wave outputs. The output frequency and phase can be programmed via software. In the excitation pulse generation module (U_3), pin 1 is connected to the power supply via capacitor (C_7) for decoupling the DAC bias voltage; pin 2 is connected to the +3.3V power supply; pin 3 is connected to capacitors (C_8) and (C_9), with the other ends of both capacitors connected to ground; pin 4 is connected to ground; pin 5 is connected to pin 3 of the 25MHz crystal oscillator (X_m1); pins 6, 7, and 8 are connected to pins 16, 15, and 14 of the CPU1 (U0) control unit, respectively; pin 9 is connected to ground; and pin 10 is the pulse signal output, connected to pin 9 of the digital potentiometer (U_1) in the excitation pulse voltage adjustment module 3. The CPU1 (U0) sends data from pin 16 to pin 6 of the excitation pulse generation module (U_3) to set the pulse type and frequency.

[0024] like Figure 4 As shown, the excitation pulse voltage adjustment module 3 includes a digital potentiometer (U_1) of model ISL22316W and a CMOS operational amplifier (U_2) of model MCP601.

[0025] Specifically, pin 1 of the digital potentiometer (U_1) is connected to pin 4 of the CPU1 (U0); pin 2 is connected to pin 5 of the CPU1 (U0). Pins 3 and 4 are connected to ground; pin 5 is connected to pin 6 of the CPU1 (U0); pin 6 is also connected to ground; pin 7 is connected to analog ground; pin 8 is connected to pin 3 of the CMOS operational amplifier (U_2) via resistor (R_4); pin 9 is connected to pin 10 of the excitation pulse generator (U_3); and pin 10 is connected to the +5V power supply.

[0026] The CPU1 (U0) sends a digital signal of voltage to the digital potentiometer (U_1) via pin 5. The digital potentiometer (U_1) generates a voltage of 0-5V via pin 8, which is used to set the voltage value of the excitation pulse and realize the excitation pulse voltage adjustment.

[0027] The CMOS operational amplifier (U_2) is used to increase the output current load capacity. Pin 1 outputs a strong excitation pulse and is connected to pin 3 of the amplifier (U1A) in the dual high-speed operational amplifier in the defect amplitude signal demodulation module 5. Pin 2 is connected to analog ground. Pin 3 is connected to pin 8 of the digital potentiometer (U_1) via resistor (R_4). Pin 4 is connected to pin 1 via resistor (R_5). Pin 5 is connected to the +5V power supply.

[0028] The eddy current sensor 4 includes an excitation unit and a receiving unit. The excitation unit is connected to the sensor transmitting probe interface PA_T of the instrumentation amplifier, and the receiving unit is connected to the sensor receiving probe interface PA_R of the instrumentation amplifier. The probe of the eddy current sensor 4 does not directly contact the rail. The excitation unit converts the excitation pulse, regulated by the excitation pulse voltage adjustment module 3, into electromagnetic waves, which act on the rail surface. Eddy currents are excited near the rail surface, and these eddy currents also generate electromagnetic waves, which are received by the receiving unit and converted into electrical signals. When there are defects on the rail surface, the electromagnetic waves generated by the eddy currents will change. The received electromagnetic waves are further demodulated by the amplitude signal demodulation module 5 and the phase signal demodulation module 6, and the output is an analog signal that reflects the characteristic values ​​(amplitude and phase) of defects of different types and depths.

[0029] like Figure 5 As shown, the amplitude signal demodulation module 5 includes a 78M05 three-port voltage regulator (U5), a GS8092 dual-channel high-speed operational amplifier, and an AD620 (U2).

[0030] Among them, pin 1 of the 78M05 three-port voltage regulator (U5) is connected to the +12V power supply; pin 2 is grounded; pin 3 outputs a regulated +5V, which is connected to pin 8 of the GS8092 dual-channel high-speed operational amplifier (U1A).

[0031] The GS8092 dual-channel high-speed operational amplifier is used to increase the load capacity of the excitation pulse. Specifically, pin 1 of the amplifier (U1A) is the output terminal, connected to the sensor excitation interface PA_T; pin 2 is connected to pin 1 via resistor (R4); and pin 3 is connected to pin 1 of the CMOS operational amplifier (U_2).

[0032] The AD620 features high precision, low offset voltage, and low offset drift characteristics. It can differentially amplify the excitation and received signals of the eddy current sensor 4 to extract the amplitude waveform of the defect. A resistor (R9) is connected between pins 1 and 8; pin 2 is the input terminal of the inverting amplifier circuit, connected to the sensor transmitting probe interface PA_T via resistor (R1) and to the sensor receiving probe interface PA_R via resistor (R2); pin 3 is the input terminal of the forward amplifier circuit, connected to the sensor receiving probe interface PA_R; pin 4 is connected to the -5V power supply; pin 5 is grounded; pin 6 is the output terminal, outputting the amplitude value of the defect. Simultaneously, the output signal is connected to pin 5 of the amplifier (U3B) in the dual-channel current operational amplifier of the phase signal demodulation module 6 via resistors (R10) and (R13); pin 7 is connected to the +5V power supply.

[0033] like Figure 6As shown, the phase signal demodulation module 6 is a TL072IDT dual-channel current operational amplifier with characteristics such as high input impedance, high slew rate, low input bias, and wide common-mode. One channel connects to the excitation signal, and the other channel connects to the demodulated defect amplitude signal. The two amplified signals are connected to a monolithic integrated circuit (U4) for phase demodulation. In the dual-channel current operational amplifier, pins 1 and 2 of amplifier (U3A) are connected to pin 2 of the monolithic integrated circuit AD8302 via (C3); pin 3 is connected to pin 10 of excitation pulse generator 2 via resistor (R11); pin 4 is connected to -5V; pin 8 is connected to +5V; pin 5 of amplifier (U3B) is connected to pin 6 of AD620 via resistors (R13) and (R10), and pins 6 and 7 are connected to pin 6 of the monolithic integrated circuit via capacitor (C6).

[0034] The AD8302 monolithic integrated circuit is used for RF / IF amplitude and phase measurement. It mainly consists of two precisely matched broadband logarithmic detectors, a phase detector, an output amplifier group, a bias unit, and an output reference voltage buffer. It can simultaneously measure the amplitude ratio and phase difference between two input signals within a frequency range from low frequency to 2.7 GHz. Pins 1 and 7 of the AD8302 are grounded; pin 3 is grounded via capacitor (C4); pin 4 is connected to a +5V power supply via switch (L1); pin 5 is grounded via (C5); pin 8 is grounded via (C10); pins 9 and 10 are connected and then connected to a resistor (R17) to output the phase signal; pins 12 and 13 are connected and then connected to ground via resistor (R18); and pin 14 is grounded via capacitor (C9).

Claims

1. A rail eddy current inspection circuit, characterised in that: The control CPU (U0) is connected with the excitation pulse generating module (U_3), the excitation pulse generating module (U_3) is connected with the excitation pulse voltage adjusting module (3), the eddy current sensor (4) has an excitation unit and a receiving unit, wherein the excitation unit is connected with the excitation pulse voltage adjusting module (3), and the receiving unit is connected with the amplitude signal demodulation module (5) and the phase signal demodulation module (6). The control CPU (U0) is an STM32F103, and communication is established between the control CPU (U0) and a computer through a TCP / IP communication protocol; 2. A rail eddy current testing circuit as claimed in claim 1, characterised in that: The excitation pulse generating module (U_3) is an AD9833, the No. 1 pin is connected with a power supply through a first capacitor, the No. 2 pin is connected with a +3.3V power supply, the No. 3 pin is connected with a second capacitor and a third capacitor, the other ends of the second capacitor and the third capacitor are connected with the ground, the No. 4 pin is connected with the ground, the No. 5 pin is connected with the No. 3 pin of a 25M crystal oscillator (X_m1), the No. 6 pin, the No. 7 pin and the No. 8 pin are respectively connected with the No. 16 pin, the No. 15 pin and the No. 14 pin of the control CPU (U0), the No. 9 pin is connected with the ground, and the No. 10 pin is a pulse signal output and is connected with the No. 9 pin of a digital potentiometer (U_1) in the excitation pulse voltage adjusting module (3); The excitation pulse voltage adjusting module (3) comprises a digital potentiometer (U_1) with an ISL22316W type and a CMOS operational amplifier (U_2) with an MCP601 type; The No. 1 pin of the digital potentiometer (U_1) is connected with the No. 4 pin of the control CPU (U0), the No. 2 pin is connected with the No. 5 pin of the control CPU (U0), the No. 3 pin and the No. 4 pin are connected with the ground, the No. 5 pin is connected with the No. 6 pin of the control CPU (U0), the No. 6 pin is connected with the ground, the No. 7 pin is connected with an analog ground, the No. 8 pin is connected with the No. 3 pin of the CMOS operational amplifier (U_2) through a first resistor, the No. 9 pin is connected with the No. 10 pin of the excitation pulse generating module (U_3), and the No. 10 pin is connected with a +5V power supply; The No. 1 pin of the CMOS operational amplifier (U_2) outputs an excitation pulse and is connected with the No. 3 pin of an amplifier (U1A) in a double-path high-speed operational amplifier in the amplitude signal demodulation module (5), the No. 2 pin is connected with an analog ground, the No. 3 pin is connected with the No. 8 pin of the digital potentiometer (U_1) through a first resistor, the No. 4 pin is connected with the No. 1 pin through a second resistor, and the No. 5 pin is connected with a +5V power supply; The eddy current sensor (4) comprises the excitation unit and the receiving unit, the excitation unit is connected with a sensor transmission probe interface PA_T interface of an instrument amplifier, and the receiving unit is connected with a sensor receiving probe interface PA_R of the instrument amplifier; The amplitude signal demodulation module (5) comprises a 78M05 three-port voltage stabilizer (U5), a GS8092 double-path high-speed operational amplifier and an AD620 (U2). ​ Wherein, 78M05 three-port voltage regulator (U5) No. 1 pin +12V power supply; No. 2 pin ground; No. 3 pin output voltage +5V, connected to GS8092 dual high-speed operational amplifier (U1A) in the amplifier 8 pin; amplifier (U1A) No. 1 pin for the output terminal, connected to the eddy current sensor (4) in the instrument amplifier PA_T interface; No. 2 pin through the third resistor connected to No. 1 pin; No. 3 pin connected to the CMOS operational amplifier (U_2) No. 1 pin; AD620 (U2) between No. 1 pin and No. 8 pin connected to the fourth resistor; No. 2 pin for the reverse amplification circuit input, through the fifth resistor connected to PA_T interface, through the sixth resistor connected to the eddy current sensor (4) in the instrument amplifier PA_R interface; No. 3 pin for the forward amplification circuit input, connected to the eddy current sensor (4) in the instrument amplifier PA_R interface; No. 4 pin connected to the power supply -5V; No. 5 pin ground; No. 6 pin for the output terminal, output defect amplitude value, at the same time, the output signal through the seventh resistor and the eighth resistor, connected to the phase signal demodulation module (6) in the dual current operational amplifier (U3B) 5 pin; No. 7 pin connected to the power supply +5V; The phase signal demodulation module (6) is TL072IDT dual current operational amplifier; the first amplifier (U3A) connected to the excitation signal, the second amplifier (U3B) connected to the demodulated defect amplitude signal; the amplified two-way signal connected to the single-chip integrated circuit (U4) for phase demodulation; the first amplifier (U3A) in the dual current operational amplifier 1 pin and 2 pin connected through the fourth capacitor connected to the single-chip integrated circuit AD8302 2 pin; No. 3 pin through the ninth resistor connected to the excitation pulse generation module 10 pin; No. 4 pin connected to -5V; No. 8 pin connected to +5V; the fifth pin of the second amplifier (U3B) in the dual current operational amplifier is connected to the sixth pin of the AD620 through the eighth resistor and the seventh resistor, and the sixth pin and the seventh pin are connected through the fifth capacitor connected to the sixth pin of the single-chip integrated circuit (U4); The single-chip integrated circuit (U4) AD8302 1 pin and 7 pin ground; No. 3 pin through the sixth capacitor connected to the ground, No. 4 pin through the switch (L1) connected to the +5V power supply, No. 5 pin through the seventh capacitor connected to the ground, No. 8 pin through the eighth capacitor connected to the ground, No. 9 pin and No. 10 pin connected through the tenth resistor output phase signal, No. 12 pin and No. 13 pin connected through the eleventh resistor connected to the ground, No. 14 pin through the ninth capacitor connected to the ground.

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