Bonding structure, ultrasonic fingerprint identification module and electronic equipment

Abstract

The utility model provides a bonding structure, ultrasonic fingerprint identification module and electronic equipment, and relates to the integrated circuit technology field, the bonding structure comprises a substrate layer, a passivation layer and a flexible circuit board, the substrate layer comprises a device layer, a first interconnection layer and a multi-layer stacking structure, the multi-layer stacking structure is arranged between the device layer and the first interconnection layer and is used for transmitting electric signals and / or buffering stress; the passivation layer is arranged on the substrate layer and covers the first interconnection layer, and a window structure is arranged on the passivation layer; the flexible circuit board is provided with a second interconnection layer, and the second interconnection layer is electrically connected with the first interconnection layer. According to the utility model, the bonding area can be limited in the window structure, the edge stress sensitive area of the first interconnection layer is avoided, the transmission path of the bonding pressure is optimized, and the multi-layer stacking structure is subjected to buffer design, so that the multi-layer stacking structure can absorb or disperse the bonding pressure, the stability of an electric signal path is further guaranteed, and the bonding effect is improved. And the problem of failure is prevented.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a bonding structure, an ultrasonic fingerprint recognition module, and an electronic device. Background Technology

[0002] Ultrasonic fingerprint recognition technology utilizes the ability of ultrasound to penetrate materials and generate echoes of varying magnitudes depending on the material to identify fingerprints. Because ultrasound has a certain degree of penetrability, it can pass through glass, aluminum, stainless steel, sapphire, and other materials for identification, making ultrasonic fingerprint recognition technology increasingly popular. Currently, many electronic devices are equipped with fingerprint recognition modules. As electronic devices gradually move towards full-screen designs, the fingerprint recognition module needs to be integrated into the screen, thus placing increasingly higher demands on its structural design.

[0003] However, in achieving ultra-thin bodies and extreme screen-to-body ratios, the physical space for fingerprint recognition modules is drastically compressed. Traditional connection methods such as soldering or wire bonding suffer from volume limitations and insufficient flexibility. Furthermore, during the bonding process between the flexible circuit board and the aluminum pad on the ultrasonic sensor chip, the bonding pressure acts directly on the delicate multilayer stacked structure beneath the aluminum pad. This multilayer stacked structure bears the core functions of signal processing and sensing. It typically consists of metal interconnect layers and brittle intermetallic dielectric layers, with vias on the intermetallic dielectric layer for signal transmission. When excessive or uneven bonding pressure is transmitted through the aluminum pad to the multilayer stacked structure, it can easily cause the brittle intermetallic dielectric layer to crack, leading to the failure of the metal interconnect layer and disrupting the electrical signal path within the multilayer stacked structure, ultimately causing the ultrasonic sensor chip to fail. Therefore, how to prevent bonding pressure from damaging the electrical signal path and causing chip failure has become a pressing technical problem to be solved. Utility Model Content

[0004] In order to overcome the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is to provide a bonding structure, an ultrasonic fingerprint recognition module and an electronic device to prevent bonding pressure from damaging the electrical signal path and causing chip failure.

[0005] The above-mentioned objective of this utility model can be achieved by the following technical solution: this utility model provides a bonding structure, including:

[0006] The substrate layer includes a device layer, a first interconnect layer, and a multilayer stacked structure, wherein the multilayer stacked structure is disposed between the device layer and the first interconnect layer for the purpose of electrical signal transmission and / or stress buffering.

[0007] A passivation layer is disposed on the substrate layer and covers the first interconnect layer, and a window structure is provided on the passivation layer.

[0008] In a preferred embodiment of the present invention, the bonding structure is used for bonding with a flexible circuit board, the flexible circuit board having a second interconnect layer, the second interconnect layer being electrically connected to the first interconnect layer.

[0009] In a preferred embodiment of the present invention, the first interconnect layer includes a metal pad disposed on the substrate layer.

[0010] In a preferred embodiment of this utility model, the metal pad is an aluminum pad.

[0011] In a preferred embodiment of this invention, the area of ​​the first interconnect layer is 8000 μm. 2 Up to 50000μm 2 .

[0012] In a preferred embodiment of the present invention, the window structure is constructed as a rectangle, the width of the window structure is ≥0.04mm, and the length of the window structure is ≥0.2mm.

[0013] In a preferred embodiment of the present invention, the second interconnect layer includes an ACF layer disposed on the flexible circuit board.

[0014] In a preferred embodiment of the present invention, the multilayer stacked structure includes a first metal interconnect layer electrically connected to the first interconnect layer, and a first intermetallic dielectric layer disposed between the first metal interconnect layer and the device layer. The first intermetallic dielectric layer is provided with a first interlayer via group, which is disposed outside the projection of the window structure along the thickness direction of the substrate layer.

[0015] In a preferred embodiment of the present invention, the thickness of the first interconnect layer is ≥11KA.

[0016] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a second metal interconnect layer stacked with the first metal-interconnect dielectric layer, and a second metal-interconnect dielectric layer disposed between the second metal interconnect layer and the device layer, wherein the second metal-interconnect dielectric layer is provided with a second interlayer via group.

[0017] In a preferred embodiment of the present invention, the second interlayer via group is disposed on the outer side of the projection of the window structure along the thickness direction of the substrate layer.

[0018] In a preferred embodiment of the present invention, the second metal interconnect layer is provided with a first hollow structure, and the first intermetallic dielectric layer and the second intermetallic dielectric layer located on both sides of the second metal interconnect layer can be connected through the first hollow structure.

[0019] In a preferred embodiment of the present invention, the first hollow structure includes a plurality of first connecting holes penetrating the second metal interconnect layer, and the first intermetallic dielectric layer and the second intermetallic dielectric layer located on both sides of the first connecting holes are connected through the first connecting holes, and the total area of ​​the plurality of first connecting holes is not less than half of the total area of ​​the second metal interconnect layer.

[0020] Alternatively, the first hollow structure divides the second metal interconnect layer into multiple spaced first metal strips, with a first connecting gap formed between adjacent first metal strips. The first intermetallic dielectric layer and the second intermetallic dielectric layer located on both sides of the second metal interconnect layer are connected through the first connecting gap, and the total area of ​​the multiple first connecting gaps is not less than half of the total area of ​​the second metal interconnect layer.

[0021] In a preferred embodiment of the present invention, the projected shape of the first connecting hole along the thickness direction of the substrate layer is a regular polygon.

[0022] In a preferred embodiment of the present invention, the window structure is rectangular, and the spacing between adjacent first connecting holes is less than 1 / 10 of the width of the window structure; and / or, the maximum diameter of the first connecting hole is greater than the spacing between adjacent first connecting holes.

[0023] In a preferred embodiment of the present invention, the plurality of first connecting holes are arranged in a rectangular array; or, the plurality of first connecting holes are arranged in an alternating array.

[0024] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a third metal interconnect layer and a third metal inter-dielectric layer disposed between the second inter-metal dielectric layer and the device layer and stacked alternately. The third metal interconnect layer is connected to the second inter-metal dielectric layer. Each of the third inter-metal dielectric layers is provided with a third inter-layer via group. The third inter-layer via group closest to the device layer is electrically connected to the device layer.

[0025] In a preferred embodiment of the present invention, the third metal interconnect layer is provided with a second hollow structure, and the second intermetallic dielectric layer and the third intermetallic dielectric layer located on both sides of the third metal interconnect layer can be connected through the second hollow structure; the second hollow structure includes a plurality of second connecting holes penetrating the third metal interconnect layer, and the second connecting holes are used to connect adjacent intermetallic dielectric layers.

[0026] In a preferred embodiment of the present invention, the multilayer stacked structure includes a first metal reinforcement layer electrically connected to the first interconnect layer, a fourth metal interconnect layer electrically connected to the first metal reinforcement layer, and a fourth inter-metal dielectric layer disposed between the fourth metal interconnect layer and the device layer, wherein a fourth inter-layer via group is provided on the fourth inter-metal dielectric layer.

[0027] In a preferred embodiment of this invention, the thickness of the first interconnect layer is ≥6KA.

[0028] In a preferred embodiment of the present invention, the material of the first metal reinforcement layer is tungsten.

[0029] In a preferred embodiment of the present invention, the thickness of the first metal reinforcement layer is not less than 200 nm.

[0030] In a preferred embodiment of the present invention, along the thickness direction of the substrate layer, the projection of the first interconnect layer is located within the first metal reinforcement layer, and the minimum interval between the side of the first metal reinforcement layer and the side of the first interconnect layer is not less than 200 nm.

[0031] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a first dielectric layer surrounding the outside of the first metal reinforcement layer and disposed between the passivation layer and the fourth metal interconnect layer.

[0032] In a preferred embodiment of the present invention, along the thickness direction of the substrate layer, the projection of the first metal reinforcement layer is located within the fourth metal interconnect layer, and the minimum interval between the side of the fourth metal interconnect layer and the side of the first metal reinforcement layer is not less than 500 nm.

[0033] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a fifth metal interconnect layer stacked with the fourth metal-intermetal dielectric layer, and a fifth metal-intermetal dielectric layer disposed between the fifth metal interconnect layer and the device layer, wherein the fifth metal-intermetal dielectric layer is provided with a fifth interlayer via group.

[0034] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a sixth metal interconnect layer and a sixth metal inter-dielectric layer disposed between the fifth metal inter-dielectric layer and the device layer and stacked alternately. The sixth metal interconnect layer is connected to the fifth metal inter-dielectric layer. A sixth inter-layer via group is provided on the sixth metal inter-dielectric layer. The sixth inter-layer via group closest to the device layer is electrically connected to the device layer.

[0035] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a second metal reinforcement layer, which is disposed between the first metal reinforcement layer and the fourth metal interconnect layer. Along the thickness direction of the substrate layer, the projection of the second metal reinforcement layer is located within the first metal reinforcement layer.

[0036] In a preferred embodiment of the present invention, the multilayer stacked structure further includes a second dielectric layer surrounding the outside of the second metal reinforcement layer and disposed between the first dielectric layer and the fourth metal interconnect layer.

[0037] In a preferred embodiment of this invention, the material of the second metal reinforcement layer is tungsten.

[0038] In a preferred embodiment of the present invention, along the thickness direction of the substrate layer, the projection of the second metal reinforcement layer is located within the window structure, and the projected area of ​​the second metal reinforcement layer is not less than 80% of the area of ​​the window structure.

[0039] In a preferred embodiment of the present invention, along the thickness direction of the substrate layer, the projection of the second metal reinforcement layer is located within the fourth metal interconnect layer, and the minimum interval between the side of the second metal reinforcement layer and the side of the fourth metal interconnect layer is not less than 500 nm.

[0040] In a preferred embodiment of the present invention, the fifth metal interconnect layer is provided with a third hollow structure, and the fourth intermetallic dielectric layer and the fifth intermetallic dielectric layer located on both sides of the fifth metal interconnect layer can be connected through the third hollow structure.

[0041] In a preferred embodiment of the present invention, the sixth metal interconnect layer is provided with a fourth hollow structure, and the fifth intermetallic dielectric layer and the sixth intermetallic dielectric layer located on both sides of the sixth metal interconnect layer can be connected through the fourth hollow structure; the fourth hollow structure includes a plurality of fourth connecting holes penetrating the sixth metal interconnect layer, and the fourth connecting holes are used to connect adjacent intermetallic dielectric layers.

[0042] This utility model also provides an ultrasonic fingerprint recognition module, including the aforementioned bonding structure.

[0043] In a preferred embodiment of this utility model, the ultrasonic fingerprint recognition module is a PVDF silicon-based ultrasonic fingerprint recognition module.

[0044] This invention also provides an electronic device, including the aforementioned ultrasonic fingerprint recognition module.

[0045] The technical solution of this utility model has the following significant beneficial effects:

[0046] The bonding structure of this invention exposes a portion of the first interconnect layer through a window structure on the passivation layer to form a bump region. The flexible circuit board can then bond with the first interconnect layer located in the bump region through a second interconnect layer, thereby forming a stable and efficient electrical connection. Furthermore, by covering the edge of the first interconnect layer with the passivation layer, the bonding region is confined within the window structure, avoiding the stress-sensitive area at the edge of the first interconnect layer. This prevents cracks at the edge of the first interconnect layer and allows the bonding pressure to be uniformly conducted through the center of the first interconnect layer to the multilayer stacked structure, optimizing the bonding pressure transmission path, avoiding localized stress concentration, and reducing the risk of damage to the first interconnect layer and the multilayer stacked structure caused by the bonding pressure. Moreover, the multilayer stacked structure can function as an electrical signal transmission point between the first interconnect layer and the device layer. Through a buffer design, the multilayer stacked structure can absorb or disperse the bonding pressure, further ensuring the stability of the electrical signal path and preventing substrate failure. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely illustrative to aid in understanding the invention and do not specifically limit the shapes and proportions of the components. Those skilled in the art, under the guidance of this invention, can select various possible shapes and proportions to implement this invention according to specific circumstances.

[0049] Figure 1 This is a side sectional view of one embodiment of the bonding structure described in this utility model;

[0050] Figure 2 This is a side sectional view of one embodiment of the multilayer stacked structure described in this utility model;

[0051] Figure 3 This is a side sectional view of another embodiment of the multilayer stacked structure described in this utility model;

[0052] Figure 4 This is a side sectional view of another embodiment of the multilayer stacked structure described in this utility model;

[0053] Figure 5 This is a three-dimensional structural diagram of one embodiment of the metal interconnect layer described in this utility model;

[0054] Figure 6 This is a three-dimensional structural diagram of another embodiment of the metal interconnect layer described in this utility model;

[0055] Figure 7 This is a three-dimensional structural diagram of another embodiment of the metal interconnect layer described in this utility model;

[0056] Figure 8 This is a schematic diagram of a rectangular array arrangement of the first connecting hole according to the present invention;

[0057] Figure 9 This is a schematic diagram of a structure of the present invention with the first connecting holes arranged in an alternating array.

[0058] Figure 10 This is a schematic diagram of a structure in which the first metal strips of this utility model are arranged at horizontal intervals.

[0059] Figure 11 This is a schematic diagram of a structure in which the first metal strips of this utility model are arranged longitudinally at intervals;

[0060] Figure 12 This is a schematic diagram of a structure in which the first metal strips of this utility model are arranged at inclined intervals;

[0061] Figure 13 This is a side sectional view of another embodiment of the bonding structure described in this utility model;

[0062] Figure 14 This is a side sectional view of one embodiment of the first metal reinforcement layer of this utility model;

[0063] Figure 15 This is a side sectional view of one embodiment of the second metal reinforcement layer of this utility model;

[0064] Figure 16 This is a top view schematic diagram of one embodiment of the window structure described in this utility model;

[0065] Figure 17This is a top view of another embodiment of the window structure described in this utility model.

[0066] The reference numerals in the above figures are as follows:

[0067] 100, Substrate layer; 110, Device layer; 120, First interconnect layer; 121, Metal pad;

[0068] 200. Multi-layer stacked structure;

[0069] 211. First metal interconnect layer; 212. First inter-metal dielectric layer; 213. First inter-layer via group;

[0070] 214. Second metal interconnect layer; 2141. First metal strip; 215. Second inter-metal dielectric layer; 216. Second inter-layer via group;

[0071] 217. Third metal interconnect layer; 218. Third inter-metal dielectric layer; 219. Third inter-layer via group;

[0072] 220. First hollow structure; 221. First connecting hole; 222. First connecting gap;

[0073] 230. First metal reinforcement layer;

[0074] 241. Fourth metal interconnect layer; 242. Fourth inter-metal dielectric layer; 243. Fourth inter-layer via group;

[0075] 244. Fifth metal interconnect layer; 245. Fifth inter-metal dielectric layer; 246. Fifth inter-layer via group;

[0076] 247. Sixth metal interconnect layer; 248. Sixth inter-metal dielectric layer; 249. Sixth inter-layer via group;

[0077] 250. First dielectric layer

[0078] 260. Second metal reinforcement layer;

[0079] 270. Second dielectric layer;

[0080] 300. Passivation layer; 310. Window structure;

[0081] 400, Flexible circuit board; 410, Second interconnect layer. Detailed Implementation

[0082] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0083] Implementation Method 1

[0084] Please refer to the following: Figures 1 to 17 As shown, an embodiment of this utility model provides a bonding structure, which includes a substrate layer 100, a passivation layer 300, and a flexible circuit board 400. The substrate layer 100 includes a device layer 110, a first interconnect layer 120, and a multilayer stacked structure 200. The multilayer stacked structure 200 is disposed between the device layer 110 and the first interconnect layer 120 for electrical signal transmission and / or stress buffering. The passivation layer 300 is disposed on the substrate layer 100 and covers the first interconnect layer 120. The passivation layer 300 is provided with a window structure 310.

[0085] Overall, the bonding structure exposes a portion of the first interconnect layer 120 through the window structure 310 on the passivation layer 300 to form a bump region. The flexible circuit board 400 can be bonded to the first interconnect layer 120 located in the bump region through the second interconnect layer 410, thereby forming a stable and efficient electrical connection.

[0086] Furthermore, by covering the edge of the first interconnect layer 120 with the passivation layer 300, the bonding area is confined within the window structure 310, avoiding the stress-sensitive area at the edge of the first interconnect layer 120. This prevents cracks from appearing at the edge of the first interconnect layer 120 and allows the bonding pressure to be uniformly transmitted to the multilayer stacked structure 200 through the middle of the first interconnect layer 120. This optimizes the transmission path of the bonding pressure, avoids local stress concentration, and reduces the risk of damage to the first interconnect layer 120 and the multilayer stacked structure 200 caused by the bonding pressure.

[0087] Furthermore, the multilayer stacked structure 200 can play a role in electrical signal transmission between the first interconnect layer 120 and the device layer 110. By implementing a buffer design for the multilayer stacked structure 200, the multilayer stacked structure 200 can absorb or disperse bonding pressure, further ensuring the stability of the electrical signal path and preventing the substrate layer 100 from failing.

[0088] In the embodiments of this utility model, the designer can adjust the specific material of the substrate 100 according to the needs of use, and no specific limitations are made here. For example, the substrate 100 includes, but is not limited to, silicon-based, glass-based, etc., and the functional layers on the substrate 100 include, but are not limited to, piezoelectric materials such as PVDF, AlN, and PZT.

[0089] In an embodiment of this utility model, the bonding structure is used to bond with a flexible circuit board 400, on which a second interconnect layer 410 is provided, and the second interconnect layer 410 is electrically connected to the first interconnect layer 120.

[0090] Specifically, such as Figure 1 and Figure 2 In the embodiment shown, the first interconnect layer 120, the passivation layer 300 and the second interconnect layer 410 are stacked together and can be placed in the gap between the flexible circuit board 400 and the substrate layer 100, which has better integration and helps to reduce the required installation space.

[0091] The bonding structure described in this invention can better meet the bonding requirements between the flexible circuit board 400 and the substrate layer 100. This bonding structure can better cope with bonding pressure to ensure electrical performance, while also taking into account the stability of the mechanical connection. Especially in full-screen devices or embedded applications, it plays an important role in improving assembly efficiency, reducing manufacturing costs, and improving product yield.

[0092] In the embodiments of this utility model, such as Figure 1 , Figure 2 and Figure 16 In the illustrated embodiment, the first interconnect layer 120 includes a metal pad 121 disposed on the substrate layer 100. The metal pad 121 possesses excellent conductivity and thermal stability, thereby providing a reliable connection foundation for the second interconnect layer 410 and enhancing the overall electrical performance and mechanical strength of the bonding structure.

[0093] Designers can adjust the number and material of the metal pads 121 according to usage needs, and no specific restrictions are imposed here. Preferably, the metal pads 121 are aluminum pads.

[0094] Designers can adjust the number and arrangement of aluminum pads according to usage needs, and no specific restrictions are imposed here. In one feasible embodiment, one aluminum pad is provided. In another feasible embodiment, multiple aluminum pads are provided, and the multiple aluminum pads are arranged in the same layer with intervals.

[0095] Among them, the aluminum pad has excellent conductivity and processability, and the aluminum pad has good compatibility with the substrate layer 100, which can effectively reduce contact resistance and improve signal transmission efficiency.

[0096] In embodiments of this invention, designers can adjust the area of ​​the first interconnect layer 120 according to usage requirements, and no specific limitations are imposed here. In one feasible embodiment, the area of ​​the first interconnect layer 120 is 8000 μm. 2 Up to 50000μm 2 .

[0097] By controlling the area of ​​the first interconnect layer 120 within the range of 8000μm² to 50000μm², it helps to optimize the overall spatial layout and integration density of the bonding structure while ensuring sufficient current conduction capability.

[0098] In embodiments of this utility model, designers can adjust the specific shape and size of the window structure 310 according to usage needs, and no specific limitations are imposed here. In one feasible embodiment, such as Figure 16 and Figure 17 In the embodiment shown, the window structure 310 is constructed as a rectangle, with a width ≥ 0.04 mm and a length ≥ 0.2 mm.

[0099] In the embodiments of this utility model, such as Figure 1 In the illustrated embodiment, the second interconnect layer 410 includes an ACF layer disposed on the flexible circuit board 400. Specifically, the ACF layer is composed of anisotropic conductive material, effectively realizing the dual functions of signal transmission and electrical isolation. Furthermore, the ACF layer also has excellent adhesive properties, which helps to improve the stability of the electrical connection.

[0100] In the prior art, the material of the first intermetallic dielectric layer 212 is generally silicon dioxide or other low dielectric constant materials, which are relatively brittle. When excessive bonding pressure is applied to the first intermetallic dielectric layer 212, it may cause cracks in the first intermetallic dielectric layer 212. These cracks can easily extend downward along the first interlayer via group 213, thereby damaging the lower metal interconnect layers and causing interlayer connection failure.

[0101] To solve the above-mentioned technical problems, in the first embodiment of this utility model, as follows: Figure 2 , Figure 3 and Figure 4 In the embodiment shown, the multilayer stacked structure 200 includes a first metal interconnect layer 211 electrically connected to the first interconnect layer 120, and a first intermetallic dielectric layer 212 disposed between the first metal interconnect layer 211 and the device layer 110. The first intermetallic dielectric layer 212 is provided with a first interlayer via group 213, which is disposed on the outside of the projection of the window structure 310 along the thickness direction of the substrate layer 100.

[0102] The first metal interconnect layer 211 can be used for rewiring layer design, and the first inter-metal dielectric layer 212 can play an electrical insulation role to avoid short circuits between adjacent metal interconnect layers.

[0103] By setting the first interlayer via group 213 outside the projection area of ​​the window structure 310, the first interlayer via group 213 can achieve efficient transmission of electrical signals while avoiding direct impact from bonding pressure, thereby reducing the risk of cracking in the first intermetallic dielectric layer 212 and ensuring the stability of the interlayer connection.

[0104] Designers can adjust the specific structure of the first interlayer via group 213 according to usage needs, and no specific restrictions are imposed here. Specifically, the first interlayer via group 213 includes multiple first interlayer vias arranged at intervals.

[0105] In the first embodiment of this utility model, the designer can adjust the specific thickness of the first interconnect layer 120 according to the usage requirements, and no specific limitation is made here. Preferably, the thickness of the first interconnect layer 120 is ≥11KA.

[0106] By making the thickness of the first interconnect layer 120 ≥ 11KA, the mechanical strength and compressive strength of the first interconnect layer 120 are further enhanced while ensuring current conduction capability, enabling it to withstand the pressure applied during the bonding process more effectively, thereby improving the overall stability and long-term reliability of the bonding structure.

[0107] In the first embodiment of this utility model, as Figure 2 , Figure 3 and Figure 4 In the embodiment shown, the multilayer stacked structure 200 further includes a second metal interconnect layer 214 stacked with the first metal-interconnect dielectric layer 212, and a second metal-interconnect dielectric layer 215 disposed between the second metal interconnect layer 214 and the device layer 110, wherein a second interlayer via group 216 is provided on the second metal-interconnect dielectric layer 215.

[0108] The second metal interconnect layer 214 can be designed for redistribution, so that the first interconnect layer 120 can be electrically connected to the device layer 110 through the first metal interconnect layer 211 and the second metal interconnect layer 214. The second intermetallic dielectric layer 215 can play an electrical insulation role, avoiding short circuits between adjacent metal interconnect layers.

[0109] Designers can adjust the specific structure of the second-layer via group 216 according to usage requirements, and no specific restrictions are imposed here. Specifically, the second-layer via group 216 includes multiple second-layer vias arranged at intervals.

[0110] In one feasible embodiment, since a second metal interconnect layer 214, a first metal interconnect layer 212, and a first metal interconnect layer 211 are disposed between the second intermetallic dielectric layer 215 and the first interconnect layer 120, bonding stress can be prevented from directly acting on the second intermetallic dielectric layer 215, thereby providing a certain buffering effect on the second interlayer via group 216. Therefore, as Figure 2 In the embodiment shown, the second interlayer via group 216 can be disposed within the projection range of the window structure 310 along the thickness direction of the substrate layer 100.

[0111] In another feasible embodiment, such as Figure 3 and Figure 4 In the illustrated embodiment, the second interlayer via group 216 is disposed on the outer side of the projection of the window structure 310 along the thickness direction of the substrate layer 100. That is, both the first interlayer via group 213 and the second interlayer via group 216 are disposed on the outer side of the projection of the window structure 310, which avoids the first interlayer via group 213 and the second interlayer via group 216 being directly subjected to bonding pressure in the thickness direction, thereby reducing the risk of breakage of the first intermetallic dielectric layer 212 and the second intermetallic dielectric layer 215.

[0112] In the first embodiment of this utility model, as Figure 4 , Figure 6 and Figure 7 In the embodiment shown, a first cutout structure 220 is provided on the second metal interconnect layer 214, and the first intermetallic dielectric layer 212 and the second intermetallic dielectric layer 215 located on both sides of the second metal interconnect layer 214 can be connected through the first cutout structure 220.

[0113] The first intermetallic dielectric layer 212 and the second intermetallic dielectric layer 215 located on both sides of the second metal interconnect layer 214 can be connected through the first hollow structure 220 to form a three-dimensional structure, which enhances the bonding force between adjacent intermetallic dielectric layers. Furthermore, the bonding pressure can be transmitted and dispersed between adjacent intermetallic dielectric layers through the first connecting hole 221, reducing the risk of the intermetallic dielectric layer breaking.

[0114] In one specific embodiment, such as Figure 6 In the embodiment shown, the first hollow structure 220 includes a plurality of first connecting holes 221 penetrating the second metal interconnect layer 214, and the first intermetallic dielectric layer 212 and the second intermetallic dielectric layer 215 located on both sides of the first connecting holes 221 are connected through the first connecting holes 221.

[0115] By providing multiple first connecting holes 221 on the second metal interconnect layer 214 to form a first hollow structure 220, the stiffness of the second metal interconnect layer 214 is reduced, which helps to reduce or eliminate the bonding stress acting on the second metal interconnect layer 214, avoid stress concentration, and thus reduce the risk of breakage.

[0116] Furthermore, the total area of ​​the plurality of first connecting holes 221 is not less than half the total area of ​​the second metal interconnect layer 214. By ensuring that the total area of ​​the first connecting holes 221 is not less than half the total area of ​​the second metal interconnect layer 214, the metal ratio is reduced, the elastic deformation capability of the second metal interconnect layer 214 is significantly improved, and the risk of the second metal interconnect layer 214 breaking under bonding pressure is reduced.

[0117] Designers can adjust the specific ratio of the total area of ​​the first connecting hole 221 to the total area of ​​the second metal interconnect layer 214 according to the needs of use, and no specific restrictions are imposed here.

[0118] In the embodiments of this utility model, such as Figure 8 and Figure 9 In the embodiment shown, the projected shape of the first connecting hole 221 along the thickness direction of the substrate layer 100 is a regular polygon.

[0119] In one specific embodiment, such as Figure 8 In the embodiment shown, the projected shape of the first connecting hole 221 is a regular hexagon. In another specific embodiment, the projected shape of the first connecting hole 221 is a regular octagon.

[0120] In the first embodiment of this utility model, as Figure 4 and Figure 16 In the embodiment shown, the window structure 310 is rectangular, and the spacing L1 between adjacent first connecting holes 221 is less than 1 / 10 of the width of the window structure 310; and / or, the maximum aperture L2 of the first connecting hole 221 is greater than the spacing L1 between adjacent first connecting holes 221.

[0121] Preferably, the spacing L1 between adjacent first connecting holes 221 is less than 1 / 10 of the width of the window structure 310; the maximum aperture L2 of the first connecting hole 221 is greater than the spacing L1 between adjacent first connecting holes 221.

[0122] By controlling the spacing L1 between adjacent first connecting holes 221 and the aperture L2 of the first connecting holes 221, the first connecting holes 221 can be more evenly distributed on the second metal interconnect layer 214, thereby improving the overall structural stability of the second metal interconnect layer 214.

[0123] Designers can adjust the specific number and arrangement of the first connecting holes 221 according to usage needs, and no specific limitations are imposed here. In one feasible embodiment, such as Figure 8 In the illustrated embodiment, the plurality of first connecting holes 221 are arranged in a rectangular array. In another feasible embodiment, such as Figure 9 In the embodiment shown, a plurality of first connecting holes 221 are arranged in an alternating array.

[0124] In another specific embodiment, such as Figure 7 In the embodiment shown, the first hollow structure 220 divides the second metal interconnect layer 214 into a plurality of spaced first metal strips 2141, and a first connecting gap 222 is formed between adjacent first metal strips 2141. The first intermetallic dielectric layer 212 and the second intermetallic dielectric layer 215 located on both sides of the second metal interconnect layer 214 are connected through the first connecting gap 222, and the total area of ​​the plurality of first connecting gaps 222 is not less than half of the total area of ​​the second metal interconnect layer 214.

[0125] By setting multiple first connecting gaps 222 on the second metal interconnect layer 214 to form a first hollow structure 220, the stiffness of the second metal interconnect layer 214 is reduced, which helps to reduce or eliminate the bonding stress acting on the second metal interconnect layer 214, avoid stress concentration, and thus reduce the risk of breakage.

[0126] Designers can adjust the number and arrangement of the first metal strips 2141 according to usage needs, and no specific limitations are imposed here. In one specific embodiment, such as Figure 10 In one embodiment, a plurality of first metal strips 2141 are arranged laterally at intervals.

[0127] In another specific embodiment, such as Figure 11 In one embodiment, a plurality of first metal strips 2141 are arranged longitudinally at intervals.

[0128] In yet another specific embodiment, such as Figure 12 In one embodiment, a plurality of first metal strips 2141 are arranged at an angle and spaced apart.

[0129] Furthermore, the total area of ​​the plurality of first connecting gaps 222 is not less than half the total area of ​​the second metal interconnect layer 214. By ensuring that the total area of ​​the first connecting gaps 222 is not less than half the total area of ​​the second metal interconnect layer 214, the metal ratio is reduced, the elastic deformation capability of the second metal interconnect layer 214 is significantly improved, and the risk of the second metal interconnect layer 214 breaking under bonding pressure is reduced.

[0130] Designers can adjust the specific ratio of the total area of ​​the first connecting gap 222 to the total area of ​​the second metal interconnect layer 214 according to the needs of use, without making specific restrictions here.

[0131] In the first embodiment of this utility model, as Figure 2 , Figure 3 and Figure 4 In the embodiment shown, the multilayer stacked structure 200 further includes a third metal interconnect layer 217 and a third metal interconnect layer 218 disposed between the second metal inter-dielectric layer 215 and the device layer 110 and stacked alternately. The third metal interconnect layer 217 is connected to the second metal inter-dielectric layer 215. Each third metal inter-dielectric layer 218 is provided with a third inter-layer via group 219. The third inter-layer via group 219 closest to the device layer 110 is electrically connected to the device layer 110.

[0132] By setting multiple metal interconnect layers, different metal interconnect layers can be used to achieve different functions. For example, the first metal interconnect layer 211 serves as the top layer and plays the role of pressure buffering and interface adaptation, the second metal interconnect layer 214 serves as the middle layer and plays the role of relay processing, and the third metal interconnect layer 217 serves as the bottom layer and plays the role of signal transmission and ultimate support.

[0133] Of course, in other feasible embodiments, designers may adjust the specific number of metal layers and inter-metal dielectric layers in the multilayer stacked structure 200 according to the needs of use, and no specific restrictions are imposed here.

[0134] In the first embodiment of this utility model, a second hollow structure is provided on the third metal interconnect layer 217, and the second intermetallic dielectric layer 215 and the third intermetallic dielectric layer 218 located on both sides of the third metal interconnect layer 217 can be connected through the second hollow structure.

[0135] The second perforated structure can reduce the stiffness of the third metal interconnect layer 217, which helps to reduce or eliminate stress on the third metal interconnect layer 217, avoid stress concentration, and thus reduce the risk of breakage.

[0136] Furthermore, the second intermetallic dielectric layer 215 and the third intermetallic dielectric layer 218 located on both sides of the third metal interconnect layer 217 can be connected through the second hollow structure to form a three-dimensional structure, which enhances the bonding force of adjacent intermetallic dielectric layers and reduces the risk of intermetallic dielectric layer breakage.

[0137] Designers can adjust the specific configuration of the second hollow structure according to usage needs, and no specific restrictions are imposed here. Preferably, the configuration of the second hollow structure is the same as or similar to that of the first hollow structure 220.

[0138] In the second embodiment of this utility model, as Figure 13 , Figure 14 and Figure 17The embodiment shown includes a multilayer stacked structure 200 comprising a first metal reinforcement layer 230 electrically connected to the first interconnect layer 120, a fourth metal interconnect layer 241 electrically connected to the first metal reinforcement layer 230, and a fourth intermetallic dielectric layer 242 disposed between the fourth metal interconnect layer 241 and the device layer 110, wherein a fourth interlayer via group 243 is provided on the fourth intermetallic dielectric layer 242.

[0139] The first metal reinforcement layer 230 has greater hardness. When bonding pressure is applied to the first interconnect layer 120 and transmitted downward to the first metal reinforcement layer 230, the first metal reinforcement layer 230 absorbs and blocks the bonding pressure, preventing the bonding pressure from damaging the fourth metal interconnect layer 241 and the fourth intermetallic dielectric layer 242, thereby ensuring the stability of the electrical signal path and preventing the substrate layer 100 from failing due to pressure.

[0140] Since the first metal reinforcement layer 230 provides protection, in this embodiment of the invention, the thickness of the first interconnect layer 120 is ≥6KA. By ensuring that the thickness of the first interconnect layer 120 is ≥6KA, the overall stability and long-term reliability of the bonding structure are improved while maintaining its current conduction capability.

[0141] Designers can adjust the specific material of the first metal reinforcement layer 230 according to the application requirements, and no specific restrictions are imposed here. Preferably, the material of the first metal reinforcement layer 230 is tungsten.

[0142] Tungsten has high hardness and excellent compressive strength, which can effectively absorb and disperse the mechanical stress generated during the bonding process, preventing the stress from being transmitted downward to the metal interconnect layer and the intermetallic dielectric layer, thereby avoiding structural failure problems such as cracking of the intermetallic dielectric layer or deformation of the metal layer.

[0143] More preferably, the thickness of the first metal reinforcement layer 230 is not less than 200 nm. When the thickness of the first metal reinforcement layer 230 is not less than 200 nm, its mechanical support capacity and stress buffering effect are further enhanced, significantly improving the durability and reliability of the bonding structure.

[0144] In the second embodiment of this utility model, along the thickness direction of the substrate layer 100, the projection of the first interconnect layer 120 is located within the first metal reinforcement layer 230, and the minimum spacing between the side of the first metal reinforcement layer 230 and the side of the first interconnect layer 120 is not less than 200nm.

[0145] By ensuring that the minimum spacing between the side of the first metal reinforcement layer 230 and the side of the first interconnect layer 120 is not less than 200 nm, the first metal reinforcement layer 230 effectively supports the first interconnect layer 120, optimizes the interlayer stress distribution, and reduces the phenomenon of interface stress concentration.

[0146] In the second embodiment of this utility model, as Figure 14 In the illustrated embodiment, the multilayer stacked structure 200 further includes a first dielectric layer 250 surrounding the outside of the first metal reinforcement layer 230 and positioned between the passivation layer 300 and the fourth metal interconnect layer 241. By providing the first dielectric layer 250 around the first metal reinforcement layer 230, the first metal reinforcement layer 230 can be provided with insulation and physical protection.

[0147] In the second embodiment of this utility model, along the thickness direction of the substrate layer 100, the projection of the first metal reinforcement layer 230 is located within the fourth metal interconnect layer 241, and the minimum spacing between the side of the fourth metal interconnect layer 241 and the side of the first metal reinforcement layer 230 is not less than 500nm.

[0148] By ensuring that the minimum spacing between the side of the fourth metal interconnect layer 241 and the side of the first metal reinforcement layer 230 is not less than 500 nm, it is possible to ensure that the fourth metal interconnect layer 241 fully covers and supports the first metal reinforcement layer 230, thereby enhancing the overall mechanical stability of the structure.

[0149] In the second embodiment of this utility model, as Figure 14 In the embodiment shown, the multilayer stacked structure 200 further includes a fifth metal interconnect layer 244 stacked with the fourth metal inter-metal dielectric layer 242, and a fifth metal inter-metal dielectric layer 245 disposed between the fifth metal interconnect layer 244 and the device layer 110, wherein the fifth metal inter-metal dielectric layer 245 is provided with a fifth inter-layer via group 246.

[0150] The fifth metal interconnect layer 244 can be used for redistribution layer design, and the fifth metal inter-dielectric layer 245 can provide electrical insulation to prevent short circuits between adjacent metal interconnect layers.

[0151] Designers can adjust the specific structure of the fifth-layer via group 246 according to usage requirements, and no specific restrictions are imposed here. Specifically, the fifth-layer via group 246 includes multiple fifth-layer vias arranged at intervals.

[0152] Furthermore, since the first metal reinforcement layer 230 can effectively absorb and disperse the mechanical stress generated during the bonding process, preventing the stress from being transmitted downward to the metal interconnect layer and the inter-metal dielectric layer, the fifth interlayer via can be set inside or outside the projection of the window structure 310, without specific restrictions.

[0153] In the second embodiment of this utility model, as Figure 14In the embodiment shown, the multilayer stacked structure 200 further includes a sixth metal interconnect layer 247 and a sixth metal interconnect layer 248 disposed between the fifth metal inter-dielectric layer 245 and the device layer 110 and stacked alternately. The sixth metal interconnect layer 247 is connected to the fifth metal inter-dielectric layer 245. The sixth metal inter-dielectric layer 248 is provided with a sixth inter-layer via group 249. The sixth inter-layer via group 249 closest to the device layer 110 is electrically connected to the device layer 110.

[0154] By setting up multiple metal interconnect layers, different metal layers are used to achieve different functions. For example, the fourth metal interconnect layer 241 is used as the top layer to play the role of pressure buffering and interface adaptation, the fifth metal interconnect layer 244 is used as the middle layer to play the role of relay processing, and the sixth metal interconnect layer 247 is used as the bottom layer to play the role of signal transmission and ultimate support.

[0155] Of course, in other feasible embodiments, designers may adjust the specific arrangement of the metal layers and intermetallic dielectric layers in the multilayer stacked structure 200 according to the needs of use, and no specific restrictions are imposed here.

[0156] In the second embodiment of this utility model, a third hollow structure is provided on the fifth metal interconnect layer 244, and the fourth intermetallic dielectric layer 242 and the fifth intermetallic dielectric layer 245 located on both sides of the fifth metal interconnect layer 244 can be connected through the third hollow structure.

[0157] The third hollow structure can reduce the stiffness of the fifth metal interconnect layer 244, which helps to reduce or eliminate the stress on the fifth metal interconnect layer 244, avoid stress concentration, and thus reduce the risk of breakage.

[0158] Furthermore, the fourth intermetallic dielectric layer 242 and the fifth intermetallic dielectric layer 245 located on both sides of the fifth metal interconnect layer 244 can be connected through the third hollow structure to form a three-dimensional structure, which enhances the bonding force of adjacent intermetallic dielectric layers and reduces the risk of intermetallic dielectric layer breakage.

[0159] Designers can adjust the specific configuration of the third hollow structure according to usage needs, and no specific restrictions are imposed here. Preferably, the specific configuration of the third hollow structure is the same as or similar to the configuration of the first hollow structure 220.

[0160] In the second embodiment of this utility model, a fourth hollow structure is provided on the sixth metal interconnect layer 247, and the fifth intermetallic dielectric layer 245 and the sixth intermetallic dielectric layer 248 located on both sides of the sixth metal interconnect layer 247 can be connected through the fourth hollow structure.

[0161] The fourth hollow structure can reduce the stiffness of the sixth metal interconnect layer 247, which helps to reduce or eliminate the stress on the sixth metal interconnect layer 247, avoid stress concentration, and thus reduce the risk of breakage.

[0162] Furthermore, the fifth intermetallic dielectric layer 245 and the sixth intermetallic dielectric layer 248 located on both sides of the sixth metal interconnect layer 247 can be connected through the fourth hollow structure to form a three-dimensional structure, which enhances the bonding force of adjacent intermetallic dielectric layers and reduces the risk of intermetallic dielectric layer breakage.

[0163] Designers may adjust the specific configuration of the fourth hollow structure according to usage requirements, and no specific restrictions are imposed here. Preferably, the configuration of the fourth hollow structure is the same as or similar to that of the first hollow structure 220.

[0164] In the third embodiment of this utility model, the difference from the second embodiment is that the multilayer stacked structure 200 further includes a second metal reinforcement layer 260, such as... Figure 15 In the embodiment shown, the second metal reinforcement layer 260 is disposed between the first metal reinforcement layer 230 and the fourth metal interconnect layer 241, and the projection of the second metal reinforcement layer 260 is located within the first metal reinforcement layer 230 along the thickness direction of the substrate layer 100.

[0165] The first metal reinforcement layer 230 and the second metal reinforcement layer 260 work together to form an inverted pyramid structure, further preventing bonding pressure from damaging the multilayer stacked structure 200 below the first interconnect layer 120.

[0166] Designers can adjust the specific material of the second metal reinforcement layer 260 according to the application requirements, and no specific restrictions are imposed here. Preferably, the material of the second metal reinforcement layer 260 is tungsten.

[0167] In the third embodiment of this utility model, as Figure 15 In the illustrated embodiment, the multilayer stacked structure 200 further includes a second dielectric layer 270 surrounding the outer side of the second metal reinforcement layer 260 and positioned between the first dielectric layer 250 and the fourth metal interconnect layer 241. By providing the second dielectric layer 270 around the second metal reinforcement layer 260, the second dielectric layer 270 can provide insulation and physical protection for the second metal reinforcement layer 260.

[0168] Designers can adjust the specific arrangement of the first dielectric layer 250 and the second dielectric layer 270 according to usage requirements, and no specific limitations are imposed here. In one feasible embodiment, the first dielectric layer 250 and the second dielectric layer 270 are stacked. In another feasible embodiment, such as Figure 15 In the embodiment shown, the first dielectric layer 250 and the second dielectric layer 270 are integrally disposed.

[0169] In the third embodiment of this utility model, along the thickness direction of the substrate layer 100, the projection of the second metal reinforcement layer 260 is located within the window structure 310, and the projected area of ​​the second metal reinforcement layer 260 is not less than 80% of the area of ​​the window structure 310.

[0170] Specifically, the center of the second metal reinforcement layer 260 coincides with that of the window structure 310. By ensuring that the projected area of ​​the second metal reinforcement layer 260 is not less than 80% of the area of ​​the window structure 310, it is possible to ensure that the bonding pressure is evenly distributed and effectively transmitted to the second metal reinforcement layer 260, thereby further improving the compressive strength.

[0171] In the third embodiment of this utility model, along the thickness direction of the substrate layer 100, the projection of the second metal reinforcement layer 260 is located within the fourth metal interconnect layer 241, and the minimum spacing between the side of the second metal reinforcement layer 260 and the side of the fourth metal interconnect layer 241 is not less than 500 nm.

[0172] By ensuring that the minimum spacing between the side of the second metal reinforcement layer 260 and the side of the fourth metal interconnect layer 241 is not less than 500 nm, it is possible to ensure that the fourth metal interconnect layer 241 fully covers and supports the second metal reinforcement layer 260, thereby enhancing the overall mechanical stability and load-bearing capacity of the structure.

[0173] Implementation Method 2

[0174] An embodiment of this utility model also discloses an ultrasonic fingerprint recognition module, which includes a bonding structure as described in Embodiment 1. The structure and effect of this bonding structure are the same as those described in Embodiment 1, and will not be repeated here.

[0175] Designers can adjust the specific structure of the ultrasonic fingerprint recognition module according to their needs, and no specific restrictions are imposed here.

[0176] The substrate 100 of the ultrasonic fingerprint recognition module includes, but is not limited to, silicon-based, glass-based, etc., and the functional layers on the substrate include, but are not limited to, piezoelectric materials such as PVDF, AlN, and PZT.

[0177] In one feasible embodiment, the substrate 100 is a silicon-based substrate, and the functional layer on the substrate 100 is configured as PVDF, so that the ultrasonic fingerprint recognition module constitutes a PVDF silicon-based ultrasonic fingerprint recognition module.

[0178] Implementation Method 3

[0179] An electronic device is also disclosed in the embodiments of this utility model, which includes an ultrasonic fingerprint recognition module as described in Embodiment 2.

[0180] The structure and effect of the ultrasonic fingerprint recognition module are the same as those described in Embodiment 2, and will not be repeated here. This electronic device includes, but is not limited to, mobile terminal devices, such as mobile phones, laptops, tablets, etc.

[0181] In an embodiment of this utility model, the electronic device includes a screen, and an ultrasonic fingerprint recognition module is disposed below the screen for recognizing the fingerprint of a finger pressed on the display screen.

[0182] All articles and references disclosed herein, including patent applications and publications, are incorporated herein by reference for various purposes. The term “substantially constitutes…” used to describe a combination should include the identified element, component, part, or step, as well as other elements, components, parts, or steps that do not substantially affect the essential novelty of the combination. The use of the terms “comprising” or “including” to describe combinations of elements, components, parts, or steps herein also contemplates embodiments substantially constituted by such elements, components, parts, or steps. The use of the term “may” herein is intended to indicate that any described attribute “may” include is optional. Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The disclosure of “a” or “an” used to describe an element, component, part, or step does not imply exclusion of other elements, components, parts, or steps.

[0183] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be included within the scope of protection of this utility model.

Claims

1. A bonding structure, characterized by, The application relates to a substrate layer, a passivation layer and a bonding structure. The substrate layer comprises a device layer, a first interconnection layer and a multilayer stack structure arranged between the device layer and the first interconnection layer for playing a role of electrical signal transmission and / or stress buffering. The passivation layer is arranged on the substrate layer and covers the first interconnection layer, and a window structure is arranged on the passivation layer.

2. The bonding structure of claim 1, wherein The bonding structure is used for bonding with a flexible circuit board, and the flexible circuit board is provided with a second interconnection layer electrically connected with the first interconnection layer.

3. The bonding structure of claim 1, wherein The first interconnection layer comprises a metal pad arranged on the substrate layer.

4. The bonding structure of claim 3, wherein The metal pad is an aluminum pad.

5. The bonding structure of claim 1, wherein The first interconnect layer has an area of 8000 μm 2 to 50000 μm 2 .

6. The bonding structure of claim 1, wherein The window structure is configured as a rectangle, the width of the window structure is greater than or equal to 0.04 mm, and the length of the window structure is greater than or equal to 0.2 mm.

7. The bonding structure of claim 2, wherein The second interconnection layer comprises an ACF layer arranged on the flexible circuit board.

8. The bonding structure of claim 1, wherein The multilayer stack structure comprises a first metal interconnection layer electrically connected with the first interconnection layer, a first intermetallic medium layer arranged between the first metal interconnection layer and the device layer, and a first interlayer via group arranged on the first intermetallic medium layer, wherein, along the thickness direction of the substrate layer, the first interlayer via group is arranged outside the projection of the window structure.

9. The bonding structure of claim 8, wherein The thickness of the first interconnection layer is greater than or equal to 11 KA.

10. The bonding structure of claim 8, wherein The multilayer stack structure further comprises a second metal interconnection layer arranged in a stack with the first intermetallic medium layer, a second intermetallic medium layer arranged between the second metal interconnection layer and the device layer, and a second interlayer via group arranged on the second intermetallic medium layer.

11. The bonding structure of claim 10, wherein Along the thickness direction of the substrate layer, the second interlayer via group is arranged outside the projection of the window structure.

12. The bonding structure of claim 10, wherein The second metal interconnection layer is provided with a first hollow structure, and the first intermetallic medium layer and the second intermetallic medium layer located on both sides of the second metal interconnection layer can be connected through the first hollow structure.

13. The bonding structure of claim 12, wherein, The first hollow structure comprises a plurality of first communication holes penetrating through the second metal interconnection layer, and the first intermetallic medium layer and the second intermetallic medium layer located on both sides of the first communication hole are connected through the first communication hole, and the total area of the plurality of first communication holes is not less than half of the total area of the second metal interconnection layer. Or, the first hollow structure divides the second metal interconnection layer into a plurality of first metal strips arranged at intervals, a first communication gap is formed between adjacent first metal strips, and the first intermetallic medium layer and the second intermetallic medium layer located on both sides of the second metal interconnection layer are connected through the first communication gap, and the total area of the plurality of first communication gaps is not less than half of the total area of the second metal interconnection layer.

14. The bonding structure of claim 13, wherein, Along the thickness direction of the substrate layer, the projection shape of the first communication hole is a regular polygon.

15. The bonding structure of claim 13, wherein The window structure is arranged in a rectangular shape, the interval distance between adjacent first communication holes is less than 1 / 10 of the width of the window structure, and / or the maximum pore diameter of the first communication hole is greater than the interval distance between adjacent first communication holes.

16. The bonding structure of claim 13, wherein The first communication holes are arranged in a rectangular array or in a staggered array.

17. The bonding structure of claim 10, wherein The multilayer stack structure further comprises third metal interconnection layers and third intermetal dielectric layers arranged between the second intermetal dielectric layer and the device layer and staggered and stacked, the third metal interconnection layers are connected with the second intermetal dielectric layer, each of the third intermetal dielectric layers is provided with a third group of interlayer vias, and the third group of interlayer vias closest to the device layer is electrically connected with the device layer.

18. The bonding structure of claim 17, wherein, The third metal interconnection layer is provided with a second hollow structure, and the second intermetal dielectric layer and the third intermetal dielectric layer on both sides of the third metal interconnection layer can be connected through the second hollow structure.

19. The bonding structure of claim 1, wherein The multilayer stack structure comprises a first metal reinforcement layer electrically connected with the first interconnection layer, a fourth metal interconnection layer electrically connected with the first metal reinforcement layer, and a fourth intermetal dielectric layer arranged between the fourth metal interconnection layer and the device layer, and the fourth intermetal dielectric layer is provided with a fourth group of interlayer vias.

20. The bonding structure of claim 19, wherein, The thickness of the first interconnection layer is greater than or equal to 6 KA.

21. The bonding structure of claim 19, wherein, The material of the first metal reinforcement layer is tungsten.

22. The bonding structure of claim 19, wherein, The thickness of the first metal reinforcement layer is not less than 200 nm.

23. The bonding structure of claim 19, wherein, In the thickness direction of the substrate layer, the projection of the first interconnection layer is located in the first metal reinforcement layer, and the minimum interval between the side edge of the first metal reinforcement layer and the side edge of the first interconnection layer is not less than 200 nm.

24. The bonding structure of claim 19, wherein, The multilayer stack structure further comprises a first dielectric layer arranged outside the first metal reinforcement layer and located between the passivation layer and the fourth metal interconnection layer.

25. The bonding structure of claim 19, wherein, In the thickness direction of the substrate layer, the projection of the first metal reinforcement layer is located in the fourth metal interconnection layer, and the minimum interval between the side edge of the fourth metal interconnection layer and the side edge of the first metal reinforcement layer is not less than 500 nm.

26. The bonding structure of claim 24, wherein, The multilayer stack structure further comprises a fifth metal interconnection layer stacked with the fourth intermetal dielectric layer, and a fifth intermetal dielectric layer arranged between the fifth metal interconnection layer and the device layer, and the fifth intermetal dielectric layer is provided with a fifth group of interlayer vias.

27. The bonding structure of claim 26, wherein, The multilayer stack structure further comprises sixth metal interconnection layers and sixth intermetal dielectric layers arranged between the fifth intermetal dielectric layer and the device layer and staggered and stacked, the sixth metal interconnection layers are connected with the fifth intermetal dielectric layer, the sixth intermetal dielectric layers are provided with a sixth group of interlayer vias, and the sixth group of interlayer vias closest to the device layer is electrically connected with the device layer.

28. The bonding structure of claim 26, wherein, The multilayer stack structure further comprises a second metal reinforcement layer arranged between the first metal reinforcement layer and the fourth metal interconnection layer, and in the thickness direction of the substrate layer, the projection of the second metal reinforcement layer is located in the first metal reinforcement layer.

29. The bonding structure of claim 28, wherein, The multilayer stack structure further comprises a second dielectric layer arranged outside the second metal reinforcement layer and located between the first dielectric layer and the fourth metal interconnection layer.

30. The bonding structure of claim 28, wherein, The material of the second metal reinforcement layer is tungsten.

31. The bonding structure of claim 28, wherein The projection of the second metal reinforcing layer is located in the window structure along the thickness direction of the substrate layer, and the projected area of the second metal reinforcing layer is not less than 80% of the area of the window structure.

32. The bonding structure of claim 31, wherein The projection of the second metal reinforcing layer is located in the fourth metal interconnection layer along the thickness direction of the substrate layer, and the minimum spacing between the side of the second metal reinforcing layer and the side of the fourth metal interconnection layer is not less than 500 nm.

33. The bonding structure of claim 27, wherein The fifth metal interconnection layer is provided with a third hollow structure, and the fourth intermetallic medium layer and the fifth intermetallic medium layer located on both sides of the fifth metal interconnection layer can be connected through the third hollow structure.

34. The bonding structure of claim 33, wherein, The sixth metal interconnection layer is provided with a fourth hollow structure, and the fifth intermetallic medium layer and the sixth intermetallic medium layer located on both sides of the sixth metal interconnection layer can be connected through the fourth hollow structure.

35. An ultrasonic fingerprint identification module, comprising: The bonding structure as claimed in any one of claims 1 to 33.

36. An electronic device, comprising: The ultrasonic fingerprint identification module as claimed in claim 35.

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