Single-ended capacitance sampling circuit, capacitance sensor, analog-to-digital converter and electronic equipment
By simplifying the differential capacitance sampling circuit into a single-ended capacitance sampling circuit, and using the same reference voltage source and shielding electrode, the problems of high area and power consumption in the prior art are solved, and low power consumption and high anti-interference capacitance sampling effect are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2026-03-06
AI Technical Summary
Existing differential capacitor sampling circuits have high area and power consumption in low-power devices, and insufficient anti-interference capability.
A single-ended capacitor sampling circuit is adopted, which is simplified to a switched capacitor circuit and a fixed capacitor circuit. It uses the same reference voltage source and combines shielded electrodes and a drive module to reduce capacitor and circuit complexity and improve anti-interference capability.
It effectively reduces circuit footprint and power consumption, improves sampling accuracy and anti-interference capability, and is suitable for low-power devices.
Smart Images
Figure CN223978642U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of sensors, and provides a single-ended capacitance sampling circuit, a capacitance sensor, an analog-to-digital converter, and an electronic device. Background Technology
[0002] like Figure 1 As shown, Figure 1 This is a schematic diagram of a prior art differential capacitor sampling circuit, where Vrefp and Vrefn are two different reference voltage sources, Vrefn is at 0 potential, and S7 and S8 are two switches controlled by different clock signals, with their closing times not overlapping. This capacitor sampling circuit includes two switched capacitor circuits with identical structures, differing only in the capacitors used. Figure 1 In the switched capacitor circuit on the right, Cn1 and Cn2 are capacitors with equal capacitance. Due to the law of conservation of charge, when S8 is closed and S1 is open, the voltage at the connection point of Cn1 and Cn2 is Vn = Vrefp / 2.
[0003] Figure 1 In the switched capacitor circuit on the left, Cp is the adjustable capacitor, Cx is the capacitor to be tested, and the voltage at the connection between Cp and Cx is denoted as Vp. Since the two switched capacitor circuits are identical and connected to the same reference voltage source, based on the principle of charge conservation, the voltage Vp = Vrefp * Cp / (Cx + Cp) and Vn = Vrefp / 2. When the capacitance of Cp is adjusted until Vp = Vn, it can be found that Cx = Cp. Therefore, by adjusting Cp and detecting the voltages of Vp and Vn until Vp = Vn, the capacitor to be tested, Cx = Cp, can be achieved.
[0004] However, the area and power consumption of this circuit need to be reduced so that it can be used in some low-power devices. Utility Model Content
[0005] In view of this, this application aims to provide a single-ended capacitance sampling circuit, a capacitance sensor, an analog-to-digital converter, and an electronic device to reduce the power consumption and area occupied by the capacitance sampling circuit.
[0006] First, this application provides a single-ended capacitance sampling circuit, including: a first switched capacitor circuit, the switched capacitor circuit including a capacitor under test, a first adjustable capacitor, a first switch, a second switch, a third switch, a fifth switch, and a sixth switch; the first terminal of the capacitor under test is connected through the sixth switch and the second terminal of the first adjustable capacitor, and is also connected to the third switch; the second terminal of the capacitor under test is grounded; the first terminal of the first adjustable capacitor is connected to the first switch and the fifth switch respectively; the second terminal of the first adjustable capacitor is also connected to the second switch; a second switched capacitor circuit, including a second capacitor and a fourth switch, the first terminal of the second capacitor is connected to the fourth switch, and the second terminal of the second capacitor is connected to a second reference voltage source. The capacitance of the second capacitor is a preset value, and the second reference voltage source is used to provide a 0 potential; the first switch, the second switch, the third switch, and the fourth switch are closed when the first clock signal is high; the fifth switch and the sixth switch are closed when the second clock signal is high; the first clock signal and the second clock signal are non-overlapping clocks; the first switch and the third switch are respectively connected to the second reference voltage source; the fourth switch is connected to the third reference voltage source; the fifth switch is connected to the first reference voltage source, the second switch is connected to the second reference voltage source, and the voltage output by the third reference voltage source is equal to half of the first reference voltage source; or, the fifth switch and the second switch are both connected to the third reference voltage source.
[0007] Existing differential capacitance sampling circuits include switched capacitor circuits with two equal capacitances (such as...). Figure 1 As shown in Cn1 and Cn2, this switched capacitor circuit provides a reference voltage, which is the voltage at the connection point of two equal capacitors. Since the capacitance values of the two capacitors are equal, in the principle of charge conservation, when adjusting the capacitance value of the adjustable capacitor, it can be determined whether the voltage at the connection point of the adjustable capacitor and the capacitor under test is equal to the reference voltage, thereby determining whether the adjustable capacitor and the capacitor under test are consistent. Based on this principle, in this embodiment, one of the switched capacitor circuits including two fixed capacitors can be modified to include only one second capacitor, and a driving voltage is provided at the first terminal of the second capacitor as a reference voltage for adjusting the capacitance value of the first adjustable capacitor in the switched capacitor circuit. This ensures that the driving voltage is equal to the voltage at the connection point of the first adjustable capacitor and the capacitor under test, provided that the capacitance values of the first adjustable capacitor and the capacitor under test are equal, thus achieving capacitance sampling. In this single-ended capacitor sampling circuit, since only one switched capacitor circuit and one second capacitor are used, compared with the prior art, the use of capacitors is reduced, as are the use of other supporting circuits, the timing signal output and switching control are reduced, and the required circuit area and power consumption are effectively reduced.
[0008] In this scenario, when the capacitance values of the first adjustable capacitor and the capacitor under test are equal, and the voltage output by the third reference voltage source is equal to half of the voltage output by the first reference voltage source, the fifth switch is connected to the first reference voltage source, and the second switch is connected to the second reference voltage source. This allows the capacitance between the first adjustable capacitor and the capacitor under test to be equal to the voltage of the third reference voltage source, which is also equal to the voltage of the second capacitor connected through the fourth switch, thus enabling capacitance sampling.
[0009] Alternatively, when there are two voltage sources, the third reference voltage source and the first reference voltage source, the voltage output by the third reference voltage source may not be exactly equal to the voltage at the connection point between the first adjustable capacitor and the capacitor under test due to process and environmental factors. This affects the accurate acquisition of the capacitance, resulting in poor anti-interference capability of the single-ended capacitor sampling circuit, and the introduction of more background noise due to the presence of voltages from different sources. Therefore, in the embodiments of this application, only the third reference voltage source can be used to provide voltage to the switched capacitor circuit, thereby achieving a common voltage source. Meanwhile, since the first terminal of the first adjustable capacitor is connected to the third reference voltage source, the voltage at the junction of the first adjustable capacitor and the capacitor under test will not be equal to the voltage output by the third reference voltage source. Therefore, the second terminal of the first adjustable capacitor can be connected to the third reference voltage source. This allows the first adjustable capacitor to store an initial charge when the first and second switches are closed. When the first and second switches are open, and the fifth and sixth switches are closed, an initial voltage is generated at the junction of the first adjustable capacitor and the voltage under test. Combined with the driving voltage provided by the driving module, the voltage at the junction of the first adjustable capacitor and the voltage under test can be equal to the voltage output by the third reference voltage source. This method reduces the use of a reference voltage source, effectively reducing the occupied area and power consumption, and reducing background noise. Furthermore, since the voltage sources are from the same source, the voltage will not be inconsistent due to environmental or process influences, improving sampling accuracy and effectively enhancing anti-interference capabilities.
[0010] In one embodiment, the driving voltage is provided by a driving module, and the single-ended capacitor sampling circuit further includes a shielding electrode; the shielding electrode surrounds the capacitor under test; the shielding electrode is connected to the driving module under the control of the second clock signal, and the driving module is used to provide the driving voltage.
[0011] In this embodiment, a shielding electrode is used to wrap the capacitor under test. When water falls on the capacitor, it changes the capacitance of the shielding electrode, thus preventing the capacitance of the capacitor under test from changing and achieving waterproofing. However, the shielding electrode wrapping around the capacitor under test creates a parasitic capacitance between the shielding electrode and the capacitor, affecting the voltage at the connection point between the first adjustable capacitor and the capacitor under test. Therefore, the shielding electrode can be connected to a driving module, so that the driving voltage provided by the driving module restores the voltage at the connection point between the first adjustable capacitor and the capacitor under test to be consistent with the driving voltage. Thus, the single-ended capacitance sampling circuit achieves waterproofing without affecting capacitance detection.
[0012] In one embodiment, when the fifth switch is connected to the first reference voltage source, the driving voltage is half of the first reference voltage.
[0013] In this embodiment, a parasitic capacitance is formed between the shielding electrode and the capacitor under test, affecting the actual voltage at the capacitor under test. When the first adjustable capacitor and the capacitor under test are connected to the circuit in the switched capacitor circuit, there are no other capacitors in the second switched capacitor circuit. When the capacitor under test is equal to the first adjustable capacitor, since the voltage of the switched capacitor circuit is provided by the first reference voltage source, the voltage at the connection between the first adjustable capacitor and the capacitor under test is equal to half of the first reference voltage output by the first reference voltage source. Therefore, the first reference voltage can be twice the driving voltage (or the driving voltage is equal to half of the first reference voltage), so that the voltage of the capacitor under test can be equal to the voltage at the first adjustable capacitor, thereby enabling the single-ended capacitor sampling circuit to accurately sample.
[0014] In one embodiment, the driving module is the third reference voltage source.
[0015] In this embodiment, the voltage source is reused (i.e., the driving module is used as the third reference voltage source), so that the third reference voltage source is also used to provide the third reference voltage to the shielding electrode. This achieves the reuse of the third reference voltage source, reduces the voltage source required, reduces the input noise floor, further reduces the required circuit area and power consumption, and improves the anti-interference capability.
[0016] Secondly, embodiments of this application provide a capacitive sensor, comprising: a single-ended capacitance sampling circuit as described in any of the first aspects; a third reference voltage source for providing a third reference voltage and connected to the fourth switch; a second reference voltage source for providing a 0 potential and connected to the second terminal of the second capacitor, the first switch, and the third switch; wherein the third reference voltage source is connected to the fifth switch and the second switch; or, the capacitive sensor further comprises: a first reference voltage source connected to the fifth switch, and the second reference voltage source is also connected to the second switch; the first reference voltage source is used to provide a first reference voltage.
[0017] In one embodiment, the single-ended capacitance sampling circuit includes a shielding electrode, and the capacitance sensor further includes a driving module connected to the shielding electrode; the driving module is used to provide a driving voltage, which is half of the first reference voltage.
[0018] Thirdly, embodiments of this application provide an analog-to-digital converter, including the capacitive sensor as described in the second aspect.
[0019] In one embodiment, the analog-to-digital converter is one of the following: a successive approximation analog-to-digital converter; a Sigma-delta analog-to-digital converter; or a scaling analog-to-digital converter.
[0020] Successive approximation analog-to-digital converters (ADCs), Sigma-delta ADCs, and scaling ADCs are all low-power ADCs commonly used in low-power scenarios. In the embodiments of this application, the use of capacitive sensors including single-ended capacitance sampling circuits in the successive approximation ADCs, Sigma-delta ADCs, and scaling ADCs helps to further reduce power consumption.
[0021] Fourthly, embodiments of this application provide an electronic device, including a capacitive sensor as described in the second aspect or an analog-to-digital converter as described in the third aspect.
[0022] In one embodiment, the electronic device is a wearable device.
[0023] Wearable devices, due to their size limitations, have relatively small battery capacities, thus requiring high power consumption. In the embodiments of this application, incorporating the aforementioned capacitive sensor or analog-to-digital converter into the wearable device helps reduce power consumption and improve its battery life. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of a prior art differential capacitance sampling circuit;
[0026] Figure 2 A schematic diagram of a single-ended capacitor sampling circuit provided in one embodiment of the application;
[0027] Figure 3A schematic diagram of a non-overlapping clock signal provided in an embodiment of this application;
[0028] Figure 4 This is a first voltage schematic diagram of a single-ended capacitor sampling circuit provided in an embodiment of this application;
[0029] Figure 5 This is a second voltage schematic diagram of a single-ended capacitor sampling circuit provided in an embodiment of this application;
[0030] Figure 6 This is a schematic diagram of the equivalent circuit for connecting the shielding electrode according to an embodiment of this application.
[0031] Icons: First switched capacitor circuit 110; Second switched capacitor circuit 120. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0033] First, this application provides a single-ended capacitor sampling circuit. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of a single-ended capacitance sampling circuit according to an embodiment of this application. The single-ended capacitance sampling circuit includes: a first switched capacitor circuit 110 and a second switched capacitor circuit 120. Wherein, C1 is a first adjustable capacitor, C2 is a second capacitor, C3 is the capacitor to be tested, S1 to S6 are the first to sixth switches, Vp is the voltage at the junction of the capacitor to be tested and the first adjustable capacitor, Vn is the voltage at the first terminal of the second capacitor, V2 is the 0 potential provided by the second reference voltage source, and V3 is the driving voltage output by the driving module.
[0034] The first switched capacitor circuit 110 includes a capacitor under test, a first adjustable capacitor, a first switch, a second switch, a third switch, a fifth switch, and a sixth switch, as follows: Figure 2 As shown, the first terminal of the capacitor under test is connected to the second terminal of the first adjustable capacitor via the sixth switch, and is also connected to the third switch; the second terminal of the capacitor under test is grounded. The first terminal of the first adjustable capacitor is connected to both the first switch and the fifth switch; the second terminal of the first adjustable capacitor is also connected to the second switch.
[0035] The second switched capacitor circuit 120 includes a second capacitor and a fourth switch. The first terminal of the second capacitor is connected to the fourth switch, and the second terminal of the second capacitor is connected to a second reference voltage source. The capacitance of the second capacitor is a preset value, and the second reference voltage source provides a zero potential. The capacitance of the second capacitor is adjustable and can be preset to be equal to the capacitance of the first adjustable capacitor.
[0036] In the circuit shown in the accompanying drawings of this application, regardless of whether it is the capacitor under test, the first adjustable capacitor, or the second capacitor, the first end can be regarded as the upper end of the capacitor, and the second end can be regarded as the lower end of the capacitor. It should be noted that in the embodiments of this application, the first end and the second end are the two ends of the capacitor, and the use of first and second is only for distinction and has no special reference.
[0037] In the embodiments of this application, the first switch, the second switch, the third switch, and the fourth switch are closed when the first clock signal is high. The fifth switch and the sixth switch are closed when the second clock signal is high. The first clock signal and the second clock signal are non-overlapping clocks, meaning that their high-level times do not coincide.
[0038] Please see Figure 3 , Figure 3 This is a schematic diagram of a non-overlapping clock signal provided in one embodiment of the present application. The first clock signal and the second clock signal do not overlap, and there is no overlap between them during the high-level time. Therefore, under the control of the first clock signal and the second clock signal, when the first switch, the second switch, the third switch and the fourth switch are closed, the fifth switch and the sixth switch are open. Conversely, when the first switch, the second switch, the third switch and the fourth switch are open, the fifth switch and the sixth switch are closed.
[0039] In the embodiments of this application, when the first, second, third, and fourth switches are closed, the first adjustable capacitor, the second capacitor, and the capacitor under test are connected to the circuit, and the single-ended capacitance sampling circuit is in the first stage of capacitance sampling. When the fifth and sixth switches are closed, the single-ended capacitance sampling circuit is in the second stage of sampling, and the two stages together complete one sampling.
[0040] In the embodiments of this application, a first reference voltage source is used to provide a first reference voltage V1, a second reference voltage source is used to provide a second reference voltage V2, wherein the second reference voltage is 0 potential, and a third reference voltage source is used to provide a third reference voltage V3.
[0041] Existing differential capacitance sampling circuits measure the capacitance value of the capacitor under test based on the principle of charge conservation, such as... Figure 1 As shown, the existing differential capacitor sampling circuit includes two switched capacitor circuits, one of which is... Figure 1The circuit on the right includes two fixed capacitors, Cn1 and Cn2, with equal capacitance values. Therefore, the voltage Vn at the junction of Cn1 and Cn2 is equal to half the voltage output by the reference voltage source Vrefp, i.e., Vn = Vrefp / 2. Another switched capacitor circuit includes an adjustable capacitor Cp and a capacitor Cx under test. The voltage Vp at the junction of the adjustable capacitor Cp and the capacitor Cx under test is Vp = Vrefp * Cp / (Cx + Cp).
[0042] In this differential capacitor circuit, the voltage sources connected to the two switched capacitor circuits are the same. Therefore, according to the principle of charge conservation, Vrefp*Cp / (Cx+Cp)=Vrefp / 2, and when Vn and Vp are equal, Cp=Cx can be made.
[0043] Therefore, when adjusting the capacitance value of the adjustable capacitor, it can be determined that the capacitance value of the adjustable capacitor is equal to the capacitance value of the capacitor under test when the voltage at the junction of the adjustable capacitor and the capacitor under test is equal to the reference voltage value Vn.
[0044] Based on this principle, the embodiments of this application simplify the existing capacitor sampling circuit by using only one first switched capacitor circuit 110. The two switched capacitor circuits in the differential capacitor sampling circuit are simplified into a first switched capacitor circuit 110 and a second switched capacitor circuit, so that the second capacitor receives the third reference voltage provided by the third reference voltage source, and the second capacitor can have a fixed voltage.
[0045] Then, the third reference voltage provided by the third reference voltage source is used as the reference object. That is, the third reference voltage is: the voltage at the connection point between the first adjustable capacitor and the capacitor under test when the capacitance values of the first adjustable capacitor and the capacitor under test are equal. Figure 1 For example, it can be expressed as V3 = Vn = Vp.
[0046] In the embodiments of this application, the circuit provided in the above embodiments can achieve sampling by providing different reference voltages.
[0047] Please see Figure 4 , Figure 4 This is a first voltage schematic diagram of a single-ended capacitor sampling circuit provided in an embodiment of this application. In an optional embodiment, the first end of the first adjustable capacitor is connected to a first reference voltage source through a fifth switch, and the second end of the first adjustable capacitor is connected to a second reference voltage source through a second switch.
[0048] In this embodiment, when the first adjustable capacitor is equal to the capacitor under test, the voltage Vp at the junction of the first adjustable capacitor and the capacitor under test is equal to half of the first reference voltage, that is, Vp = V1 / 2. If Vp is equal to the third reference voltage, then Vp = V3, V3 = V1 / 2. Therefore, 2*V3 = V1. The first reference voltage is twice the driving voltage, or it can be expressed as the voltage output by the third reference voltage source being equal to half of the first reference voltage source.
[0049] In this embodiment, when the first clock signal controls the first switch, the second switch, the third switch, and the fourth switch to close, and the second clock signal controls the fifth switch and the sixth switch to open, the capacitor under test and the first adjustable capacitor are disconnected, the two ends of the first adjustable capacitor are connected to a potential of 0, and the charge of the first adjustable capacitor is 0.
[0050] When the first clock signal controls the first, second, third, and fourth switches to open, and the second clock signal controls the fifth and sixth switches to close, and the first adjustable capacitor has been adjusted to be equal to the capacitor under test, the voltage Vp at the junction of the first adjustable capacitor and the capacitor under test is V1 / 2, and the voltage output of the third reference voltage source is V3 = V1 / 2, and Vp = V3. Based on the aforementioned principle of charge conservation, it can be determined that C1 = C3 at this time.
[0051] In the above embodiment, the second reference voltage source is at 0 potential, which does not affect the circuit's noise floor. However, the first and third reference voltage sources are different voltage sources. On the one hand, the voltages from different voltage sources will increase the noise floor. On the other hand, due to environmental and process influences, the output voltages of the first and third reference voltage sources may not meet expectations during use; for example, they may be slightly higher or lower. This will affect the accuracy of the test.
[0052] Therefore, in the embodiments of this application, another optional embodiment is also provided to solve this problem. Please refer to... Figure 5 , Figure 5 This is a second voltage schematic diagram of a single-ended capacitor sampling circuit provided in one embodiment of this application. In this optional embodiment, both the fifth switch and the second switch are connected to a third reference voltage source.
[0053] Different from Figure 4 The given embodiments, in such cases Figure 4 In the example of connecting to the first reference voltage source, when the first switch and the second switch are closed, the two ends of the first adjustable capacitor are connected to the second reference voltage source (0 potential), which makes the initial charge of the first adjustable capacitor 0.
[0054] exist Figure 5In the circuit shown, when the first and second switches are closed, the initial charge of the first adjustable capacitor needs to be non-zero. Therefore, the second terminal of the first adjustable capacitor can be connected to the third reference voltage source through the second switch. In this embodiment, when the first, second, third, and fourth switches are closed, and the fifth and sixth switches are open, the voltage of the first adjustable capacitor is the third reference voltage. Thus, one end of the first adjustable capacitor is connected to the second reference voltage source (0 potential), and the other end is connected to the third reference voltage source. This makes the charge at node Vp Q1 = V3 * C1. When the fifth and sixth switches are closed, the actual charge at node Vp is Q2 = Vp * C3 + (Vp - V3) * C1. Based on the law of conservation of charge, Q1 = Q2, which leads to Vp = 2 * V3 * C1 / (C1 + C3). When the capacitance values of the capacitor under test and the first adjustable capacitor are equal, Vp = V3, satisfying the condition that the driving voltage is equal to the voltage Vp at the connection point between the first adjustable capacitor and the capacitor under test.
[0055] In this embodiment, the second reference voltage source provides a 0 potential, which will not affect the circuit noise floor. Only the third reference voltage source provides the voltage, that is, there is only one voltage source in the single-ended capacitor sampling circuit. The same voltage source provides the same voltage at different locations. This method will effectively reduce the situation where the voltages provided by different voltage sources cannot be equal due to environmental and process influences, thus leading to inaccurate capacitor sampling. It improves the anti-interference capability of the single-ended capacitor sampling circuit and reduces the noise floor introduced by different voltage sources.
[0056] A capacitance sensor detects capacitance by collecting data and converting it into a voltage value. Therefore, a capacitance sensor includes a capacitance sampling circuit.
[0057] Capacitive sensors are used to convert capacitance into voltage or current values. Therefore, a single-ended capacitance sampling circuit can be used for capacitive sensors. Since capacitive sensors are widely used in human-machine interfaces of electronic devices and in home appliances, they need to be waterproof to prevent accidental contact with water or other substances. Therefore, in the embodiments of this application, the single-ended capacitance sampling circuit can also be made waterproof.
[0058] In the embodiments of this application, the single-ended capacitance sampling circuit may further include a shielding electrode, which is disposed on the surface of the capacitor under test to wrap the capacitor under test. At the same time, the shielding electrode is grounded so that the single-ended capacitance sampling circuit can achieve a waterproof function.
[0059] Please see Figure 6 , Figure 6This is a schematic diagram of an equivalent circuit for connecting a shielding electrode according to an embodiment of this application, wherein Vsh is the voltage of the shielding electrode, Csh is the parasitic capacitance of the shielding electrode grounded, and C3_sh is the parasitic capacitance between the shielding electrode and the capacitor under test.
[0060] The shielding electrode wraps around the capacitor under test. Water will actually drip onto the surface of the shielding electrode, thereby increasing the parasitic capacitance between the shielding electrode and the capacitor under test. However, the capacitance value of the capacitor under test, Cx, will not change significantly, thus achieving waterproofing.
[0061] Parasitic capacitances are generated between the shielding electrode and the capacitor under test, as well as between the shielding electrode and ground, affecting the actual voltage at the capacitor under test. Therefore, an additional voltage needs to be provided to the shielding electrode so that the actual voltage at the first terminal of the capacitor under test is equal to the third reference voltage. In the embodiments of this application, the shielding electrode can be connected to the driving module to provide a driving voltage to the shielding electrode.
[0062] In embodiments of this application, the shielding electrode can be connected to the driving module under the control of a second clock signal, wherein the driving module is used to provide a driving voltage.
[0063] When the fifth switch is connected to the first reference voltage source, it is originally expected that the voltage at the junction of the capacitor under test and the first adjustable capacitor will be equal to half of the first reference voltage, that is, equal to the third reference voltage. However, in reality, when the first reference voltage provides the first reference voltage to the capacitor under test, the voltage at the junction of the capacitor under test and the first adjustable capacitor will be evenly divided by the parasitic capacitance formed between the capacitor under test and the shielding electrode, such as... Figure 6 As shown, this ensures that the voltage Cp at the capacitor under test and the voltage Vsh at the shielding electrode are equal. Since Vsh and Vp are the same, the charge at node Vp will not be affected. The charge at this node is equal to the capacitance multiplied by the voltage, Q = C * V. Conversely, if the shielding electrode is not at the same potential as Vp, it will introduce charge, potentially causing charge non-conservation, making it impossible to sample the capacitance or resulting in an inaccurate capacitance value.
[0064] In some other embodiments of this application, the driving module can also be a third reference voltage source. That is, the shielding electrode is connected to the third reference voltage source under the control of the second clock signal. In this embodiment, the use of voltage sources can be reduced, thereby reducing background noise and environmental impact, reducing power consumption, and improving anti-interference capability.
[0065] For further information on shielding electrodes, please refer to existing technologies; they will not be elaborated upon here.
[0066] Based on the same inventive concept, embodiments of this application also provide a capacitive sensor, which includes the single-ended capacitance sampling circuit, driving module, second reference voltage source and third reference voltage source provided in any of the foregoing embodiments.
[0067] The third reference voltage source is used to provide the third reference voltage and is connected to the fourth switch of the single-ended capacitor sampling circuit.
[0068] The second reference voltage source is used to provide a 0 potential and is connected to the second terminal of the second capacitor of the single-ended capacitor sampling circuit, the first switch, and the third switch.
[0069] The third reference voltage source is connected to the fifth and second switches of the single-ended capacitor sampling circuit.
[0070] Alternatively, the capacitive sensor may further include: a first reference voltage source connected to the fifth switch of the single-ended capacitance sampling circuit, and a second reference voltage source also connected to the second switch; the first reference voltage source is used to provide a first reference voltage, and the voltage provided by the third reference voltage source is equal to half of the first reference voltage.
[0071] In some embodiments, the single-ended capacitance sampling circuit includes a shielding electrode, and the capacitance sensor further includes a driving module connected to the shielding electrode; the driving module is used to provide a driving voltage, which is half of a first reference voltage.
[0072] In some embodiments, a third reference voltage source may also be used as a driving module.
[0073] Capacitive sensors may also include other necessary structures, which can be found in existing technologies and will not be elaborated here.
[0074] Based on the same inventive concept, embodiments of this application also provide an analog-to-digital converter, including the capacitive sensor provided in the foregoing embodiments. Other structures included in the analog-to-digital converter can be referred to existing analog-to-digital converters, and will not be elaborated here.
[0075] In the embodiments of this application, the analog-to-digital converter is one of the following: a successive approximation analog-to-digital converter, a Sigma-delta analog-to-digital converter, or a scaling analog-to-digital converter.
[0076] Successive approximation analog-to-digital converters (ADCs), Sigma-delta ADCs, and scaling ADCs are all low-power ADCs, commonly used in low-power scenarios. Therefore, using the capacitive sensor with a single-ended capacitance sampling circuit provided in the aforementioned embodiments in successive approximation ADCs, Sigma-delta ADCs, and scaling ADCs helps to further reduce power consumption.
[0077] In embodiments of this application, the electronic device can be a wearable device. Wearable devices can be headphones, smart glasses, smartwatches, etc.
[0078] Wearable devices, due to their size limitations, have relatively small battery capacities, thus requiring high power consumption. In the embodiments of this application, incorporating the aforementioned capacitive sensor or analog-to-digital converter into the wearable device helps reduce power consumption and improve its battery life.
[0079] The above embodiments can be combined with each other without conflict to obtain new embodiments, and these combined embodiments are also within the protection scope of this application.
[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0081] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.
Claims
1. A single-ended capacitance sampling circuit, characterized by The single-ended capacitor sampling circuit comprises: a first switched capacitor circuit comprising a to-be-tested capacitor, a first adjustable capacitor, a first switch, a second switch, a third switch, a fifth switch and a sixth switch; a first end of the to-be-tested capacitor is connected to a second end of the first adjustable capacitor through the sixth switch and connected to the third switch; a second end of the to-be-tested capacitor is grounded; a first end of the first adjustable capacitor is connected to the first switch and the fifth switch respectively; and a second end of the first adjustable capacitor is further connected to the second switch; a second switched capacitor circuit comprising a second capacitor and a fourth switch, wherein a first end of the second capacitor is connected to the fourth switch, a second end of the second capacitor is connected to a second reference voltage source, and the second capacitor has a preset capacitance value, and the second reference voltage source is configured to provide a 0 potential; the first switch, the second switch, the third switch and the fourth switch are closed when a first clock signal is high; the fifth switch and the sixth switch are closed when a second clock signal is high; the first clock signal and the second clock signal are non-overlapping clock signals; the first switch and the third switch are connected to a second reference voltage source; the fourth switch is connected to a third reference voltage source; the fifth switch is connected to a first reference voltage source, the second switch is connected to the second reference voltage source, and the third reference voltage source outputs a voltage equal to half of the first reference voltage source; or, the fifth switch and the second switch are both connected to the third reference voltage source.
2. The single-ended capacitive sampling circuit of claim 1, wherein, The single-ended capacitor sampling circuit further comprises a shielding electrode; the shielding electrode wraps the to-be-tested capacitor; the shielding electrode is connected to a driving module through control of the second clock signal, and the driving module is configured to provide a driving voltage.
3. The single-ended capacitive sampling circuit of claim 2, wherein, In the case that the fifth switch is connected to the first reference voltage source, the driving voltage is half of the first reference voltage.
4. The single-ended capacitive sampling circuit of claim 2, wherein, The driving module is the third reference voltage source.
5. A capacitive sensor, characterized by The single-ended capacitor sampling circuit comprises: The single-ended capacitor sampling circuit according to any one of claims 1-4; a third reference voltage source configured to provide a third reference voltage and connected to the fourth switch; a second reference voltage source configured to provide a 0 potential and connected to a second end of the second capacitor, the first switch and the third switch; wherein the third reference voltage source is connected to the fifth switch and the second switch; or, the capacitor sensor further comprises a first reference voltage source connected to the fifth switch, and the second reference voltage source is further connected to the second switch; the first reference voltage source is configured to provide a first reference voltage; and the third reference voltage source outputs a voltage equal to half of the first reference voltage.
6. The capacitive sensor of claim 5, wherein, The single-ended capacitor sampling circuit comprises a shielding electrode, and the capacitor sensor further comprises a driving module connected to the shielding electrode; the driving module is configured to provide a driving voltage, and the driving voltage is half of the first reference voltage.
7. An analog-to-digital converter, characterized by The capacitor sensor comprises: The capacitor sensor according to claim 6.
8. The analog-to-digital converter of claim 7, wherein, The analog-to-digital converter is one of: a successive approximation analog-to-digital converter; a Sigma-delta analog-to-digital converter; A scaling analog-to-digital converter.
9. An electronic device, comprising: The electronic device is a wearable device.
10. The electronic device of claim 9, wherein, The electronic device is a wearable device.