Semiconductor structure and static random access memory unit

Abstract

The utility model provides a semiconductor structure and a static random access memory unit, and the semiconductor structure comprises an active region which comprises a channel layer stack; the metal gate structure is arranged above the channel layer stack; a source / drain structure disposed over the source / drain region of the active region and adjacent to the channel layer stack, and a backside via penetrating from a backside of the active region and extending to contact a channel layer of the channel layer stack. A backside via is electrically connected to the source / drain structure through a channel layer of the channel layer stack and contacts the metal gate structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure and a static random access memory unit. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This shrinkage process typically benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of integrated circuit fabrication and manufacturing.

[0003] In deep submicron integrated circuit technology, Static Random Access Memory (SRAM) devices have become popular storage units for high-speed communications, image processing, and system-on-a-chip (SoC) products. As silicon technology continues to expand from one generation to the next, the manufacture of traditional SRAM devices and / or their manufacturing processes may face limitations. For example, aggressive shrinkage of IC dimensions has led to densely spaced source / drain and gate structures, as well as densely spaced source / drain contacts and gate vias formed thereon. In some SRAM devices, a multilayer interconnect structure is formed above the source / drain contacts and gate vias of the transistors in the memory cells. This multilayer interconnect structure provides metal lines for interconnecting power and signal lines within and between the memory cells of the SRAM device. As device dimensions continue to shrink and transistor spacing becomes denser, some metal lines (e.g., those used for power routing) are formed with reduced dimensions, which can lead to increased parasitic resistance, increased parasitic capacitance, higher process risks, and / or poor connectivity, potentially reducing the speed of the storage device. All these issues present challenges in terms of performance, yield, and cost. Therefore, while existing SRAM devices are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Utility Model Content

[0004] This invention provides a semiconductor structure. The semiconductor structure includes: an active region comprising a channel layer stack; a metal gate structure disposed above the channel layer stack; a source / drain structure disposed above and adjacent to the source / drain region of the active region and adjacent to the channel layer stack; and a back-side via penetrating from the back side of the active region and extending to contact the channel layer of the channel layer stack. The back-side via is electrically connected to the source / drain structure through the channel layer of the channel layer stack and contacts the metal gate structure.

[0005] This utility model provides a semiconductor structure. The semiconductor structure includes a fin-shaped active region, which comprises a semiconductor substrate and a first channel layer stack and a second channel layer stack above the semiconductor substrate, and is longitudinally oriented along a first direction and has ends; a first source / drain structure is disposed above the semiconductor substrate of the fin-shaped active region and between the first and second channel layer stacks; a second source / drain structure is disposed above the semiconductor substrate of the fin-shaped active region and adjacent to the second channel layer stack; a first metal gate structure is disposed above the first channel layer stack; a second metal gate structure is disposed above the second channel layer stack and surrounds each channel layer of the second channel layer stack; and a back-side contact structure is embedded in the semiconductor substrate of the fin-shaped active region, perpendicularly overlapping the ends of the fin-shaped active region, and contacting the bottommost channel layer of the first channel layer stack.

[0006] This utility model provides a static random access memory (SRAM) cell. The SRAM cell includes a first active region and a second active region extending longitudinally along a first direction; a first metal gate structure disposed above the first active region; a second metal gate structure disposed above the first and second active regions; a third metal gate structure disposed above the second active region; a source / drain structure disposed above the first active region and between the first and second metal gate structures; and a back-side via disposed directly below the intersection of the first active region and the first metal gate structure. The first, second, and third metal gate structures extend longitudinally along a second direction perpendicular to the first direction. The first active region includes a first channel member stack and a second channel member stack connected to the source / drain structure. The second metal gate structure surrounds each channel member of the second channel member stack. The back-side via directly contacts the channel members of the first channel member stack and the first metal gate structure. Attached Figure Description

[0007] The best understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A flowchart of a method for forming a semiconductor device according to one or more aspects of this disclosure is shown.

[0009] Figure 2 A fragment layout of an exemplary artifact according to some embodiments of this disclosure is shown.

[0010] Figure 3A , 4A5A, 6A and 7A illustrate one or more aspects of this disclosure in accordance with... Figure 1 During the manufacturing process of the method, along Figure 2 A partial cross-sectional view of an exemplary workpiece with line segment AA.

[0011] Figure 3B , 4B 5B, 6B and 7B illustrate one or more aspects of this disclosure in accordance with... Figure 1 During the manufacturing process of the method, along Figure 2 A partial cross-sectional view of an exemplary workpiece with line segment BB.

[0012] Figure 8 A circuit diagram of a static random access memory (SRAM) cell according to some embodiments of the present disclosure is shown.

[0013] Figure 9A , 10A 11A, 12A, 13A and 14A illustrate one or more aspects of this disclosure along Figure 2 The line segment AA represents a partial cross-sectional view of the workpiece.

[0014] Figure 9B , 10B 11B, 12B, 13B and 14B illustrate one or more aspects of this disclosure along... Figure 2 The line segment BB replaces a partial cross-sectional view of the workpiece. Detailed Implementation

[0015] It is important to understand that the following disclosure provides many different embodiments or examples of implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation of the disclosure. Of course, these are merely examples and are not intended to limit the invention. For example, the following disclosure describes forming a first component on or above a second component, indicating that it includes embodiments where the formed first component and the second component are in direct contact, as well as embodiments where additional components may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. Furthermore, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0016] Furthermore, the following description of a component formed on, connected to, and / or coupled to another component may include embodiments where the components are in direct contact with each other, or embodiments where other components may be formed between these components such that the components are not in direct contact with each other. In addition, to facilitate the description of the relationship between one component and another in embodiments of the present invention, spatially related terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “top,” “bottom,” etc., and their derivative terms (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially related terms are used to cover different orientations of the device containing the components. Furthermore, when numbers or ranges of numbers are described using terms such as “approximately,” “about,” and similar terms, the purpose of these terms is to cover a reasonable range of the described numbers, such as within + / - 10% of the described numbers, or other values ​​that should be understood by those skilled in the art to which this invention pertains. For example, the term “about 5 nm” covers a size range of 4.5 nm to 5.5 nm.

[0017] Static Random Access Memory (SRAM) is an electronic data storage device implemented on semiconductor-based integrated circuits, typically offering faster access times than other types of data storage technologies. SRAM is popular in high-speed communications, image processing, and system-on-a-chip (SoC) applications. A bit can be read or written from an SRAM cell in nanoseconds. An SRAM cell includes transistors with metal interconnect structures above them. These interconnect structures include metal lines for interconnecting the transistor gate and source / drain regions, signal lines for routing bit lines and bit line signals to the cell assembly, and power rails (e.g., metal lines for power supply voltage and power ground) to power the battery assembly. Contacts and corresponding vias electrically connect the battery assembly to the signal lines and power rails. For example, some source / drain regions in the SRAM cell are coupled to the power supply voltage V through source / drain contacts, source / drain vias, and lines in the corresponding metal power rails. DD (also known as V) CC ) and / or electrical ground V SS The source / drain region can refer to the source or drain individually or collectively, depending on the context.

[0018] Traditionally, SRAM devices are built in a stacked manner, with transistors at the lowest layer and interconnect structures (contacts, vias, and metal lines) on top of the transistors to provide connections to them. For example, the interconnect structure may include front-side mating contacts that electrically connect the source / drain structure to the gates of pull-down and pull-up transistors, occupying space above the transistors. Power rails are also above the transistors and can be part of the interconnect structure. As SRAM device sizes continue to shrink, so do power rails. Due to the limited available layout area, and the fact that the metal lines in the power rails are typically formed with reduced dimensions, this inevitably leads to increased voltage drops on the power rails and increased power consumption, which has become a critical issue for further improving SRAM device performance. Therefore, while existing methods in semiconductor manufacturing are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects in the case of SRAM devices.

[0019] Some exemplary embodiments relate to, but are not limited to, multi-gate components. The purpose of introducing multi-gate components is to improve gate control, reduce off-state current, and reduce short-channel effects (SCE) by increasing gate channel coupling. One such multi-gate component that has been introduced is the gate-on-ring (GAA) transistor. The GAA transistor gets its name from its gate structure, which can extend around a channel region (e.g., a nanosheet stack), providing access to channels on all four sides. GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to scale significantly while maintaining gate control and mitigating SCE. The following disclosure will continue to illustrate various embodiments of this disclosure using one or more GAA paradigms. However, it should be understood that this application should not be limited to a particular type of device unless specifically stated otherwise.

[0020] This disclosure provides various embodiments of a semiconductor device. Specifically, this disclosure provides a semiconductor device having a back-side buried contact. This semiconductor device includes a channel layer stack, a gate stack above the channel layer stack, and a source / drain structure contacting the channel layer stack. The back-side buried contact extends from the back side of the semiconductor device to contact the channel layers of the channel layer stack. The back-side buried contact extends through a portion of the gate stack and directly contacts a portion of the gate stack. Thus, the back-side buried contact electrically connects the gate stack and the source / drain structure. In some embodiments, the back-side buried contact extends through multiple channel layers of the channel layer stack. Because the back-side buried contact is located below the channel layer stack, the front-side via density of the semiconductor device can be reduced, thereby providing increased space for front-side conductive structures such as metal lines and vias. The semiconductor device may include static random access memory (SRAM) cells. The channel layer stack may be located at the end of the active region. The back-side buried contact may be located directly below the intersection of the end of the active region and the gate stack.

[0021] The various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 10 for forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. Method 10 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 10. Additional steps may be provided before, during, and after method 10, and some steps may be replaced, eliminated, or moved to achieve some of the steps described in other embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 7B Method 10 is described, and they are based on Figure 1 Partial layout or cross-sectional view of workpiece 200 at different manufacturing stages in an embodiment of method 10. Because workpiece 200 will be manufactured into a semiconductor structure or semiconductor device, workpiece 200 may be referred to herein as semiconductor structure 200 or semiconductor device 200, depending on the context. Figure 8 This is a circuit diagram of SRAM cell 300, which is equivalent to a part of workpiece 200. Figures 9A to 14B These are partial cross-sectional views of the replacement workpieces 400, 500, 600, 700, 800, and 900, respectively. To avoid misunderstanding, the X, Y, and Z directions in the figures are... Figures 2 to 7B and 9A to Figure 14B They are perpendicular to each other. Furthermore, the same reference numerals can denote the same structure throughout the disclosure.

[0022] In some embodiments, the semiconductor device 200 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, storage components, other suitable components, or combinations thereof.

[0023] refer to Figure 1 and Figures 2 to 3B Method 10 includes providing a block 12 for workpiece 200. Figure 2 A partial layout of the workpiece 200 according to various aspects of this disclosure is shown. Figure 3A and Figure 3B The images show workpiece 200 along the line at block 12. Figure 2 Partial cross-sectional views of line segments AA and BB.

[0024] refer to Figure 2 The workpiece 200 includes multiple active regions 212 oriented longitudinally along the X direction and multiple gate stacks 240 oriented longitudinally along the Y direction. The active region of a transistor refers to the area below the gate structure of the transistor where the source region, drain region, and channel region are formed. In this context, the active region is also referred to as an "oxide-bounded (OD) region." Figure 2 As shown, the active region 212 includes active regions 212a, 212b, 212c, 212d, and 212e, which may be referred to individually or collectively as active region 212 depending on the context. In some embodiments, active regions 212a and 212e are n-type active regions and are disposed above P-well regions 207a and 207b, respectively. In an embodiment, active regions 212b, 212c, and 212d are p-type active regions and are disposed above N-well region 205. In an embodiment, active region 212 is a fin structure and is also referred to as fin structure 212. The gate stack 240 includes gate stacks 240a, 240b, 240c, 240d, 240e, 240f, 240g, and 240h, which may be referred to individually or collectively as gate stack 240 depending on the context. Gate stack 240a is disposed above active regions 212a, 212b, and 212d; gate stack 240b is disposed above active region 212a; gate stack 240c is disposed above active region 212e; and gate stack 240d is disposed above active regions 212b, 212d, and 212e. At the intersection of active region 212 and gate stack 240, transistors (e.g., pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and transmission gate transistors PG-1 and PG-2) are formed. In the case of a GAA transistor formed at the intersection of active region 212 and gate stack 240, active region 212 includes elongated nanostructures (also referred to as channel members or channel layers) vertically stacked in a channel region defined in active region 212 and located above semiconductor substrate 204 (described below) of active region 212. Semiconductor substrate 204 protrudes upward beyond substrate 202 (described below). In some embodiments, the portion of the active region 212 not covered by the gate stack 240 serves as a source / drain region. A source / drain structure (described below) is formed within the source / drain region defined in the active region 212 and over the semiconductor substrate 204. The source / drain structure is adjacent to two opposite ends of the nanostructure.

[0025] For reference Figures 3A to 3BAs shown, workpiece 200 includes a substrate 202 on its back side. In some embodiments, substrate 202 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In various embodiments, substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GAAsP, AlInAs, AlGAAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In alternative embodiments, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In embodiments, substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions may be formed in or on substrate 202. Depending on design requirements, the doped regions may be doped with n-type dopants such as phosphorus or arsenic and / or p-type dopants such as boron. The doped regions can be formed directly on the substrate 202, in a p-well structure, an n-well structure, a dual-well structure, or using a bump structure. The doped regions can be formed through dopant atom implantation, in-situ doped epitaxial growth, and / or other suitable techniques.

[0026] In an embodiment, workpiece 200 includes an active region 212 above substrate 202. Each active region 212 includes a semiconductor substrate 204 protruding from substrate 202 and a stack of nanostructures 208 vertically stacked and suspended above semiconductor substrate 204. In an embodiment, semiconductor substrate 204 includes silicon, silicon-germanium, germanium, or other suitable semiconductors and may be doped with n-type or p-type dopants. Active regions 212 can be patterned by any suitable method. For example, active regions 212 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacer walls are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacer walls or axes can then be used as mask assemblies for patterning active regions 212. For example, a mask assembly can be used to etch a trench in a semiconductor layer above or within substrate 202, leaving active region 212 on substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can be implemented using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. For example, a wet etching process can include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method for forming active region 212 can be suitable.

[0027] The nanostructure 208 in the stack connects the two source / drain structures 214 and serves as a channel layer for the GAA transistor. Therefore, the nanostructure 208 can also be referred to as channel layer 208. The nanostructure 208 may comprise a semiconductor material suitable for a transistor channel, such as silicon, silicon germanium, or other semiconductor materials. In various embodiments, the nanostructure 208 may be in the shape of a rod, bar, sheet, or other shape. In embodiments, the nanostructure 208 is initially part of a semiconductor layer stack comprising the nanostructure 208 and other sacrificial semiconductor layers stacked alternately layer by layer. The sacrificial semiconductor layers and the nanostructure 208 comprise different material compositions (e.g., different semiconductor materials, different atomic percentages of components, and / or different weight percentages of components) to achieve etch selectivity. During the gate replacement process that forms the gate stack 240, the sacrificial semiconductor layers are selectively removed, leaving the nanostructure 208 suspended above the semiconductor substrate 204. It is noteworthy that in the illustrated embodiment, three nanostructures 208 are stacked vertically; this is for illustrative purposes only and is not intended to limit the scope beyond the invention. It is understood that any number of nanostructures can be formed, depending on the performance requirements of the device. In some embodiments, the number of vertically stacked nanostructures 208 is between 2 and 10.

[0028] In this embodiment, the workpiece 200 also includes an isolation structure 218 formed around each active region 212 (e.g., Figure 3B As shown), to isolate two adjacent active regions 212. The isolation structure 218 may also be referred to as a shallow trench isolation (STI) structure and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof and / or other suitable materials.

[0029] In some embodiments, the workpiece 200 includes a fin isolation structure 230 above the substrate 202 (e.g., Figure 3A(Middle). The fin isolation structure 230 separates one active region 212 from another active region 212 aligned with it along the X direction. In the depicted embodiment, the fin isolation structure 230 contacts the channel layer 208 and the gate stack 240. In an embodiment, each fin isolation structure 230 includes a first dielectric layer 226 embedded in the semiconductor substrate 204, a second dielectric layer 228 disposed above the first dielectric layer 226, and a third dielectric layer 232 extending into the first dielectric layer 226 and the second dielectric layer 228. The fin isolation structure 230 can be formed using various different processes. In an exemplary process, a fin-cut trench is formed along the Y direction to divide one or more active regions 212 into multiple segments. Isolation dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride are deposited over the workpiece 200, including in grooves and trenches deposited between the active regions 212. The deposited isolation dielectric material is then planarized, for example, by chemical mechanical polishing (CMP), followed by etching back to form a first dielectric layer 226. In some cases, the first dielectric layer 226 may be a shallow trench isolation (STI) structure and may be referred to as such. In various examples, a second dielectric layer 228 may be formed over the first dielectric layer 226, similar to the formation of the first dielectric layer 226 (e.g., depositing an isolation dielectric material and performing a CMP process). In some embodiments, auxiliary trenches are formed in the first dielectric layer 226 and the second dielectric layer 228. Then, similar to the formation of the second dielectric layer 228, a third dielectric layer 232 is formed in the auxiliary trenches. The second dielectric layer 228 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or silicon carbide. The third dielectric layer 232 may include an isolation material, such as silicon oxide, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, degel, aerogel, amorphous fluorinated carbon, parylene, BCB, polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the second dielectric layer 228 and the third dielectric layer 232 comprise multiple layers. In various examples, the fin isolation structure 230 also includes an etch stop layer (ESL, not shown), which may be conformally disposed in the second trench prior to the deposition of the third dielectric layer 232. The ESL may comprise silicon nitride.

[0030] In some embodiments, workpiece 200 includes source / drain structures 214 formed in and / or above the source / drain regions of active region 212, each source / drain structure 214 being configured adjacent to gate stack 240. Source / drain structures 214 may refer independently or collectively to a source or drain, depending on the context. Source / drain structures 214 can be formed using any suitable technique, such as an etching process, followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of active region 212, thereby forming a trench (not shown) in the source / drain regions. A cleaning process may be performed to clean the trench using a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow the source / drain structures 214 in the trenches. Each source / drain structure 214 may be adapted to form a p-type or n-type device. The p-type source / drain structure of a p-type transistor (e.g., pull-up transistors PU-1 and PU-2) may include one or more epitaxial layers of silicon-germanium (epi SiGe) doped with p-type dopants, such as boron, germanium, indium, and / or other p-type dopants. The n-type source / drain structure of an n-type transistor (e.g., transmission gate transistors PG-1, PG-2, pull-down transistors PD-1, PD-2) may include one or more epitaxial layers of silicon (epi Si) or silicon-carbon (epi SiC) doped with n-type dopants such as arsenic, phosphorus, and / or other n-type dopants.

[0031] In some embodiments, workpiece 200 further includes an inner spacer wall 254 disposed between source / drain (S / D) structure 214 and adjacent gate stack 240. In some embodiments, the inner spacer wall 254 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, and other materials, such as suitable materials or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the inner spacer wall 254 comprises a low-k dielectric material, such as that described herein. The inner spacer wall 254 can be formed by deposition and etching processes. For example, after etching the S / D trench and before epitaxially growing the S / D structure 214 from the S / D trench, an etching process can be used to recess the sacrificial layer between adjacent channel layers 208 to vertically form a gap between channel layers 208 and adjacent channel layers 208. Then, one or more dielectric materials (e.g., using CVD or ALD) are deposited to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the inner spacer wall 254.

[0032] In some embodiments, the workpiece includes a gate stack 240 located between two source / drain structures 214, the gate stack 240 being disposed above and surrounding each of the channel layers 208. Reference Figure 3A and Figure 3BThe gate stack 240 may include an interface layer 238 formed on the surface of the channel layer 208 that intersects with the gate stack 240, a high-k dielectric layer 244 formed above the interface layer 238, and a gate electrode layer 242 formed above the high-k dielectric layer 244. A portion of the gate stack 240 and its surrounding structures are... Figures 3A to 3BA magnified view is provided to show details of the layers of the gate stack 240. Interface layer 238 may include silicon dioxide, silicon oxynitride, or other suitable materials. Interface layer 238 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. High-k dielectric layer 244 may include high-k dielectric materials such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, AlSiZO3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). The high-k dielectric layer 244 can be formed by ALD, CVD, metal-organic CVD (MOCVD), PVD, thermal oxidation, and / or other suitable methods. In some embodiments, the gate electrode layer 242 includes a work function layer 246, which is an n-type or p-type work function layer, and a metal filling layer 236 located above the work function layer 246. For example, the n-type work function layer may include a metal with a sufficiently low effective work function, and the p-type work function layer may include a metal with a sufficiently large effective work function. For example, the n-type work function layer may include Ta, aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum titanium oxide (TiAlO), TiAlN, or combinations thereof. For example, the p-type work function layer may include TiN, TaN, WN, or combinations thereof. In some embodiments, the work function layer 246 may include a multilayer structure, such as a first work function layer 246a and a second work function layer 246b (not shown). For example, the first work function layer 246a may include metals such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof, and the second work function layer 246b may include metals such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. In embodiments, the metal filler layer 236 includes aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the metal filler layer 236 disposed above the p-type work function layer (also referred to as metal filler layer 236p) is a p-type metal filler layer. In some embodiments, the metal filler layer 236 disposed above the n-type work function layer (also referred to as metal filler layer 236n) is an n-type metal filler layer. In some other embodiments, the metal filler layers 236p and 236n disposed above the p-type and n-type work function layers have the same material. The gate electrode layer 242 may be formed by CVD, PVD, electroplating, and / or other suitable processes.Because the gate stack 240 includes a high-k dielectric layer and a metal layer, it is also known as a high-k metal gate.

[0033] In some embodiments, the gate stack 240 is formed after fabricating other parts of workpiece 200 (e.g., source / drain structure 214). This process, commonly referred to as a gate replacement process, includes forming a dummy gate structure (not shown) as a placeholder for the gate stack 240, forming the source / drain structure 214, and forming a dielectric structure 262 thereon (described below). The dummy gate structure and the source / drain structure 214 are planarized, for example, by CMP to expose the top surface of the dummy gate structure, the dummy gate structure in the dielectric structure 262 is removed to form a channel region exposing the removed active region 212, the sacrificial layer for channel release is removed, and the gate stack 240 is formed in the trench and around the channel layer 208 to complete the gate replacement process. Although not shown, in some embodiments, the gate stack 240 may be partially recessed, and a dielectric capping layer may be formed on the recessed gate stack 240.

[0034] In an embodiment, the workpiece 200 further includes a gate gap wall 252 disposed on the sidewall of the gate stack 240 (e.g., Figure 3A (As shown). The gate spacer 252 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon carbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon carbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicide, zirconium silicide, etc.), other suitable materials, or combinations thereof. The gate spacer 252 may be a single-layer or multi-layer structure. Notably, the composition of the gate spacer 252 differs from the composition of the surrounding dielectric components (e.g., dielectric structure 262), allowing for etch selectivity between the gate spacer 252 and the surrounding dielectric components during subsequent etching processes. In an embodiment, the gate spacer 252 comprises SiN. The gate spacer 252 can be formed by first depositing a spacer material capping layer over the workpiece 200, and then performing an anisotropic etching process to remove part of the spacer material to form the gate spacer 252.

[0035] In some embodiments, reference Figure 3AThe workpiece 200 includes a dielectric structure 262 disposed above the source / drain structure 214. The dielectric structure 262 may include a contact etch stop layer (CESL) 258 and an interlayer dielectric (ILD) layer 256 formed above the CESL 258. The ILD layer 256 includes a dielectric material such as tetraethyl orthosilicate (TEOS), silicon oxide, a low-k dielectric material, doped silicon oxide such as borosilicate glass (BPSG), phosphosilicate glass (PSG), FSG, borosilicate glass (BSG), other suitable dielectric materials, or combinations thereof. The ILD layer 256 may include a multilayer structure having multiple dielectric materials and may be formed by deposition processes such as CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof. The CESL 258 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, other suitable materials, or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. ILD layer 256 can be deposited after CESL 258.

[0036] In some embodiments, reference Figure 3B Workpiece 200 includes a gate isolation structure 216. Gate isolation structure 216 is a dielectric component that divides one or more long gate stacks into short gate stacks. In an exemplary process, the long gate stack is formed in a first patterning process, and then the long gate stack is cut into short gate stacks (e.g., gate stack 240) in a second patterning process, such that gate stack 240 has the dimensions of a design. Gate isolation structure 216 can be formed by a patterning process to form trenches and a deposition process to fill the trenches with one or more dielectric materials. The patterning process includes a photolithography process and an etching process, and a hard photomask can be used to define the area of ​​gate isolation structure 216. The etching process can include wet etching, dry etching, or a combination thereof to etch conductive material through the long metal gate structure. The etching process can use one or more etchants. CMP can be performed after the deposition process to remove excess material deposited on dielectric structure 262 and gate stack 240 of gate isolation structure 216 and to planarize the top surface of workpiece 200. Gate isolation structure 216 and isolation structure 218 can together provide isolation functionality, such as isolating gate stack 240a with gate stack 240c.

[0037] like Figure 3A and Figure 3BAs shown, workpiece 200 also includes a dielectric structure 266. The dielectric structure 266 is disposed above the fin isolation structure 230, dielectric structure 262, gate stack 240, gate spacer 252, and gate isolation structure 216. In some embodiments, the dielectric structure 266 includes a plurality of dielectric layers 264 and a contact etch stop layer (CESL) 268. The CESL 268 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The dielectric layer 264 may comprise tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BPSG), fluorine-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric layer 264 may be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0038] In some embodiments, reference Figure 2 and Figure 3AThe workpiece 200 also includes a source / drain (S / D) contact 222 above the source / drain structure 214. The S / D contact 222 may extend through a portion of the dielectric structure 262 and dielectric structure 266 (e.g., dielectric layer 264 and CESL 268). In some embodiments, the workpiece 200 also includes a silicide structure 224 located between the source / drain contact 222 and the source / drain structure 214. The silicide structure 224 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In embodiments, the S / D contact 222 may include a conductive barrier layer and a metal filler layer above the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filler layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contact 222. Some S / D contacts 222 (e.g.) Figure 2 (As shown) connects multiple S / D structures 214 and is referred to as long contacts in some embodiments.

[0039] like Figure 2 and Figure 3B As shown, workpiece 200 also includes a gate via 256 connecting the gate stack 240 and the metal line 250 (described below). The gate via 256 can be embedded in a dielectric structure 266, as shown. The gate via 256 can comprise a similar material and can be formed similarly to the S / D contact 222. Reference Figure 2 The workpiece 200 includes a source / drain via 257. The source / drain via 257 may be embedded in a dielectric structure 266 and connect source / drain contacts 222 and metal lines 250 and / or VDD (described below). The source / drain via 257 may comprise a material similar to that of the gate via 256 and may be formed similarly.

[0040] In some embodiments, the workpiece 200 further includes a conductive structure embedded in the dielectric structure 266. In some embodiments, the dielectric structure 266 includes a conductive structure disposed in the dielectric structure 266. Figure 3A and Figure 3BThe diagram shows additional dielectric layers 264 and CESL 268 above the layer shown. The conductive and dielectric structures 266 can be collectively referred to as a multilayer interconnect (MLI). The conductive structures may include metal lines, metal vias, etc. The conductive structures electrically connect various devices and / or components of workpiece 200 (e.g., source / drain regions 214, gate stack 240) such that the various devices and / or components can operate electrically as specified in the design requirements of workpiece 200. The MLI may include one or more interconnect layers. In the depicted embodiment, the MLI includes a metal zero interconnect layer (M0 layer) (e.g., a layer including metal lines 250, BL, VDD, and BLB). Although not shown, the MLI may also include via-interconnect layers (V1 level), metal-interconnect layers (M1 level), ..., via x interconnect layers (Vx level, where x is an integer), and metal x interconnect layers (Mx layer). Each of the M0 level, V1 level, M1 level, ..., Vx level and Mx level may be referred to as a metal level. Metal lines formed on the M0 layer can be referred to as M0 metal lines. Similarly, vias or metal lines formed on the V1, M1, ... Vx, and Mx layers can be referred to as V1 vias, M1 metal lines, ... Vx vias, and Mx metal lines, respectively. This disclosure envisions an MLI with more or fewer interconnect layers and / or layers, for example, a total of N interconnect layers (layers) of the MLI, where N is an integer ranging from 1 to 10. Each layer of the MLI includes conductive layer structures (e.g., metal lines, metal vias) disposed in one or more dielectric layers (e.g., dielectric layer 264) and CESLs (e.g., CESL 268). In some embodiments, conductive structures are simultaneously formed on the same layer (e.g., the M0 layer) of the MLI. In some embodiments, conductive structures at the same level of the MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially flat to each other.

[0041] In an embodiment, the V1 layer includes a V1 via disposed in the dielectric structure 266, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 layer includes M1 metal lines disposed in the dielectric structure 266. The Vx layer includes a Vx via disposed in the dielectric structure 266, wherein the Vx via connects M(x-1) metal lines to the Mx metal line.

[0042] refer to Figure 1 , 2 and Figures 4A to 4B Method 10 includes a block 14 in which a trench 275 is formed from the back side of the substrate 202. Figure 4A and 4B The workpiece 200 is shown along the line at block 14. Figure 2 A partial cross-sectional view of line segments AA and BB. The location of trench 275 (e.g., trenches 275a, 275b, 275c, and 275d, referred to individually or collectively as trench 275 depending on the context) is shown in... Figure 2 It is shown in the dashed square.

[0043] Block 14 includes a thinning process for workpiece 200 from the back side. In some embodiments, after thinning is completed, a semiconductor substrate 204, a first dielectric layer 226, and an isolation structure 218 are exposed from the back side. The thinning process may include a mechanical polishing process and / or a chemical thinning process. During the mechanical polishing process, a significant amount of substrate material may be removed from the substrate 202. Then, the chemical thinning process may apply etching chemicals to the back side of the substrate 202 to further thin the substrate 202.

[0044] An etch stop layer 278 is formed above the back side of the workpiece 200. The etch stop layer 278 may include silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, or combinations thereof. The thickness of the etch stop layer 278 may be in the range of about 5 nm to about 15 nm.

[0045] In some embodiments, block 14 includes forming trench 275. Forming trench 275 may include forming a hard mask layer (not shown) below etch stop layer 278 and performing photolithographic patterning and etching processes to pattern the hard mask layer. The hard mask layer may include suitable materials such as SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, etc. The patterning of the hard mask layer occurs at certain intersections of gate stack 240 and active region 212 (e.g., Figure 2 An opening is formed directly below the dashed square (as depicted in the image). As in the illustrated embodiment, the intersection is located at the ends of active regions 212b, 212c, and 212d. Figure 4AAs shown, the end A or B of the active region 212 may be adjacent to the fin isolation structure 230 and may include a stack of channel layers 208 such that the stack of channel layers 208 is disposed between adjacent source / drain structures 214 and fin isolation structures 230. In some embodiments, such as end B, a complete gate stack 240 having a width G1 along the X direction is disposed above end B, and the end 206b of the active region 212 is aligned with the end 209b of the gate stack 240. In some embodiments, such as end A, an incomplete gate stack 240 with a width G1' along the X direction is disposed above end A, and the end 206a of the active region 212 is aligned with the end 209a of the gate stack 240. G1' may be about 0.5 to about 1 times G1. In some other embodiments not shown, the end 206b extends beyond end 209b along the X direction by an amount equal to or less than G1. For ease of description, the channel layers 208 at the intersection are labeled 208-1, 208-2, and 208-3 from bottom to top. Please note that the channel layer 208 at the ends of active regions 212b, 212c, and 212d is not part of the transistors (e.g., pull-up transistors PU-1, PU-2, pull-down transistors PD-1, PD-2, and transmission gate transistors PG-1, PG-2) of workpiece 200. Therefore, forming the trench 275 at the ends and subsequent processes will not damage the functional channel layer 208 of the transistors. Then, a hard mask layer is used as a mask to perform one or more etching processes to form the trench 275. The one or more etching processes may include multiple steps and involve various etching fluids. The one or more etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, dry etching processes can be implemented using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. For example, wet etching processes can include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; solutions containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants.

[0046] Trench 275 may extend through etch stop layer 278 and semiconductor substrate 204. In embodiments, each trench 275 extends to contact channel layer 208 (e.g., channel layer 208-1). In embodiments, trench 275 exposes the bottom surface of channel layer 208. In some embodiments, trench 275 extends into channel layer 208 (e.g., channel layer 208-1) and further exposes the sidewall surfaces of channel layer 208. In the depicted embodiments, channel layer 208 is the bottommost channel layer 208-1. A portion of the gate stack 240 beneath channel layer 208 is also extended through by trench 275. In some embodiments (e.g., trench 275a), trench 275 is spaced apart from inner spacer wall 254 and fin isolation structure 230. In some other embodiments (e.g., trench 275b), trench 275 exposes inner spacer wall 254 and / or fin isolation structure 230. The trench 275 does not expose or extend into the adjacent source / drain structure 214. In other words, damage to the source / drain structure 214 is avoided during the formation of the trench 275, which can benefit the operation of the workpiece 200.

[0047] refer to Figure 4A In some embodiments, trench 275 has a width W1 along the X direction. Each gate stack 240 includes an upper portion situated above the stack of channel layers 208 and inner layers interleaved with channel layers 208. The upper portion has a width G1 along the X direction, and each lower layer has a width (e.g., g1, g2, g3) along the X direction. In embodiments, the ratio of W1 to G1 (e.g., W1 / G1) is about 0.5 to about 1. The ratio of W1 to the width of the inner layers (e.g., W1 / g1, W1 / g2, W1 / g3) is about 0.5 to about 1. These ranges are not arbitrary. If one of these ratios is greater than about 1, a portion of the inner spacer wall 254 adjacent to trench 275 may be removed during the formation of trench 275, thus reducing the isolation provided by the inner spacer wall 254, which could result in an electrical short circuit between adjacent source / drain structures 214 and the back-side buried contacts to be formed in trench 275. If one of the ratios is less than about 0.5, the resistance of the back-side embedded contact formed in the trench 275 may be too high, causing excessive energy waste during the operation of the workpiece 200.

[0048] refer to Figure 4BIn some embodiments, trench 275 has a width W2 along the Y direction. Channel layer 208 may have a width W3 along the Y direction. In embodiments, the ratio of W2 to W3 (W2 / W3) is from about 0.5 to about 2. If the ratio is greater than about 2, trench 275 may extend into adjacent gate isolation structures 216 and / or may be too close to adjacent stacks of channel layers 208 of active regions 212b or 212e, and this may unnecessarily increase the footprint of the back-side buried contacts and the associated costs. If the ratio is less than about 0.5, the resistance of the back-side buried contacts to be formed in trench 275 may be too high, resulting in excessive energy waste during operation of workpiece 200.

[0049] refer to Figure 1 and Figures 5A to 5B Method 10 includes a block 16, wherein a barrier layer 284 is formed on a portion of the sidewall of the trench 275. Figure 5A and Figure 5B The images show workpiece 200 along the line at block 16. Figure 2 A partial cross-sectional view of line segments AA and BB. This step is optional.

[0050] Barrier layer 284 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, barrier layer 284 includes silicon nitride. For example, barrier layer 284 may be deposited conformally over the back side of workpiece 200 using a blanket deposition process employing a process such as CVD, SACVD, ALD, PVD, or other suitable processes. In the illustrated embodiment, an etch-back (e.g., anisotropic) process is performed after depositing the dielectric material layer to remove the dielectric material layer from the top portions of the horizontal surface and sidewall surfaces of trench 275. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. In some embodiments, the etch-back process includes a directional etching process (e.g., tilted plasma etching), wherein an ion beam may be directed at an angle relative to the Z-direction to the surface of workpiece 200. In this embodiment, after the etch-back process, the surface of the channel layer 208-1 and the sidewall surfaces of the inner layers of the gate stack 240 below the channel layer 208-1 are exposed. A dielectric layer can be retained on the sidewalls of the semiconductor substrate 204 and the etch stop layer 278 as a barrier layer 284. The resulting structure after the etch-back process is as follows... Figures 5A to 5BAs shown. Barrier layer 284 provides electrical isolation between back-side metal filler 286 (described below) and semiconductor substrate 204. In some embodiments, the deposited barrier layer 284 is first processed to alter its composition. In this case, the processed portion of barrier layer 284 is retained during an etch-back process, and the unprocessed portion is removed through the etch-back process. In a further embodiment, barrier layer 284 comprises silicon oxide, and the processing includes tilted ion implantation using suitable ions (e.g., nitrogen ions) such that nitrogen is introduced into the bottom portion of barrier layer 284. Portions of barrier layer 284 are selectively removed through the etch-back process using a suitable etchant such as phosphorous acid.

[0051] refer to Figure 1 and Figures 6A to 6B Method 10 includes a block 18, wherein a silicide structure 282 is formed on the top portion of the surface of the trench 275. Figure 6A and Figure 6B The images show workpiece 200 along block 18. Figure 2 A partial cross-sectional view of line segments AA and BB. This step is optional.

[0052] Forming the silicide structure 282 may include depositing one or more metals into the trench 275 using CVD, PVD, ALD, or other suitable methods; performing an annealing process on the workpiece 200 to induce a reaction between the one or more metals and the exposed channel layer 208 to produce the silicide structure 282; and removing unreacted portions of the one or more metals, leaving the silicide structure 282 in the trench 275. In such embodiments, the silicide structure 282 is formed on the exposed surfaces of the channel layer 208 (e.g., the exposed bottom surface and the exposed sidewall surfaces), but not on the exposed sidewall surfaces of the inner layers of the gate stack 240. In the depicted embodiment, the silicide structure 282 is formed on the top surface and a portion of the sidewall of the trench 275. In the depicted embodiment, the silicide structure 282 is continuous. The silicide structure 282 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. In some embodiments, the silicide structure 282 includes TiSi. The silicide structure 282 is formed between the channel layer 208 and the back-side metal filler 286 (described below) to further reduce contact resistance.

[0053] refer to Figure 1 and Figures 7A to 7BMethod 10 includes a block 20, wherein a back-side metal filler 286 is formed in a groove 275. Figure 7A and Figure 7B The workpiece 200 is shown along the block 20. Figure 2 Partial cross-sectional views of line segments AA and BB.

[0054] The back-side metal filler 286 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the back-side metal filler 286 includes performing a planarization operation, such as a CMP process, to remove excess conductive material from the back-side metal filler 286. An etch stop layer 278 may be used as a stop layer for the planarization operation, such that the planarization operation also removes the hard mask layer.

[0055] The structure obtained after the flattening operation is as follows Figures 7A to 7B As shown. The silicide structure 282, the barrier layer 284, and the back-side metal filler 286 together form the back-side embedded contact 280. The back-side embedded contact 280 substantially tracks the shape and size of the trench 275. In an embodiment, the back-side embedded contact 280 is electrically connected to a channel layer 208 (e.g., channel layer 208-1), which is connected to an adjacent source / drain structure 214. Therefore, the back-side embedded contact 280 is electrically connected to the adjacent source / drain structure 214 through the channel layer 208-1, with a conductive path as shown. Figure 7A As indicated by arrow 270. In the depicted embodiment, the back-side metal filler 286 directly contacts the sidewall of the inner layer of the gate stack 240. Therefore, the back-side buried contact 280 is electrically connected to the gate stack 240. The conductive path between the gate stack 240 and the channel layer 208-1 is... Figure 7B This is shown as arrow 271. Therefore, the gate stack 240 and the adjacent source / drain structure 214 are electrically connected via the back-side buried contact 280 and the channel layer 208. In some embodiments, the back-side buried contact 280 serves as a local interconnect component and is not connected to a back-side metal line or back-side via. The back-side metal filler 286 may be spaced apart from the adjacent source / drain structure at least through the inner spacer wall 254. In embodiments, the back-side buried contact 280 directly contacts the inner spacer wall 254 and / or the fin isolation structure 230.

[0056] In some embodiments, return to reference Figure 2Metal lines BL, VDD, and BLB extend longitudinally in the X direction and are spaced apart along the Y direction. The spacing between metal lines BL and VDD can be the same as the spacing between metal lines VDD and BLB. Because the back-side buried contact 280 is disposed below the transistor, and no front-side mating contact is required to connect the gate stack 240 and the adjacent source / drain structure 214, the available space in the M0 layer is increased. Therefore, the M0 metal lines BL, VDD, and BLB can have a width that increases along the Y direction. In some embodiments, metal line VDD has a rectangular shape in top view, such as... Figure 2 As shown, the metal lines BL, VDD, and BLB have increasing widths along the Y direction to reduce resistance. In this embodiment, the widths of the metal lines BL, VDD, and BLB along the Y direction are D1, D2, and D3, respectively. The ratio of D2 / D1 is about 0.5 to about 2. The ratio of D2 / D3 is about 0.5 to about 2. If the ratio of D2 / D1 or D2 / D3 is greater than about 2, the metal line VDD may be too close to the adjacent metal line BL or metal line BLB, and therefore the isolation between them may be too small. If the ratio is less than about 0.5, the resistance of the metal line VDD may be too large, resulting in too much voltage drop and / or energy waste during operation of the workpiece 200.

[0057] Figure 8 This is a circuit diagram of an exemplary SRAM cell 300, which is equivalent to Figure 2 The portion of workpiece 200 within the dashed rectangle on the left. SRAM cell 300 can be implemented as a memory cell. SRAM arrays according to various aspects of this disclosure (e.g., Figure 2 (The 1×2 SRAM array in the example). In the illustrated embodiment, SRAM cell 300 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, SRAM cell 300 may be other types of memory cells, such as dual-port memory cells or memory cells with more than six transistors. For clarity, Figure 8 The invention has been simplified to better understand the inventive concept disclosed herein. Additional structures can be added to the single-port SRAM cell 300, and some of the structures described below can be replaced, modified, or eliminated in other embodiments of the single-port SRAM cell 300.

[0058] An exemplary SRAM cell 300 includes six transistors: a transfer gate transistor PG-1, a transfer gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the transfer gate transistors PG-1 and PG-2 provide access to a storage portion of the SRAM cell 300, which includes a cross-coupled inverter pair of inverters 392 and 394. Inverter 392 includes pull-up transistor PU-1 and pull-down transistor PD-1, and inverter 394 includes pull-up transistor PU-2 and pull-down transistor PD-2. As described above, pull-up transistors PU-1 and PU-2 are configured as p-type GAA transistors, and pull-down transistors PD-1 and PD-2 are configured as n-type GAA transistors.

[0059] The gate of pull-up transistor PU-1 is located between the source and the power supply voltage (V). DD The pull-down transistor PD-1 is electrically coupled between the source and the first common drain (CD1), and its gate is located between the source and the power supply voltage (V). SS Electrical coupling (which can be electrical ground) and the first common drain. The gate of the pull-up transistor PU-2 is located between the source (and the power supply voltage (V)). DD The pull-down transistor PD-2 is electrically coupled between the source and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is located between the source and the power supply voltage (V). SS Electrically coupled between the first common drain (CD1) and the second common drain (CD2). In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in physical form, while the second common drain (CD2) is a storage node (SNB) that stores data in complementary form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are connected through a back-side embedded contact 280 (e.g., Figure 7A The back-side embedded contact 280 is formed in Figure 2 The trench 275a) is coupled to the second common drain (CD2). The gates of the pull-up transistor PU-2 and the pull-down transistor PD-2 are connected through another back-side embedded contact 280 (e.g., formed in...). Figure 2The back-side embedded contact 280 of trench 275c is electrically coupled to the first common drain (CD1). The gate of transfer gate transistor PG-1 is located between its source (electrically coupled to bit line BL) and its drain, which is electrically coupled to the first common drain (CD1). The gate of transfer gate transistor PG-2 is located between its source (electrically coupled to complementary bit line BLB) and its drain, which is electrically coupled to the second common drain (CD2). The gates of transfer gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some implementations, transfer gate transistors PG-1 and PG-2 provide access to storage nodes SN and SNB during read and / or write operations. For example, transfer gate transistors PG-1 and PG-2 couple storage nodes SN and SNB to bit lines BL and BLB, respectively, through the word line WL in response to voltages applied to their gates.

[0060] The gate of the transmission gate transistor PG-1 is formed by gate stack 240b, the gate of the pull-down transistor PD-1 is formed by gate stack 240a, and the gate of the pull-up transistor PU-1 is formed by gate stack 240a. The gate of the pull-up transistor PU-2 is formed by gate stack 240d, the gate of the pull-down transistor PD-2 is formed by gate stack 240d, and the transmission gate transistor PG-2 is formed by gate stack 240c. Bit lines BL and BLB can each contain... Figure 7B The metal wires BL and BLB. Power supply voltage (V) DD It can be done through Figure 7B The metal wire VDD in the middle is provided.

[0061] Figures 9A to 9B The replacement workpieces 400 along each are shown. Figure 2 Partial cross-sectional views of line segments AA and BB. The difference between workpiece 400 and workpiece 200 is that the silicide structure 282 is formed by depositing a silicide layer in trench 275. In some embodiments, the silicide layer is conformally deposited in the bottom surface of trench 275 and etch stop layer 278. During operation in block 18. In such an embodiment, the operation in block 18 further includes performing an etch-back process to remove the silicide layer from the bottom portion of the sidewalls of trench 275 and the bottom surface of etch stop layer 278, with the remaining portion of the silicide layer forming the silicide structure 282 above the sidewall surfaces of the inner layers of gate stack 240 and the surface of channel layer 208-1, as shown in the figure. Figures 9A to 9B As shown. In some embodiments, a silicide structure 282 is disposed between the back-side metal filler 286 and the channel layer 208-1 and the inner layer of the gate stack 240. The silicide structure 282 may include components that are... Figures 7A to 7B The workpiece 200 has a silicide structure similar to that of 282.

[0062] Figures 10A to 10B The replacement workpieces 500 along each are shown. Figure 2 Partial cross-sectional views of line segments AA and BB. Differences between workpiece 500 and workpiece 200 include the absence of a silicide structure 282 or a barrier layer 284. In such embodiments, blocks 16 and 18 are omitted. In the depicted embodiment, the backside metal fill 286 directly contacts the channel layer 208-1, the inner layer of the gate stack 240, the semiconductor substrate 204, and the etch stop layer 278. In embodiments, the backside metal fill 286 directly contacts the inner spacer wall 254 and / or the fin isolation structure 230. In some other embodiments not depicted, blocks 16 or 18 are omitted. In such embodiments, only one of the silicide structure 282 and the barrier layer 284 is incorporated into the backside embedded contact 280.

[0063] Figures 11A to 11B The replacement workpiece 600 is shown respectively. Figure 2 Partial cross-sectional views of line segments AA and BB. The difference between workpiece 600 and workpiece 200 includes the extension of the back-side buried contact 280 to the channel layer 208-2. In such an embodiment, compared to workpiece 200, the back-side buried contact 280 also extends from the bottom through the channel layer 208-1 and the second inner layer of the gate stack 240, and extends to contact the channel layer 208-2. In the depicted embodiment, the silicide structure 282 is formed similarly to the silicide structure 282 of workpiece 200, and is disposed on the sidewalls and bottom surface of the channel layer 208-2 and on the sidewalls of the channel layer 208-1. The silicide structure 282 is not disposed on the sidewalls of the inner layer of the gate stack 240. Therefore, the silicide structure 282 is discontinuous. Arrow 272 shows the conductive path between the source / drain structure 214 and the back-side buried contact 280. Arrow 273 shows the conductive path between channel layer 208-2 and gate stack 240. It should be understood that channel layer 208-1 can also be electrically connected to gate stack 240 through back-side buried contact 280. For ease of reading the diagram, the conductive path of back-side buried contact 280 is not shown.

[0064] Figures 12A to 12B The replacement workpiece 700 is shown respectively. Figure 2 Partial cross-sectional views of line segments AA and BB. The difference between workpiece 700 and workpiece 600 includes the deposition of a silicide layer in trench 275 to form silicide structure 282, and related to... Figures 9A to 9B Similar to the description. In this embodiment, the silicide structure 282 is continuous. The silicide structure 282 may be disposed between the back-side metal filler 286 and the first and second inner layers of the gate stack 240 from the bottom, and between the back-side metal filler 286 and the channel layers 208-1 and 208-2.

[0065] Figures 13A to 13B The replacement workpiece 800 is shown respectively. Figure 2 Partial cross-sectional views of line segments AA and BB. The difference between workpiece 800 and workpiece 600 includes the extension of the back-side buried contact 280 to the channel layer 208-3. In such an embodiment, compared to workpiece 600, the back-side buried contact 280 also extends from the bottom through the channel layer 208-2 and the third inner layer of the gate stack 240, and extends to contact the channel layer 208-3. In the depicted embodiment, the silicide structure 282 is formed similarly to the silicide structure 282 of workpiece 600, and is disposed on the sidewalls and bottom surface of the channel layer 208-3 and on the sidewalls of the channel layers 208-1 and 208-2. The silicide structure 282 is not disposed on the sidewalls of the inner layer of the gate stack 240. Therefore, the silicide structure 282 is discontinuous. Arrow 274 shows the conductive path between the source / drain structure 214 and the back-side buried contact 280. Arrow 275 shows the conductive path between channel layer 208-3 and gate stack 240. It should be understood that channel layers 208-1 and 208-2 can also be electrically connected to gate stack 240 via back-side embedded contacts 280, but their conductive paths are not shown for ease of reading the diagram.

[0066] Figures 14A to 14B The replacement workpiece 900 is shown respectively. Figure 2 Partial cross-sectional views of line segments AA and BB. The difference between workpiece 900 and workpiece 800 is that silicide structure 282 is formed by depositing a silicide layer in trench 275, as shown in the reference. Figures 9A to 9B Similar to the description. In this embodiment, the silicide structure 282 is continuous. The silicide structure 282 may be disposed between the back-side metal filler 286 and the first inner layer, second inner layer and third inner layer of the gate stack 240 from the bottom, and between the back-side metal filler 286 and the channel layers 208-1, 208-2 and 208-3.

[0067] It should be understood that, as described above, more channel layers 208 may be included in the stack of channel layers 208. The back-side embedded contact 280 may extend through multiple (e.g., 2, 3, 4, 5, 6, 7, 8, 9, 10) channel layers 208 in the stack.

[0068] While not intended to be limiting, one or more embodiments of this disclosure offer numerous benefits for semiconductor devices and their fabrication. For example, this disclosure reduces the front-side conductive structure density and provides greater freedom for M0-level designs by having back-side buried contacts. Therefore, M0 metal lines (e.g., metal line VDD) can have increased width and reduced resistance, which can reduce voltage drop and wasted energy during semiconductor device operation. The back-side buried contacts are spaced apart from adjacent source / drain structures, thus eliminating source / drain structure losses and potentially improving semiconductor device performance. Furthermore, the embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes. For example, the back-side buried contacts can be formed together with other back-side vias in the semiconductor device (e.g., back-side vias beneath source / drain structures).

[0069] In one exemplary aspect, this disclosure relates to a semiconductor structure. This semiconductor structure includes: an active region comprising a channel layer stack; a metal gate structure disposed above the channel layer stack; a source / drain structure disposed above and adjacent to the source / drain region of the active region and the channel layer stack; and a back-side via penetrating from the back side of the active region and extending to contact the channel layer of the channel layer stack. The back-side via is electrically connected to the source / drain structure through the channel layer of the channel layer stack and contacts the metal gate structure.

[0070] In some embodiments, the back-side via includes a metal filler layer and a silicide layer disposed between the metal filler layer and the channel layers of the channel layer stack. In some embodiments, the silicide layer is also disposed between the metal filler layer and the metal gate structure. In some embodiments, the back-side via penetrates multiple channel layers of the channel layer stack, and the silicide layer includes discontinuous segments and is disposed on the sidewalls of the multiple channel layers of the channel layer stack. In some embodiments, the back-side via includes a metal filler layer and a dielectric barrier layer disposed on at least a portion of the sidewalls of the metal filler layer. In some embodiments, the channel layer of the channel layer stack is the bottommost channel layer of the channel layer stack. In some embodiments, the back-side via penetrates multiple channel layers of the channel layer stack. In some embodiments, the channel layer of the channel layer stack is the topmost channel layer of the channel layer stack, and the back-side via is electrically connected to each channel layer of the channel layer stack. In some embodiments, the semiconductor structure further includes an inner spacer wall disposed between the source / drain structure and the back-side via. In some embodiments, the channel layer stack is disposed at the end of the active region.

[0071] In another exemplary aspect, this disclosure relates to a semiconductor structure. This semiconductor structure includes a finned active region comprising a semiconductor substrate and a first channel layer stack and a second channel layer stack above the semiconductor substrate, and is longitudinally oriented along a first direction and has ends; a first source / drain structure disposed above the semiconductor substrate of the finned active region and between the first and second channel layer stacks; a second source / drain structure disposed above the semiconductor substrate of the finned active region and adjacent to the second channel layer stack; a first metal gate structure disposed above the first channel layer stack; a second metal gate structure disposed above the second channel layer stack and surrounding each channel layer of the second channel layer stack; and a back-side contact structure embedded in the semiconductor substrate of the finned active region, perpendicularly overlapping the ends of the finned active region, and contacting the bottommost channel layer of the first channel layer stack.

[0072] In some embodiments, the back-side contact structure includes a silicide layer disposed on the sidewall of the bottom channel layer of the first channel layer stack. In some embodiments, the silicide layer has a discontinuous structure having multiple segments that contact and align with the channel layers of the first channel layer stack. In some embodiments, the back-side contact structure penetrates the portion of the first metal gate structure located below the first channel layer stack. In some embodiments, the semiconductor structure further includes an inner spacer wall disposed between the back-side contact structure and the first source / drain structure. In some embodiments, the first source / drain structure and the first metal gate structure are electrically connected through the back-side contact structure and the bottom channel layer of the first channel layer stack.

[0073] In another exemplary aspect, this disclosure relates to a static random access memory (SRAM) cell. The SRAM cell includes a first active region and a second active region extending longitudinally along a first direction, a first metal gate structure disposed above the first active region, a second metal gate structure disposed above the first and second active regions, a third metal gate structure disposed above the second active region, a source / drain structure disposed above the first active region and between the first and second metal gate structures, and a back-side via disposed directly below the intersection of the first active region and the first metal gate structure. The first, second, and third metal gate structures extend longitudinally along a second direction perpendicular to the first direction. The first active region includes a first channel member stack and a second channel member stack connected to the source / drain structure. The second metal gate structure surrounds each channel member of the second channel member stack. The back-side via directly contacts the channel members of the first channel member stack and the first metal gate structure.

[0074] In some embodiments, the back-side via is directly disposed below the end of the first active region. In some embodiments, the back-side via includes a silicide layer disposed on the sidewall of the channel member of the first channel member stack. In some embodiments, the static random access memory (SRAM) cell further includes a spacer layer disposed between the back-side via and the source / drain structure.

[0075] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, comprises: an active region comprising a channel layer stack; a metal gate structure disposed over the channel layer stack; a source / drain structure disposed over a source / drain region of the active region and adjacent to the channel layer stack; and a backside via penetrating from a backside of the active region and extending to contact a channel layer of the channel layer stack, wherein the backside via is electrically connected to the source / drain structure through the channel layer of the channel layer stack and contacts the metal gate structure. The backside via comprises:

2. The semiconductor structure of claim 1, wherein, a metal fill layer; and a silicide layer disposed between the metal fill layer and the channel layer of the channel layer stack.

3. The semiconductor structure of claim 2, wherein: the backside via penetrates a plurality of channel layers of the channel layer stack, the silicide layer comprises discontinuous segments and is disposed on sidewalls of the plurality of channel layers of the channel layer stack. The backside via comprises:

4. The semiconductor structure of claim 1, wherein, a metal fill layer; and a dielectric barrier layer disposed on at least a portion of sidewalls of the metal fill layer. The backside via penetrates a plurality of channel layers of the channel layer stack.

5. The semiconductor structure of claim 1, wherein, 6. The semiconductor structure of claim 5, wherein: the channel layer of the channel layer stack is a topmost channel layer of the channel layer stack, and the backside via is electrically connected to each channel layer of the channel layer stack. comprises:

7. A semiconductor structure, characterized by a fin-shaped active region comprising a semiconductor substrate and a first channel layer stack and a second channel layer stack over the semiconductor substrate and the fin-shaped active region is longitudinally oriented along a first direction and has an end portion; a first source / drain structure disposed over the semiconductor substrate of the fin-shaped active region and between the first channel layer stack and the second channel layer stack; a second source / drain structure disposed over the semiconductor substrate of the fin-shaped active region and adjacent to the second channel layer stack; a first metal gate structure disposed over the first channel layer stack; a second metal gate structure disposed over the second channel layer stack and wrapping each channel layer of the second channel layer stack; and a backside contact structure embedded in the semiconductor substrate of the fin-shaped active region, vertically overlapping the end portion of the fin-shaped active region, and contacting a bottommost channel layer of the first channel layer stack. further comprising an inner spacer disposed between the backside contact structure and the first source / drain structure. comprises:

8. The semiconductor structure of claim 7, wherein, a first active region and a second active region extending longitudinally along a first direction; 9. A static random access memory cell, comprising: a first metal gate structure disposed over the first active region; a second metal gate structure disposed over the first active region and the second active region; a third metal gate structure disposed over the second active region; a source / drain structure disposed between the first metal gate structure and the second metal gate structure over the first active region; and a backside via disposed directly under an intersection of the first active region and the first metal gate structure, ​ ​ ​ wherein the first metal gate structure, the second metal gate structure, and the third metal gate structure extend longitudinally along a second direction perpendicular to the first direction, wherein the first active region includes a first channel member stack and a second channel member stack connected to the source / drain structure, wherein the second metal gate structure encircles each channel member of the second channel member stack, and wherein the backside via directly contacts a channel member of the first channel member stack and the first metal gate structure.

10. The SRAM cell of claim 9, wherein, the backside via is disposed directly below an end of the first active region. the backside via is disposed directly below an end of the first active region.

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