Silicon carbide MOSFET capable of reducing body diode voltage drop

Abstract

The utility model provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) capable of reducing the voltage drop of a body diode. The lower side surface of an epitaxial layer is connected to the upper side surface of a silicon carbide substrate; a first groove is formed in the epitaxial layer; the P-type base region is arranged in the first groove, and a second groove is formed in the P-type base region; the N + source region is arranged in the second groove; the P + source region is arranged in the second groove, and the outer side surface of the P + source region is connected to the inner side surface of the N + source region; the lower side surface of the gate oxide layer is connected to the N + source region, the P-type base region and the epitaxial layer; the lower side surface of the polycrystalline silicon electrode layer is connected to the upper side surface of the gate oxide layer; the lower side surface of the first contact metal layer is connected to the N + source region; the lower side surface of the second contact metal layer is connected to the P + source region, and the second contact metal layer is connected to the first contact metal layer; the metal work function of the first contact metal layer is smaller than that of the second contact metal layer; and on the basis of reducing the on resistance, the forward voltage drop of the body diode is reduced, and the loss of the MOSFET when being applied in a circuit is also reduced.

Description

Technical Field

[0001] This utility model relates to a silicon carbide MOSFET that reduces the body diode voltage drop. Background Technology

[0002] The body diode of a silicon carbide MOSFET is a PiN diode, and the ohmic contact between its source metal and the P-region directly affects the forward voltage drop of the body diode. Current technology uses a single metal material to form ohmic contacts with both the N-type and P-type regions. However, since a single metal cannot simultaneously form an anti-blocking layer with both N-type and P-type semiconductors, thus failing to achieve an ideal ohmic contact, a metal that more easily forms an ohmic contact with the N-type semiconductor is typically chosen to reduce the MOSFET's on-resistance, thereby lowering the source contact resistance. This results in an imperfect ohmic contact between the source metal and the P-type region, increasing the anode contact resistance of the body diode, which in turn increases the forward voltage drop and leads to higher losses in circuit applications. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a silicon carbide MOSFET that reduces the body diode voltage drop. By reducing the on-resistance of the MOSFET, the forward voltage drop of the body diode is reduced, and the loss of the MOSFET when it is used in the circuit is also reduced.

[0004] This invention is achieved as follows: a silicon carbide MOSFET for reducing body diode voltage drop, comprising:

[0005] silicon carbide substrate;

[0006] An epitaxial layer, the lower side of which is connected to the upper side of the silicon carbide substrate; a first groove is provided in the epitaxial layer;

[0007] A P-type base region is provided in the first groove, and a second groove is provided in the P-type base region;

[0008] The N+ source region is disposed within the second groove;

[0009] The P+ source region is disposed in the second groove, and the outer side of the P+ source region is connected to the inner side of the N+ source region.

[0010] A gate oxide layer, the lower side of which is connected to the N+ source region, the P-type base region, and the epitaxial layer;

[0011] A polycrystalline silicon electrode layer, wherein the lower side of the polycrystalline silicon electrode layer is connected to the upper side of the gate oxide layer;

[0012] A first contact metal layer, the lower side of which is connected to the N+ source region;

[0013] And a second contact metal layer, the lower side of which is connected to the P+ source region, and the second contact metal layer is connected to the first contact metal layer; the work function of the first contact metal layer is less than the work function of the second contact metal layer.

[0014] The advantages of this invention are as follows: This invention provides a silicon carbide MOSFET that reduces the body diode voltage drop, allowing the metal to form an antiblocking layer with both the N+ and P+ source regions. After depositing the metal, a high-temperature annealing process is used to form an alloy between the metal and the semiconductor, thereby forming an ohmic contact. This reduces the forward voltage drop of the body diode while decreasing the on-resistance of the MOSFET, and also reduces the losses of the MOSFET when used in circuits. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0016] Figure 1 This is a cell cross-sectional view of a silicon carbide MOSFET for reducing body diode voltage drop according to this utility model. Detailed Implementation

[0017] like Figure 1 As shown, this utility model discloses a silicon carbide MOSFET for reducing body diode voltage drop, comprising:

[0018] Silicon carbide substrate 201;

[0019] Epitaxial layer 202, the lower side of which is connected to the upper side of the silicon carbide substrate 201; a first groove (not shown in the figure) is provided in the epitaxial layer 202;

[0020] P-type base region 203, wherein the P-type base region 203 is disposed in the first groove, and a second groove (not shown in the figure) is provided in the P-type base region 203;

[0021] N+ source region 204, wherein the N+ source region 204 is disposed in the second groove;

[0022] P+ source region 205, wherein the P+ source region 205 is disposed in the second groove, and the outer side of the P+ source region 205 is connected to the inner side of the N+ source region 204;

[0023] Gate oxide layer 206, the lower side of which is connected to the N+ source region 204, the P-type base region 203 and the epitaxial layer 202;

[0024] A polycrystalline silicon electrode layer 207, the lower side of which is connected to the upper side of the gate oxide layer 206;

[0025] A gate-source isolation layer 208 is provided, which encloses the polysilicon electrode layer 207, and the lower side of the gate-source isolation layer 208 is connected to the N+ source region 204.

[0026] A first contact metal layer 209, the lower side of the first contact metal layer 209 being connected to the N+ source region 204;

[0027] And, a second contact metal layer 210, the lower side of the second contact metal layer 210 being connected to the P+ source region 204, the second contact metal layer 210 being connected to the first contact metal layer 209; the work function of the first contact metal layer 209 being less than the work function of the second contact metal layer 210.

[0028] In this embodiment, preferably, the first contact metal layer 209 is a nickel metal layer; the second contact metal layer 210 includes a titanium metal layer and an aluminum metal layer, or the second contact metal layer 210 includes a nickel metal layer, a titanium metal layer and an aluminum metal layer.

[0029] In another embodiment of this utility model,

[0030] Different contact metals are designed for the N+ source region 204 and the P+ source region 205, so that the metals simultaneously form anti-blocking layers with both the N+ and P+ source regions, achieving ideal ohmic contact and thus reducing ohmic contact resistance. Nickel is selected for the N+ source region, while two or more metals are selected for the P+ source region, such as titanium aluminum (Ti / Al) or nickel titanium aluminum (Ni / Ti / Al).

[0031] Preparation method: On the surface of the silicon carbide epitaxial layer, a P-type base region 203, an N+ source region 204, and a P+ source region 205 are formed by ion implantation. Then, a metal layer, such as nickel, is deposited on the N+ source region, and multiple metal layers, such as titanium aluminum (Ti / Al) and nickel titanium aluminum (Ni / Ti / Al), are deposited on the P+ source region. After that, high-temperature annealing is performed at a temperature of 900℃ to 1100℃ for a time of 2 min to 10 min. The annealing process is used to form an alloy between the semiconductor and the metal to eliminate the potential barrier between the semiconductor and the metal, thereby forming an ideal ohmic contact.

[0032] like Figure 1As shown, the structure specifically includes an N+ silicon carbide substrate 201, an N- epitaxial layer 202, equally spaced P-type base regions 203 disposed within the active region of the epitaxial layer 202, an N+ source region 204 and a P+ source region 205 disposed within the P-type base region 203, a gate oxide layer 206 on the epitaxial layer, a polysilicon electrode layer 207 disposed above the gate oxide layer, a gate-source isolation layer 208, a first contact metal layer 209, and a second contact metal layer 210. After ion implantation and high-temperature activation of the P-type base region 203, the N+ source region 204, and the P+ source region 205, different types of metals are deposited in the N+ source region 204 and the P+ source region 205, respectively. When Wm (metal work function) < Ws (semiconductor work function), an anti-blocking layer can be formed between the metal and the N-type semiconductor; while when Wm (metal work function) > Ws (semiconductor work function), an anti-blocking layer can also be formed between the metal and the P-type semiconductor. Therefore, nickel metal is deposited in the N+ source region 204, and titanium aluminum (Ti / Al) or nickel titanium aluminum (Ni / Ti / Al) is deposited in the P+ source region 205. This allows the metal to form an antiblocking layer with both the N+ source region 204 and the P+ source region 205. After depositing the metal, a high-temperature annealing process is used to alloy the metal and the semiconductor, thereby forming an ohmic contact. This reduces the forward voltage drop of the body diode while decreasing the on-resistance of the MOSFET, and also reduces the losses of the MOSFET when used in the circuit.

[0033] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0034] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide MOSFET with reduced body diode voltage drop, characterized by: The application relates to a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, which comprises: a silicon carbide substrate; an epitaxial layer, the lower side of which is connected to the upper side of the silicon carbide substrate; a first recess is arranged in the epitaxial layer; a P-type base region is arranged in the first recess, and a second recess is arranged in the P-type base region; an N+ source region is arranged in the second recess; a P+ source region is arranged in the second recess, and the outer side of the P+ source region is connected to the inner side of the N+ source region; a gate oxide layer, the lower side of which is connected to the N+ source region, the P-type base region and the epitaxial layer; a polysilicon electrode layer, the lower side of which is connected to the upper side of the gate oxide layer; a first contact metal layer, the lower side of which is connected to the N+ source region; a second contact metal layer, the lower side of which is connected to the P+ source region, and the second contact metal layer is connected to the first contact metal layer; the metal work function of the first contact metal layer is smaller than that of the second contact metal layer.

2. A silicon carbide MOSFET for reducing the voltage drop of a body diode as defined in claim 1, wherein: The first contact metal layer is a nickel metal layer; the second contact metal layer comprises a titanium metal layer and an aluminum metal layer, or the second contact metal layer comprises a nickel metal layer, a titanium metal layer and an aluminum metal layer.

3. A silicon carbide MOSFET for reducing the voltage drop of a body diode as defined in claim 1, wherein: The application further comprises a gate-source isolation layer, which wraps the polysilicon electrode layer, and the lower side of the gate-source isolation layer is connected to the N+ source region.

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