Pixel sensor array and image sensor device

Abstract

The embodiment of the utility model provides a pixel sensor array. The pixel sensor array comprises a plurality of pixel sensors and a deep trench isolation structure, wherein the pixel sensors are arranged in a grid and comprise a plurality of photodiodes positioned in a substrate; the deep trench isolation structure surrounds the photodiodes in the side direction and is positioned in the substrate; a metal grid structure over the deep trench isolation structure and over the substrate; and an anti-reflection layer on a top surface of the metal grid structure, wherein the metal grid structure surrounds the plurality of photodiodes and the top surface faces away from the substrate. The anti-reflective structure may reduce the likelihood of and reduce the extent of optical crosstalk occurring between adjacent pixel sensors in the pixel sensor array.

Description

Technical Field

[0001] The embodiments of this utility model relate to a pixel sensor array and an image sensor device, and particularly to a pixel sensor array and an image sensor device including a metal grid structure. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors may include multiple pixel sensors. Each pixel sensor in a CMOS image sensor may include a transfer gate transistor, which may include a photodiode and a transfer gate. The photodiode is configured to convert photons of incident light into a photocurrent of electrons, and the transfer gate is configured to control the flow of the photocurrent between the photodiode and a drain region. The drain region may be configured to receive the photocurrent, such that the photocurrent can be measured and / or transferred to other regions of the CMOS image sensor. Utility Model Content

[0003] An embodiment of this utility model provides a pixel sensor array comprising a plurality of pixel sensors arranged in a grid and including a plurality of photodiodes located in a substrate, a deep trench isolation structure laterally surrounding the plurality of photodiodes and located in the substrate, a metal grid structure located above the deep trench isolation structure and above the substrate, and an anti-reflection layer located on the top surface of the metal grid structure, wherein the metal grid structure surrounds the plurality of photodiodes and the top surface faces away from the substrate.

[0004] An embodiment of the present invention provides an image sensor device comprising a plurality of pixel sensors arranged in a pixel sensor array and including a plurality of photodiodes located in a substrate of the image sensor device, a deep trench isolation structure located around the plurality of photodiodes and located in the substrate, and a metal grid structure located above the deep trench isolation structure and located above the substrate, wherein the metal grid structure surrounds the plurality of photodiodes, and wherein the metal grid structure includes a plurality of concave surfaces located in the top surface of the metal grid structure.

[0005] Based on the above, the image sensor device of embodiments of this utility model may include one or more types of anti-reflective structures located on a metal grid structure, the metal grid structure surrounding pixel sensors in a pixel sensor array of the image sensor device. The anti-reflective structure may include an anti-reflective layer, nanostructures extending from the anti-reflective layer, and / or multiple cavities formed in the metal grid structure. The anti-reflective structure may be present in and / or on one or more surfaces of the metal grid structure to reduce the reflection of incident light, which may reduce the likelihood and / or the degree of optical crosstalk between adjacent pixel sensors in the pixel sensor array.

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a diagram of an example of the pixel sensor described in this article.

[0008] Figures 2A to 2C This is a diagram of an example of an image sensor device described in this article.

[0009] Figures 3A to 3D This is a diagram of an example of a pixel sensor array of the sensor chip described in this article.

[0010] Figures 4A to 4D This is a diagram of an example of a pixel sensor array of the sensor chip described in this article.

[0011] Figures 5A to 5J This is a diagram of an example of a pixel sensor array of the sensor chip described in this article.

[0012] Figures 6A to 6E This is a diagram illustrating an exemplary implementation of the circuit system die (or part of the circuit system die) described herein.

[0013] Figures 7A to 7F This is a diagram illustrating an exemplary implementation of the sensor die (or part of a sensor die) described herein.

[0014] Figures 8A to 8F This is a diagram illustrating an exemplary embodiment of the image sensor device (or part of an image sensor device) described herein.

[0015] Figures 9A to 9F This is a figure illustrating an exemplary implementation of forming nanostructures on the metal lattice structure of the pixel sensor array described in this paper.

[0016] Figures 10A to 10DThis is a figure illustrating an exemplary implementation of forming nanostructures on the metal lattice structure of the pixel sensor array described in this paper.

[0017] Figures 11A to 11E This is a diagram of an exemplary embodiment in which an anti-reflective layer is formed on the metal lattice structure of the pixel sensor array described herein.

[0018] Figures 12A to 12C This is a diagram of an exemplary embodiment in which an anti-reflective layer is formed on the metal lattice structure of the pixel sensor array described herein.

[0019] Figures 13A to 13D This is a diagram of an exemplary embodiment in which a cavity is formed in the metal grid structure of the pixel sensor array described herein.

[0020] Figure 14A and Figure 14B This is a diagram of an exemplary embodiment in which a cavity is formed in the metal grid structure of the pixel sensor array described herein.

[0021] Figure 15 This is a flowchart of an exemplary process associated with the metal lattice structure that forms a pixel sensor array.

[0022] Explanation of reference numerals in the attached figures

[0023] 100: Pixel sensor; 102: Power supply voltage (V) dd ); 104: Electrical ground; 106: Sensing area; 108: Control circuit system area; 110: Photocurrent; 112: Photodiode; 114: Transfer gate; 116: Transfer voltage (V) tx ); 118: Reset gate; 120: Reset voltage (V) rst ); 122: Floating diffusion node; 124: Source follower gate; 126: Row select gate; 128: Select voltage (V) di); 130: Output; 200, 300, 308, 312, 314, 400, 404, 406, 408, 500, 504, 506, 508, 510, 512, 514, 516, 518, 520: Instance; 202: Circuit System Chip; 204: Sensor Chip; 206: Circuit System Die; 208: Sensor Die; 210: Image Sensor Device; 212, 216: Device Layer; 214, 218: Interconnect Layer; 220: Interface Surface; 222: Pixel sensor array; 224: Metal grid structure; 226: Black level (BLC) area; 228: Bonding pad area; 230: Sealing ring area; 232, 246: Substrate; 234, 238, 248, 258, 274, 276, 278, 280, 282: Dielectric layer; 236: Device; 240, 260: Bonding layer; 242, 262: Interconnect structure / first interconnect structure / second interconnect structure; 244, 264: Bonding structure; 250 252: Shallow trench isolation (STI) structure; 254: Deep trench isolation (DTI) structure; 255: Dielectric material; 256: Dielectric pad; 266, 302: Passivation layer; 268: Color filter area / NIR bandpass color filter area / blue filter area / green filter area / red filter area / yellow filter area; 270: Microlens; 272: Metal layer; 284: Bonding pad structure; 286: Bonding pad opening; 304: Nanostructure; 306: Top surface; 310: Sidewall; 402, 902: Anti-reflective layer; 502: Cavity; 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400: Implementation scheme; 904, 1102: Patterned masking layer; 1302: Masking layer; 1304, 1402: Pattern; 1500: Process; 1510, 1520, 1530, 1540: Block; D1, D2, D3, D4, D5, D6, D7, D8, D9: Size; x, y, z: Direction. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0025] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0026] An image sensor device (such as a complementary metal-oxide-semiconductor (CMOS) image sensor device or another type of image sensor device) is an electronic semiconductor device that uses pixel sensors to generate photocurrents based on light received at the pixel sensors. The magnitude of the photocurrent can be based on the intensity of the light, the wavelength of the light, and / or another property of the light. The photocurrent is then processed to generate electronic images, electronic video, and / or another type of electronic signal.

[0027] Optical crosstalk can occur between adjacent pixels in an image sensor array. Optical crosstalk is the phenomenon where incident light passes through a pixel sensor at a non-orthogonal angle due to optical crosstalk and is at least partially absorbed by the photodiodes of adjacent pixels. Optical crosstalk can degrade the spatial resolution of the image sensor, reduce the overall sensitivity of the image sensor, cause color mixing between pixels, and / or lead to image noise after color correction.

[0028] In some cases, one or more structures are included in the pixel sensor array to reduce and / or minimize optical crosstalk between the individual pixels in the array. For example, a deep trench isolation (DTI) structure can be formed in the substrate, such that the DTI structure surrounds the photodiodes of the pixel sensors in the pixel sensor array. As another example, a metal grating structure can be formed above the substrate and can surround the pixel sensors in a similar manner to the DTI structure. The metal grating structure can be formed of one or more metallic materials to facilitate the reflection of incident light toward the photodiodes of the pixel sensors, thereby improving the quantum efficiency (QE) of the pixel array. However, some incident light may be reflected away from one pixel sensor and toward another, causing the incident light to pass through multiple different types of color filters. This can lead to optical crosstalk between the pixel sensors and associated color mixing.

[0029] The image sensor device described herein may include one or more types of anti-reflective structures located on a metal grating structure surrounding pixel sensors in a pixel sensor array of the image sensor device. The anti-reflective structure may include an anti-reflective layer, nanostructures extending from the anti-reflective layer, and / or multiple cavities formed in the metal grating structure. The anti-reflective structure may be present in and / or on one or more surfaces of the metal grating structure to reduce the reflection of incident light, which may reduce the likelihood and / or the degree of optical crosstalk between adjacent pixel sensors in the pixel sensor array.

[0030] Figure 1 This is a diagram illustrating an example of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the front side of a sensor die), a rear-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the back side of a sensor die), and / or another type of pixel sensor. The pixel sensor 100 may be electrically connected to a power supply voltage (V). dd 102 and electrical ground 104.

[0031] The pixel sensor 100 includes a sensing area 106, which is configured to sense and / or accumulate incident light (e.g., light directed toward the pixel sensor 100). The pixel sensor 100 also includes a control circuitry system area 108. The control circuitry system area 108 is electrically connected to the sensing area 106 and is configured to receive a photocurrent 110 generated by the sensing area 106. Additionally, the control circuitry system area 108 is configured to transfer the photocurrent 110 from the sensing area 106 to downstream circuitry (e.g., an amplifier or an analog-to-digital (AD) converter, etc.).

[0032] Sensing region 106 includes a photodiode 112. The photodiode 112 absorbs and accumulates photons of incident light and generates a photocurrent 110 based on the absorbed photons. The magnitude of the photocurrent 110 is based on the amount of light collected in the photodiode 112. Therefore, the accumulation of photons in the photodiode 112 produces a build-up of electrical charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge corresponds to a larger intensity or brightness, and a smaller amount of charge corresponds to a lower intensity or brightness).

[0033] Photodiode 112 is electrically connected to the source of transfer gate 114 located in control circuit system region 108. Transfer gate 114 is configured to control the transfer of photocurrent 110 from photodiode 112. Photocurrent 110 is supplied from the source to the drain of transfer gate 114 based on selectively switching the gate of transfer gate 114. A transfer voltage (V) can be applied to transfer gate 114. tx The transfer voltage 116 is used to selectively switch the gate of the transfer gate 114. In some embodiments, the transfer voltage 116 applied to the transfer gate 114 causes a conductive path to be formed between the source and drain of the transfer gate 114, allowing the photocurrent 110 to flow from the source to the drain along the conductive path. In some embodiments, removing the transfer voltage 116 from the transfer gate 114 (or the absence of the transfer voltage 116) causes the conductive path to be removed, preventing the photocurrent 110 from flowing from the source to the drain.

[0034] The control circuit system area 108 further includes a reset gate 118. The reset gate 118 is electrically connected to the power supply voltage 102. The reset gate 118 can be controlled by a reset voltage (V). rst )120 is controlled. The transfer gate 114 and reset gate 118 can be electrically coupled to the floating diffusion node 122. Before enabling the transfer gate 114 to transfer the photocurrent 110 from the photodiode 112 to the floating diffusion node 122, a reset voltage 120 can be applied to the reset gate 118 to pull the drain of the transfer gate 114 to a high voltage (e.g., supply voltage 102) to "reset" the floating diffusion node 122 (e.g., by drawing all residual charge from the floating diffusion node 122).

[0035] The photocurrent 110 can be used to apply a floating diffusion voltage (V) to the source follower gate 124 of the control circuit system region 108. fd This allows the photocurrent 110 to be observed without removing or venting it from the floating diffusion node 122. Alternatively, a reset gate 118 can be used to remove or vent the photocurrent 110 from the floating diffusion node 122.

[0036] The source follower gate 124 serves as a high-impedance amplifier for the pixel sensor 100. The source follower gate 124 provides voltage-to-current conversion for the floating diffusion voltage. The output of the source follower gate 124 is electrically connected to the row selection gate 126, which is configured to control the flow of photocurrent 110 to external circuitry. This is achieved by selectively applying a selection voltage (V0) to the gate of the row selection gate 126. di )128 is used to control the row selection gate 126. This allows the photocurrent 110 to flow to the output 130 of the pixel sensor 100.

[0037] As mentioned above, Figure 1 It is provided as an instance. Other instances may differ from those targeted at... Figure 1 Examples provided.

[0038] Figures 2A to 2C This is a figure of example 200 of the image sensor device described in this article. Figure 2A As shown, an image sensor device can be formed by bonding a circuit system wafer 202 and a sensor wafer 204. For example, bonding tools can be used to perform bonding operations on the circuit system wafer 202 and the sensor wafer 204 using metal-to-metal bonding, dielectric-to-dielectric bonding, and / or another bonding technique. In the bonding operation, a circuit system die 206 located on the circuit system wafer 202 and an associated sensor die 208 located on the sensor wafer 204 are bonded to form an image sensor device 210. The image sensor device 210 is then diced and packaged. Other processing steps may be performed to form the image sensor device 210.

[0039] Each image sensor device 210 includes a circuit system die 206 and a sensor die 208. The circuit system die 206 and the sensor die 208 may be stacked in the image sensor device 210 or arranged vertically in the image sensor device 210. The sensor die 208 includes a pixel sensor array, which includes a plurality of pixel sensors 100 or portions of a plurality of pixel sensors 100. Specifically, the pixel sensor array includes at least the sensing area 106 of the pixel sensor 100 (and therefore includes a photodiode 112). Thus, the sensor die 208 is primarily configured to sense photons of incident light and convert the photons into a photocurrent 110.

[0040] The circuit system die 206 includes circuitry configured to measure, manipulate, and / or otherwise utilize the photocurrent 110. Additionally, the circuit system die 206 includes at least a subset of transistors in the control circuitry region 108 of the pixel sensor 100. For example, the circuit system die 206 may include a row select gate 126 of the pixel sensor 100, a source follower gate 124 of the pixel sensor, and / or combinations thereof. This provides an increased area for the photodiode 112 on the sensor die 208, which allows the size of the photodiode 112 to be increased to improve the overall performance of the pixel sensor's sensitivity and / or photosensitivity and / or to allow the size of the pixel sensor 100 to be reduced while maintaining the same size for each photodiode 112.

[0041] like Figure 2AAs further shown, the circuit system die 206 may include a device layer 212 and an interconnect layer 214. Device layer 212 may include devices of the circuit system die 206 (e.g., transistors), and interconnect layer 214 may include interconnects that enable signals and / or power to be provided to and / or from the devices in device layer 212. Sensor die 208 may also include a device layer 216 and an interconnect layer 218. Device layer 216 may include portions of pixel sensor 100, such as photodiode 112, transfer gate 114, and floating diffusion node 122, etc. Interconnect layer 218 may include interconnects that enable signals and / or power to be provided to and / or from device layer 216.

[0042] The circuit system die 206 and the sensor die 208 can be coupled at a bonding interface 220, which may be located between the interconnect layer 214 and the interconnect layer 218 and / or may be located in a portion of the interconnect layer 214 and / or a portion of the interconnect layer 218. The bonding interface 220 may include bonding pads, bonding vias, bonding dielectric layers, and / or other bonding structures.

[0043] Figure 2B This is a top view of an exemplary pixel sensor array 222 included on sensor die 208. Pixel sensor array 222 may be included on sensor die 208 of image sensor device 210. Figure 2B As shown, the pixel sensor array 222 may include a plurality of pixel sensors 100 (or portions of said plurality of pixel sensors 100). For example, the pixel sensor array 222 may include photodiodes 112 of the pixel sensors 100. Figure 2B As further shown, the pixel sensors 100 can be arranged in a grid. In some embodiments, the pixel sensors 100 are square in shape (e.g., Figure 2B (As shown in the example). In some embodiments, the pixel sensor 100 includes other shapes, such as rectangular, circular, octagonal, rhomboid, and / or other shapes.

[0044] In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is approximately 1 micrometer. In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is less than approximately 1 micrometer. For example, the width of one or more of pixel sensors 100 may range from approximately 0.6 micrometers to approximately 0.7 micrometers. In these examples, pixel sensor 100 may be referred to as a sub-micron pixel sensor. Sub-micron pixel sensors can reduce the pixel sensor pitch (e.g., the distance between adjacent pixel sensors) in pixel sensor array 222, which can increase the pixel sensor density in pixel sensor array 222 (which can improve the efficiency of pixel sensor array 222). However, other values ​​in the range of pixel sensor 100 size are also within the scope of this disclosure.

[0045] Each pixel sensor 100 may be configured to sense a specific wavelength range of incident light associated with a specific color component of the incident light. For example, pixel sensor 100 may be configured to sense a wavelength range associated with the red component of the incident light, and thus may be referred to as a red pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the blue component of the incident light, and thus may be referred to as a blue pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the green component of the incident light, and thus may be referred to as a green pixel sensor. In some embodiments, multiple pixel sensors 100 are configured to sense a wavelength range associated with the near-infrared (NIR) component of the incident light, and thus may be referred to as NIR pixel sensors. NIR pixel sensors may be included in pixel sensor array 222 to improve the low-light performance of image sensor device 210 and / or enable image sensor device 210 to achieve night-vision functionality.

[0046] like Figure 2B As further shown, the photodiodes 112 of the pixel sensor 100 can be electrically and optically isolated by the metal grid structure 224 included in the pixel sensor array 222. The photodiodes 112 may be formed in the substrate of the sensor die 208, and the metal grid structure 224 may be included above the substrate. The metal grid structure 224 includes a plurality of intersecting metal lines located around the periphery of the pixel sensor 100. The metal grid structure 224 may be formed of tungsten (W) and / or another suitable metal or metal alloy. The metal grid structure 224 may be included in the pixel sensor array 222 to reduce optical crosstalk between the pixel sensors 100, which in turn reduces color mixing between the pixel sensors 100.

[0047] Figure 2C A cross-sectional view of the image sensor device 210 is shown. Figure 2C As shown, the circuit system die 206 and the sensor die 208 can be joined at the interface 220, such that the circuit system die 206 and the sensor die 208 are stacked in the image sensor device 210 in the z-direction or arranged vertically in the image sensor device 210 in the z-direction. Figure 2C As further shown, the image sensor device 210 includes a pixel sensor array 222 (e.g., including pixel sensor 100), a black level (BLC) region 226 adjacent to (e.g., horizontally adjacent to) the pixel sensor array 222, a bonding pad region 228 adjacent to (e.g., horizontally adjacent to) the BLC region 226, and a sealing ring region 230 adjacent to (e.g., horizontally adjacent to) the bonding pad region 228, etc.

[0048] like Figure 2C As further shown, the image sensor device 210 includes multiple layers, such as device layer 212 and interconnect layer 214 of circuit system die 206, and device layer 216 and interconnect layer 218 of sensor die 208. Device layer 212 of circuit system die 206 includes a substrate 232 and a dielectric layer 234 located above the substrate 232. The substrate 232 may comprise silicon (Si) (e.g., a silicon substrate), a silicon-containing material, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), silicon-on-insulator (SOI), or another type of semiconductor material. The substrate 232 may include a semiconductor layer (e.g., a silicon layer). The dielectric layer 234 may comprise one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), and / or carbon-doped silicon oxide, etc.

[0049] Device 236 may be included in and / or on the substrate 232 of device layer 212. Device 236 may include one or more application-specific integrated circuit (ASIC) devices, one or more system-on-chip (SOC) devices, one or more transistors and / or one or more other components configured to measure the extent of photocurrent 110 generated by pixel sensor 100 to determine the light intensity of incident light and / or generate images and / or video (e.g., digital images, digital video).

[0050] The interconnect layer 214 of the circuit system die 206 may include a dielectric layer 238, a bonding layer 240, a plurality of interconnect structures 242 located in the dielectric layer 238, and a plurality of bonding structures 244 located in the bonding layer 240. The dielectric layer 238 may include one or more interlayer dielectric (ILD) layers, one or more intermetallic dielectric (IMD) layers, and / or one or more etch stop layers (ESL), etc. The dielectric layer 238 and the bonding layer 240 may each contain one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, etc.

[0051] Interconnect structures 242 may each include conductive wires, channels, vias, interconnects, metallization layers, and / or other types of conductive structures that electrically connect device 236 to one or more other areas of circuit system die 206 and / or one or more areas of sensor die 208. Bonding structures 244 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 242 and bonding structures 244 may each contain one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), as well as other examples of conductive materials.

[0052] The device layer 216 of the sensor die 208 includes a substrate 246 and a dielectric layer 248 located beneath the substrate 246. The substrate 246 may comprise silicon (Si) (e.g., a silicon substrate), a silicon layer or another type of semiconductor layer, a silicon-containing material, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), SOI, or another type of semiconductor material. The dielectric layer 248 may comprise one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, etc.

[0053] The photodiode 112 of the pixel sensor 100 is included in the substrate 246 of the sensor die 208. Each photodiode 112 may include one or more doped regions of the substrate 246. Various types of ions can be used to dope the substrate 246 to form a pn junction or PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion) corresponding to the photodiode 112. For example, an n-type dopant can be used to dope the substrate 246 to form a first portion (e.g., an n-type portion) of the photodiode 112, and a p-type dopant can be used to dope the substrate 246 to form a second portion (e.g., a p-type portion) of the photodiode 112. The photodiode 112 can be configured to absorb photons of incident light. Due to the photoelectric effect, the absorption of photons causes the photodiode 112 to accumulate charge (photocurrent 110). Here, photons bombard the photodiode 112, causing the photodiode 112 to emit electrons. The emission of electrons causes the formation of electron-hole pairs, in which the electrons migrate toward the cathode of the photodiode 112 and the holes migrate toward the anode, which generates a photocurrent 110.

[0054] Each photodiode 112 can be electrically and / or optically isolated from each other through one or more isolation structures in the substrate 246. A shallow trench isolation (STI) structure 250 extends from the bottom side of the substrate 246 (referred to as the front side of the substrate 246) into the substrate 246, and a deep trench isolation (DTI) structure 252 extends from the top side of the substrate 246 (referred to as the back side of the substrate 246) over the STI structure 250. The combination of the STI structure 250 and the DTI structure 252 in the substrate 246 surrounds the pixel sensor 100 in the substrate 246 and provides electrical and / or optical isolation for each pixel sensor 100 in the substrate 246.

[0055] STI structure 250 may contain one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y And / or silicon oxynitride (SiON), etc. The DTI structure 252 may include an elongated structure formed of dielectric material 254 and a dielectric pad 256 located between the dielectric material 254 and the substrate 246. The DTI structure 252 extends along the side of the photodiode 112 and is connected to... Figure 2B The top view of the metal grid structure 224 shown is conformal. The dielectric material 254 may also be included as a buffer layer on the top side of the substrate 246. The dielectric pad 256 may be included on the sidewalls and bottom surface of the DTI structure 252 and may be included as an antireflective coating (ARC) and / or further facilitate electrical and / or optical isolation for each pixel sensor 100. In some embodiments, the dielectric material 254 comprises silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)) and silicon nitride (SiO2) x N y ), silicon carbide (SiC) x ), Hafnium oxide (HfO) x The dielectric material may include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicon glass (FSG), carbon-doped silicon oxide, and / or another dielectric material. In some embodiments, the dielectric pad 256 may comprise a high-k dielectric material, such as silicon nitride (SiON). x N y ), Hafnium oxide (HfO) x ) and / or another high dielectric constant dielectric material.

[0056] The transfer gate 114 of the pixel sensor 100 is included in the dielectric layer 248 and on the bottom side of the substrate 246. The transfer gate 114 is electrically connected to the interconnect layer 218, which allows an input (e.g., gate voltage) to be provided to the transfer gate 114 to control the flow of photocurrent 110 from the photodiode 112 to the floating diffusion node 122 (not shown) of the pixel sensor 100.

[0057] The interconnect layer 218 may include a dielectric layer 258, a bonding layer 260, a plurality of interconnect structures 262 located in the dielectric layer 258, and a plurality of bonding structures 264 located in the bonding layer 260. The dielectric layer 258 may include one or more ILD layers, one or more IMD layers, and / or one or more ESL layers, etc. The dielectric layer 258 and the bonding layer 260 may each contain one or more dielectric materials, such as silicon oxide (SiO2).x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, etc.

[0058] Interconnect structures 262 may each include conductive lines, trenches, vias, interconnects, metallization layers, and / or other types of conductive structures that electrically connect the transfer gate 114 to one or more other regions of the sensor die 208 and / or one or more regions of the circuit system die 206. Bonding structures 264 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 262 and bonding structures 264 may each contain one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), as well as other examples of conductive materials.

[0059] At bonding interface 220, bonding layer 240 and bonding layer 260 may be bonded together (e.g., by dielectric-to-dielectric bonding), and bonding structure 244 and bonding structure 264 may be bonded together (e.g., by metal-to-metal bonding). Signals and / or power may be provided between circuit system die 206 and sensor die 208 via bonding structures 244 and 264.

[0060] A passivation layer 266 may be included on the buffer layer above the top side of the substrate 246, and a metal lattice structure 224 may be included above the passivation layer 266. The passivation layer 266 may comprise, for example, silicon oxide (SiO2). x Oxide materials such as silicon nitride (SiN) are used for the passivation layer 266. Alternatively and / or as an alternative, silicon nitride (SiN) is used for the passivation layer 266. x ), silicon carbide (SiC) x ) or mixtures thereof (e.g., silicon carbon nitride (SiCN), silicon oxynitride (SiON) or another dielectric material).

[0061] like Figure 2CAs shown, each segment of the metal grid structure 224 may have an approximately trapezoidal cross-sectional shape or profile. Alternatively and / or as another option, each segment of the metal grid structure 224 may have an approximately square cross-sectional profile. Each segment of the metal grid structure 224 may be located above the DTI structure 252 and may be formed around the periphery of the photodiode 112 of the pixel sensor 100. Openings in the metal grid structure 224 are included above the photodiode 112 to allow incident light to pass through the metal grid structure 224 and reach the photodiode 112. The metal grid structure 224 may be formed of a metallic material (e.g., gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)) and / or combinations thereof, etc.).

[0062] An opening in the metal grid structure 224 may include a color filter region 268 of the pixel sensor 100. The color filter region 268 may be located above a photodiode 112 of the pixel sensor 100. Each color filter region 268 may be configured to filter incident light so that incident light of a specific wavelength can pass through to the photodiode 112. For example, the color filter region 268 may filter incident light so that red light can pass through the color filter region 268 to reach the associated photodiode 112. As another example, the color filter region 268 may filter incident light so that green light can pass through the color filter region 268 to reach the associated photodiode 112. As another example, the color filter region 268 may filter incident light so that blue light can pass through the color filter region 268 to reach the associated photodiode 112.

[0063] Blue filter area 268 allows incident light components with wavelengths up to 450 nm to pass through while blocking other wavelengths. Green filter area 268 allows incident light components with wavelengths up to 550 nm to pass through while blocking other wavelengths. Red filter area 268 allows incident light components with wavelengths up to 650 nm to pass through while blocking other wavelengths. Yellow filter area 268 allows incident light components with wavelengths up to 580 nm to pass through while blocking other wavelengths.

[0064] In some embodiments, the color filter region 268 may be non-discriminative or unfiltered, which defines the white pixel sensor. The non-discriminative or unfiltered color filter region 268 may contain material that allows light of all wavelengths to pass through the associated photodiode 112 (e.g., to determine overall brightness to improve the photosensitivity of the image sensor). In some embodiments, the color filter region 268 may be an NIR bandpass color filter region 268 that defines the NIR pixel sensor. The NIR bandpass color filter region 268 may contain material that blocks visible light from passing through the associated photodiode 112 while allowing a portion of the incident light in the NIR wavelength range to pass through the associated photodiode 112.

[0065] Microlenses 270 may be included on and / or on the color filter area 268. Microlenses 270 may include corresponding microlenses for each of the pixel sensors 100. The microlenses may be configured to focus incident light toward the photodiode 112 of the associated pixel sensor 100.

[0066] like Figure 2C As further shown, a metal layer 272 may be included above substrate 246 in the BLC region 226 of substrate 246. The metal layer 272 may serve as a light-blocking layer to prevent incident light from entering the portion of substrate 246 located in the BLC region 226. Therefore, the portion of substrate 246 located in the BLC region 226 is a sensing area that remains "dark," allowing dark current measurement to be performed in the BLC region 226. Dark current measurement can be performed to measure the amount of charge (dark current) generated in substrate 246 from sources other than incident light (e.g., from heat energy in substrate 246), allowing the dark current measurement to be used for black level correction (or black level calibration) of the pixel sensor array 222.

[0067] like Figure 2C As further shown, the bonding pad region 228 may include a plurality of dielectric layers 274, 276, 278, 280, and 282 that electrically isolate the bonding pad structure 284. The bonding pad structure 284 is electrically coupled and / or physically coupled to one or more of the interconnect structures 262 located in the interconnect layer 218 of the sensor die 208. A bonding pad opening 286 is included above the bonding pad structure 284 to enable the formation of external electrical connections to the bonding pad structure 284.

[0068] The plurality of dielectric layers 274, 276, 278, 280 and 282 may each contain one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si xN y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, etc. The bonding pad structure 284 may contain metallic materials such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof, etc.

[0069] The sealing ring region 230 includes a plurality of stacked interconnect structures 242 located in the interconnect layer 214 and a plurality of stacked interconnect structures 262 located in the interconnect layer 218, to seal the structure and layers of the image sensor device 210, thereby preventing moisture and other contaminants from entering and providing structural rigidity to the image sensor device 210.

[0070] As mentioned above, Figures 2A to 2C It is provided as an instance. Other instances may differ from those targeted at... Figures 2A to 2C Examples provided.

[0071] Figures 3A to 3D This is a diagram of an example of the pixel sensor array 222 of the sensor die 208 described in this article. Figures 3A to 3D A cross-sectional view showing an example of pixel sensor array 222. Figures 3A to 3D The examples shown each include an exemplary embodiment of an anti-reflective structure for the metal grating structure 224 of the pixel sensor array 222. Each exemplary embodiment of the anti-reflective structure described herein may include, within the associated pixel sensor array 222, an embodiment to reduce, minimize, and / or prevent reflection of incident light from one pixel sensor 100 toward another pixel sensor 100. Therefore, each exemplary embodiment of the anti-reflective structure described herein may reduce, minimize, and / or prevent optical crosstalk between the individual pixel sensors 100 of the associated pixel sensor array 222. Figures 3A to 3D One or more of the examples of the pixel sensor array 222 shown may be included in the combination Figures 2A to 2C The image sensor device 210 shown and described contains a sensor die 208.

[0072] like Figure 3AAs shown, an example 300 of the pixel sensor array 222 includes a plurality of pixel sensors 100. Each pixel sensor 100 includes a photodiode 112 located in a substrate 246 of a sensor die 208. A DTI structure 252 is included around the photodiode 112 in the substrate 246, and a metal grid structure 224 is included on the substrate 246 above the DTI structure 252. The metal grid structure 224 extends over the substrate 246 and surrounds the photodiode 112. A color filter region 268 is included between the openings of the metal grid structure 224, and a microlens 270 is included on the color filter region. A passivation layer 302 may be additionally included on the metal grid structure 224, or the passivation layer 302 may be omitted.

[0073] As further shown in Example 300, a nanostructure 304 is included on the top surface 306 of the metal lattice structure 224. The nanostructure 304 may include nanotubes, nanowires, and / or other types of nanostructures extending from the top surface 306 of the metal lattice structure 224. The nanostructure 304 may be formed of carbon (C) and / or another suitable material. Because the nanostructure 304 can absorb photons of incident light that would otherwise reflect away from the top surface 306 of the metal lattice structure 224, the nanostructure 304 can reduce optical crosstalk in the pixel sensor array 222.

[0074] The length of the 304 nanostructure (in) Figure 3A The length of the nanostructure 304 (indicated as size D1) can range from approximately 80 nanometers to approximately 1000 nanometers. If the length of the nanostructure 304 is less than approximately 80 nanometers, the nanostructure 304 may not provide sufficient optical absorption to reduce or prevent optical crosstalk, while if the length of the nanostructure 304 is greater than approximately 1000 nanometers, the nanostructure 304 may reduce the absorption of photons in the photodiode 112 (which can reduce the quantum efficiency of the pixel sensor 100). If the length of the nanostructure 304 is within the range of approximately 80 nanometers to approximately 1000 nanometers, the nanostructure 304 can provide sufficient optical absorption to reduce or prevent optical crosstalk while enabling the pixel sensor 100 to achieve high quantum efficiency. However, other values ​​of the length of the nanostructure 304, and ranges other than approximately 80 nanometers to approximately 1000 nanometers, are also within the scope of this disclosure.

[0075] The nanostructure 304 may extend in a direction approximately perpendicular to the top surface 306 of the metal lattice structure 224. Alternatively and / or as another option, at least a subset of the nanostructure 304 may extend in a direction at an angle (e.g., at an angle of approximately 60 degrees or approximately 75 degrees) relative to the top surface 306 of the metal lattice structure 224.

[0076] like Figure 3AAs further shown, the metal grid structure 224 in example 300 of the pixel sensor array 222 may have an approximately trapezoidal cross-sectional shape or profile. For example, the cross-sectional width of the top surface 306 of the metal grid structure 224 may be smaller than the cross-sectional width of the bottom surface of the metal grid structure 224. Therefore, the cross-sectional width of the metal grid structure 224 increases from the top surface 306 to the bottom surface.

[0077] Figure 3B Example 308 of pixel sensor array 222 is shown. Example 308 of pixel sensor array 222 is similar to example 300 of pixel sensor array 222, except that example 308 further includes a nanostructure 304 located on the sidewalls 310 of the metal grating structure 224. Therefore, the nanostructure 304 is included on the top surface 306 and sidewalls 310 of the metal grating structure 224. The nanostructure 304 can further reduce optical crosstalk by absorbing photons of incident light directed toward the sidewalls 310 of the metal grating structure 224.

[0078] Figure 3C Example 312 of pixel sensor array 222 is shown. Example 312 of pixel sensor array 222 is similar to example 300 of pixel sensor array 222, except that the metal grid structure 224 in example 312 of pixel sensor array 222 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224.

[0079] Figure 3D Example 314 of pixel sensor array 222 is shown, which is similar to example 312 of pixel sensor array 222, except that example 314 further includes a nanostructure 304 located on the sidewall 310 of the metal grating structure 224. Therefore, the nanostructure 304 is included on the top surface 306 and the sidewall 310 of the metal grating structure 224, wherein the sidewall 310 is approximately perpendicular to the top surface 306. The nanostructure 304 can further reduce optical crosstalk by absorbing photons of incident light directed toward the sidewall 310 of the metal grating structure 224.

[0080] As mentioned above, Figures 3A to 3D It is provided as an instance. Other instances may differ from those targeted at... Figures 3A to 3D Examples provided.

[0081] Figures 4A to 4D This is a diagram of an example of the pixel sensor array 222 of the sensor die 208 described in this article. Figures 4A to 4D A cross-sectional view showing an example of pixel sensor array 222. Figures 4A to 4DThe examples shown each include an exemplary embodiment of an anti-reflective structure for the metal grating structure 224 of the pixel sensor array 222. Each exemplary embodiment of the anti-reflective structure described herein may include, within the associated pixel sensor array 222, an embodiment to reduce, minimize, and / or prevent reflection of incident light from one pixel sensor 100 toward another pixel sensor 100. Therefore, each exemplary embodiment of the anti-reflective structure described herein may reduce, minimize, and / or prevent optical crosstalk between the individual pixel sensors 100 of the associated pixel sensor array 222. Figures 4A to 4D One or more of the examples of the pixel sensor array 222 shown may be included in the combination Figures 2A to 2C The image sensor device 210 shown and described contains a sensor die 208.

[0082] like Figure 4A As shown, an example 400 of the pixel sensor array 222 includes a plurality of pixel sensors 100. Each pixel sensor 100 includes a photodiode 112 located in a substrate 246 of a sensor die 208. A DTI structure 252 is included around the photodiode 112 in the substrate 246, and a metal grid structure 224 is included on the substrate 246 above the DTI structure 252. The metal grid structure 224 extends over the substrate 246 and surrounds the photodiode 112. A color filter region 268 is included between the openings of the metal grid structure 224, and a microlens 270 is included on the color filter region. A passivation layer 302 may be additionally included on the metal grid structure 224, or the passivation layer 302 may be omitted.

[0083] As further shown in Example 400, an antireflective layer 402 is included on the top surface 306 of the metal lattice structure 224. Each antireflective layer 402 may comprise an antireflective material layer that absorbs photons of incident light. The antireflective material layer may have one or more properties that, when included on the metal lattice structure 224, cause incident light of a wide range of wavelengths to be canceled. Examples of such properties include refractive index, optical band gap, and / or thickness, etc. The properties of the antireflective material layer can cause the formation of destructive waves that are out of phase with the incident light, and these destructive waves cancel the incident light, thus preventing or reducing the reflection of the incident light away from the metal lattice structure 224. Therefore, the antireflective material can be selected based on the material used for the metal lattice structure 224. For example, the antireflective material can be selected such that the refractive index, optical band gap, and / or another property of the antireflective material, in combination with the refractive index, optical band gap, and / or another property of the metallic material of the metal lattice structure, causes the formation of destructive waves that cancel the incident light. Examples of such antireflective materials include zinc oxide (ZnO), aluminum-doped zinc oxide (Al:ZnO or AZO), and / or aluminum oxide (Al₂O₃). x O y For example, Al3O4, etc.

[0084] The thickness of the anti-reflective layer 402 (in) Figure 4A The thickness of the antireflective layer 402 (indicated as size D2) can range from approximately 50 nanometers to approximately 200 nanometers. If the thickness of the antireflective layer 402 is less than approximately 50 nanometers or greater than approximately 200 nanometers, the properties of the antireflective layer 402 may not be able to effectively cancel incident light to reduce or prevent optical crosstalk in combination with the properties of the metallic material of the metallic lattice structure 224. If the thickness of the antireflective layer 402 is within the range of approximately 50 nanometers to approximately 200 nanometers, the properties of the antireflective layer 402 can effectively cancel incident light to reduce or prevent optical crosstalk in combination with the properties of the metallic material of the metallic lattice structure 224. However, other values ​​for the thickness of the antireflective layer 402, as well as ranges other than approximately 50 nanometers to approximately 200 nanometers, are also within the scope of this disclosure.

[0085] like Figure 4A As further shown, the metal grid structure 224 in example 400 of the pixel sensor array 222 may have an approximately trapezoidal cross-sectional shape or profile. For example, the cross-sectional width of the top surface 306 of the metal grid structure 224 may be smaller than the cross-sectional width of the bottom surface of the metal grid structure 224. Therefore, the cross-sectional width of the metal grid structure 224 increases from the top surface 306 to the bottom surface.

[0086] Figure 4BExample 404 of pixel sensor array 222 is shown, which is similar to example 400 of pixel sensor array 222, except that in example 404, antireflective layer 402 is included on the sidewall 310 of metal grid structure 224. Therefore, antireflective layer 402 is included on the top surface 306 and sidewall 310 of metal grid structure 224. Antireflective layer 402 can further reduce optical crosstalk by canceling the reflection of incident light that would otherwise be reflective of the sidewall 310 of metal grid structure 224.

[0087] Figure 4C Example 406 of pixel sensor array 222 is shown. Example 406 of pixel sensor array 222 is similar to example 400 of pixel sensor array 222, except that the metal grid structure 224 in example 406 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224.

[0088] Figure 4D Example 408 of pixel sensor array 222 is shown. Example 408 of pixel sensor array 222 is similar to example 406 of pixel sensor array 222, except that in example 404 of pixel sensor array 222, the antireflective layer 402 is included on the sidewall 310 of the metal grid structure 224. Therefore, the antireflective layer 402 is included on the top surface 306 and the sidewall 310 of the metal grid structure 224, wherein the sidewall 310 is approximately perpendicular to the top surface 306. The antireflective layer 402 can further reduce optical crosstalk by canceling the reflection of incident light that would otherwise be reflected away from the sidewall 310 of the metal grid structure 224.

[0089] As mentioned above, Figures 4A to 4D It is provided as an instance. Other instances may differ from those targeted at... Figures 4A to 4D Examples provided.

[0090] Figures 5A to 5J This is a diagram of an example of the pixel sensor array 222 of the sensor die 208 described in this article. Figures 5A to 5J A cross-sectional view showing an example of pixel sensor array 222. Figures 5A to 5JThe examples shown each include an exemplary embodiment of an anti-reflective structure for the metal grating structure 224 of the pixel sensor array 222. Each exemplary embodiment of the anti-reflective structure described herein may include, within the associated pixel sensor array 222, an embodiment to reduce, minimize, and / or prevent reflection of incident light from one pixel sensor 100 toward another pixel sensor 100. Therefore, each exemplary embodiment of the anti-reflective structure described herein may reduce, minimize, and / or prevent optical crosstalk between the individual pixel sensors 100 of the associated pixel sensor array 222. Figures 5A to 5J One or more of the examples of the pixel sensor array 222 shown may be included in the combination Figures 2A to 2C The image sensor device 210 shown and described contains a sensor die 208.

[0091] like Figure 5A As shown, an example 500 of the pixel sensor array 222 includes a plurality of pixel sensors 100. Each pixel sensor 100 includes a photodiode 112 located in a substrate 246 of a sensor die 208. A DTI structure 252 is included around the photodiode 112 in the substrate 246, and a metal grid structure 224 is included on the substrate 246 above the DTI structure 252. The metal grid structure 224 extends over the substrate 246 and surrounds the photodiode 112. A color filter region 268 is included between the openings of the metal grid structure 224, and a microlens 270 is included on the color filter region. A passivation layer 302 may be additionally included on the metal grid structure 224, or the passivation layer 302 may be omitted.

[0092] As further shown in Example 500, a cavity 502 is included in the top surface 306 of the metal grid structure 224 as an anti-reflection structure. The cavity 502 causes the top surface 306 of the metal grid structure 224 to have multiple concave surfaces (or multiple recessed surfaces). The cavities 502 may be spaced apart from each other in the top surface 306 and may each have an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile. The curved or rounded surfaces of the cavities 502 cause photons of the incident light to scatter. The scattering of photons of the incident light around the photodiode 112 causes the incident light to be guided away from the top surface 306 of the metal grid structure 224 in multiple directions, thereby reducing the concentration of photons reflected toward other photodiodes 112 and thereby reducing optical crosstalk in the pixel sensor array 222.

[0093] Cavity 502 may have one or more dimensions, such as depth (in) Figure 5A The size D3 is shown in the middle, and the spacing between adjacent cavities 502 is shown in the middle. Figure 5A The dimensions are shown as D4) and / or the width is shown as (in the image). Figure 5A(shown as size D5), etc. One or more sizes of cavities 502, the number of cavities 502, and / or another parameter of cavities 502 can be selected to reduce, minimize, and / or prevent optical crosstalk caused by incident light reflecting off the metal grid structure 224. The one or more sizes of cavities 502, the number of cavities 502, and / or another parameter of cavities 502 can be selected based on the size of the pixel sensor 100 (e.g., the width of the pixel sensor 100, the spacing between adjacent pixel sensors 100, and / or another parameter, the width of the pixel sensor 100 being based on one or more wavelengths of incident light to be sensed by the pixel sensor array 222).

[0094] In some embodiments, the depth (size D3) of cavity 502 ranges from approximately 1 nanometer to approximately 10 nanometers. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the spacing (size D4) between adjacent cavities 502 ranges from approximately 1 nanometer to approximately 5 nanometers. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the width (size D5) of cavity 502 ranges from approximately 1 nanometer to approximately 50 nanometers. However, other values ​​within this range are also within the scope of this disclosure.

[0095] like Figure 5A As further shown, the metal grid structure 224 in example 500 of the pixel sensor array 222 may have an approximately trapezoidal cross-sectional shape or profile. For example, the cross-sectional width of the top surface 306 of the metal grid structure 224 may be smaller than the cross-sectional width of the bottom surface of the metal grid structure 224. Therefore, the cross-sectional width of the metal grid structure 224 increases from the top surface 306 to the bottom surface.

[0096] Figure 5B Example 504 of pixel sensor array 222 is shown. Example 504 of pixel sensor array 222 is similar to example 500 of pixel sensor array 222, except that in example 504, the cavity 502 has an approximately V-shaped (or triangular) cross-sectional profile. The cavity 502 in example 504 may have one or more sizes, such as depth (in...). Figure 5B The size is shown as D6), and the spacing between adjacent cavities 502 is shown as... Figure 5B The sidewall angle (shown as size D7) relative to the bottom surface of the metal grid structure 224 (in) Figure 5B The size (D8) and / or width (in) are shown in the figure. Figure 5B(shown as size D9), etc. One or more sizes of cavities 502, the number of cavities 502, and / or another parameter of cavities 502 can be selected to reduce, minimize, and / or prevent optical crosstalk caused by incident light reflecting off the metal grid structure 224. The one or more sizes of cavities 502, the number of cavities 502, and / or another parameter of cavities 502 can be selected based on the size of the pixel sensor 100 (e.g., the width of the pixel sensor 100, the spacing between adjacent pixel sensors 100, and / or another parameter, the width of the pixel sensor 100 being based on one or more wavelengths of incident light to be sensed by the pixel sensor array 222).

[0097] In some embodiments, the depth (size D6) of cavity 502 ranges from approximately 1 nanometer to approximately 10 nanometers. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the spacing (size D7) between adjacent cavities 502 ranges from approximately 1 nanometer to approximately 5 nanometers. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the sidewall angle (size D8) of cavity 502 ranges from approximately 30 degrees to approximately 75 degrees. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the width (size D9) of cavity 502 ranges from approximately 1 nanometer to approximately 50 nanometers. However, other values ​​within this range are also within the scope of this disclosure.

[0098] Figure 5C Example 506 of pixel sensor array 222 is shown. Example 506 of pixel sensor array 222 is similar to example 500 of pixel sensor array 222, except that in example 504 of pixel sensor array 222, a cavity 502 with an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile is also included in the sidewall 310 of the metal grid structure 224. Therefore, the cavity 502 with an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile is included in the top surface 306 and sidewall 310 of the metal grid structure 224. The cavity 502 in the sidewall 310 can further reduce optical crosstalk by scattering incident light guided to the sidewall 310 of the metal grid structure 224.

[0099] Figure 5DExample 508 of pixel sensor array 222 is shown. Example 508 of pixel sensor array 222 is similar to example 504 of pixel sensor array 222, except that in example 504 of pixel sensor array 222, a cavity 502 with an approximately V-shaped (or triangular) cross-sectional profile is also included in the sidewall 310 of the metal grid structure 224. Therefore, the cavity 502 with an approximately V-shaped (or triangular) cross-sectional profile is included in the top surface 306 and the sidewall 310 of the metal grid structure 224. The cavity 502 in the sidewall 310 can further reduce optical crosstalk by scattering incident light guided to the sidewall 310 of the metal grid structure 224.

[0100] Figure 5E Example 510 of pixel sensor array 222 is shown. Example 510 of pixel sensor array 222 is similar to examples 506 and 508 of pixel sensor array 222, except that... Figure 5E Example 510 of the pixel sensor array 222 includes cavities 502 located in the top surface 306 of the metal grid structure 224 and cavities 502 located in the sidewalls 310 of the metal grid structure 224, each cavity 502 having a different cross-sectional profile. For example, the cavity 502 located in the top surface 306 of the metal grid structure 224 may have an approximately V-shaped (or triangular) cross-sectional profile, and the cavity 502 located in the sidewalls 310 of the metal grid structure 224 may have an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile (e.g., ...). Figure 5E (As shown in the example). As another example, the cavity 502 located in the top surface 306 of the metal grid structure 224 may have an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile, and the cavity 502 located in the sidewall 310 of the metal grid structure 224 may have an approximately V-shaped (or triangular) cross-sectional profile. This allows for greater flexibility in configuring the metal grid structure 224 to further reduce optical crosstalk in the pixel sensor array 222.

[0101] Figure 5F Example 512 of pixel sensor array 222 is shown. Example 512 of pixel sensor array 222 is similar to example 500 of pixel sensor array 222, except that the metal grid structure 224 in example 512 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224.

[0102] Figure 5GExample 514 of pixel sensor array 222 is shown, which is similar to example 504 of pixel sensor array 222, except that the metal grid structure 224 in example 514 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224.

[0103] Figure 5H Example 516 of pixel sensor array 222 is shown, which is similar to example 506 of pixel sensor array 222, except that the metal grid structure 224 in example 516 of pixel sensor array 222 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224, and the cavities 502 located in the sidewalls 310 of the metal grid structure 224 may have approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profiles.

[0104] Figure 5I Example 518 of pixel sensor array 222 is shown, which is similar to example 508 of pixel sensor array 222, except that the metal grid structure 224 in example 518 of pixel sensor array 222 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224, and the cavities 502 located in the sidewalls 310 of the metal grid structure 224 may have an approximately V-shaped (or triangular) cross-sectional profile.

[0105] Figure 5J Example 520 of pixel sensor array 222 is shown, which is similar to example 510 of pixel sensor array 222, except that the metal grid structure 224 in example 520 has a square cross-sectional shape or profile. Therefore, the sidewalls 310 of the metal grid structure 224 are approximately perpendicular to the top surface 306 of the metal grid structure 224. The cavities 502 located in the sidewalls 310 may have an approximately V-shaped (or triangular) cross-sectional profile, or may have an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile.

[0106] As mentioned above, Figures 5A to 5J It is provided as an instance. Other instances may differ from those targeted at... Figures 5A to 5J Examples provided.

[0107] Figures 6A to 6EThis is a diagram illustrating an exemplary embodiment 600 of the circuit system die 206 (or a portion thereof) described herein. In some embodiments, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.) may be used to implement the combination. Figures 6A to 6E One or more of the semiconductor processing operations described.

[0108] Go to Figure 6A The substrate 232 provides the device layer 212 of the circuit system die 206. The substrate 232 may be provided in the form of a semiconductor wafer (e.g., a silicon (Si) wafer that may be provided as an SOI wafer and / or another type of semiconductor workpiece).

[0109] like Figure 6B As shown, one or more devices 236 may be formed in and / or on substrate 232. One or more semiconductor processing tools may be used to form one or more portions of device 236. For example, deposition tools may be used to perform various deposition operations to deposit layers of device 236 and / or deposit photoresist layers for etching portions of substrate 232 and / or the deposited layers. As another example, exposure tools may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, development tools may be used to develop the pattern in the photoresist layer. As another example, etching tools may be used to etch portions of substrate 232 and / or the deposited layers to form device 236. As another example, planarization tools may be used to planarize portions of device 236. As another example, plating tools may be used to deposit metal structures and / or layers of device 236.

[0110] like Figure 6B As further shown, a dielectric layer 234 can be deposited on and / or on the substrate 232 and on and / or on the device 236. The dielectric layer 234 can be deposited using deposition tools employing physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, or another type of deposition technique. In some embodiments, a planarization tool can be used to planarize the dielectric layer 234 after deposition.

[0111] like Figure 6CAs shown, a first portion of the interconnect layer 214 of the circuit system die 206 is formed above the device layer 212. To form the first portion of the interconnect layer 214, a dielectric layer 238 (which may include one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more dielectric layers of another type) can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, or another deposition technique. In some embodiments, a planarization tool may be used to planarize the dielectric layer 238 after deposition.

[0112] Various operations for forming the interconnect structure 242 in the first portion of the interconnect layer 214 can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, plating tools, and / or other semiconductor processing tools. The interconnect structure 242 can be deposited using PVD, ALD, CVD, electroplating, and / or other deposition techniques. In some embodiments, a planarization tool can be used to planarize the interconnect structure 242 after deposition.

[0113] In some embodiments, a first portion of the interconnect layer 214 is constructed in the z-direction within a plurality of via layers (V layers) and metallization layers (M layers). For example, a first portion of a dielectric layer 238 may be formed, a groove may be formed in the first portion of the dielectric layer 238, and a first interconnect structure 242 (e.g., V0 via layer, M0 metallization layer) may be formed in the groove. A second portion of the dielectric layer 238 may be formed, a groove may be formed in the second portion of the dielectric layer 238, and a second interconnect structure 242 (e.g., V1 via layer, M1 metallization layer) may be formed in the groove. The remaining via layers and / or metallization layers of the first portion of the interconnect layer 214 may be formed in a similar manner.

[0114] like Figure 6D and Figure 6E As shown, a second portion of the interconnect layer 214 can be formed, and the second portion of the interconnect layer 214 may include a bonding layer 240 and a bonding structure 244. Figure 6D As shown, a bonding layer 240 may be formed on and / or on the dielectric layer 238 and on and / or on the topmost interconnect structure 242. The bonding layer 240 may be deposited using deposition tools employing PVD, ALD, CVD, oxidation, or another deposition technique. In some embodiments, a planarization tool may be used to planarize the bonding layer 240 after deposition.

[0115] like Figure 6EAs shown, a bonding structure 244 can be formed in the bonding layer 240. For example, a patterned masking layer can be formed on the bonding layer 240 using deposition tools, exposure tools, and development tools. Etching tools can be used to etch the bonding layer 240 (e.g., using wet etching techniques, dry etching techniques) to form grooves in the bonding layer 240. Deposition tools and / or plating tools can be used to deposit the bonding structure 244 in the grooves using CVD, PVD, ALD, electroplating, and / or another deposition technique. In some embodiments, a planarization tool can be used to perform a planarization operation on the bonding structure 244 after it has been deposited.

[0116] As mentioned above, Figures 6A to 6E It is provided as an instance. Other instances may differ from those targeted at... Figures 6A to 6E Examples provided.

[0117] Figures 7A to 7F This is a diagram illustrating an exemplary embodiment 700 of the sensor die 208 (or a portion thereof) described herein. In some embodiments, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.) may be used to implement the combination. Figures 7A to 7F One or more of the semiconductor processing operations described.

[0118] Go to Figure 7A The substrate 246 provides the device layer 216 of the sensor die 208. The substrate 246 may be provided in the form of a semiconductor wafer (e.g., a silicon (Si) wafer that may be provided as an SOI wafer and / or another type of semiconductor workpiece).

[0119] like Figure 7B As shown, the photodiode 112 of the pixel sensor 100 of the pixel sensor array 222 of the sensor die 208 can be formed in the device layer 216 of the sensor die 208 in the substrate 246. In some embodiments, an ion implantation tool can be used to implant ions into the substrate 246 to form a PN junction between the p-doped region and the n-doped region of the substrate 246, or to form a PIN junction between the p-doped region of the substrate 246, the n-doped region of the substrate 246, and the intrinsic (e.g., undoped) semiconductor region of the photodiode 112.

[0120] like Figure 7BAs further shown, an STI structure 250 can be formed in the substrate 246 (e.g., from the front side of the substrate 246) such that the STI structure 250 is located between the photodiodes 112. In some embodiments, the STI structure 250 is formed after the photodiodes 112 are formed. In some embodiments, the STI structure 250 is formed before the photodiodes 112 are formed. A patterned masking layer can be formed on the substrate 246 using deposition tools, exposure tools, and development tools. An etching tool can be used to etch from the front side of the substrate 246 into the substrate 246 (e.g., using wet etching techniques, dry etching techniques) to form a trench in the front side of the substrate 246. A deposition tool can be used to deposit the STI structure 250 in the trench using CVD, PVD, ALD, oxidation, and / or another deposition technique. In some embodiments, a planarization tool can be used to perform a planarization operation to planarize the STI structure 250 after it has been deposited.

[0121] like Figure 7C As shown, a transfer gate 114 of the pixel sensor 100 may be formed on and / or on the front surface of the substrate 246. Forming the transfer gate 114 may include: depositing a gate dielectric layer on the front surface of the substrate 246; depositing a gate electrode on the gate dielectric layer; and / or forming sidewall spacers on the sidewalls of the gate electrode, etc.

[0122] like Figure 7C As further shown, a dielectric layer 248 may be formed on the front side of the substrate 246 and / or on the front side of the substrate 246 and on and / or on the transfer gate 114. The dielectric layer 248 may be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or another deposition technique. In some embodiments, a planarization tool may perform a planarization operation to planarize the dielectric layer 248 after it has been deposited.

[0123] like Figure 7D As shown, a first portion of the interconnect layer 218 of the sensor die 208 is formed above the device layer 216. To form the first portion of the interconnect layer 218, a dielectric layer 258 (which may include one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more dielectric layers of another type) can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, or another deposition technique. In some embodiments, a planarization tool may be used to planarize the dielectric layer 258 after deposition.

[0124] Various operations for forming the interconnect structure 262 in the first portion of the interconnect layer 218 can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, plating tools, and / or other semiconductor processing tools. The interconnect structure 262 can be deposited using PVD, ALD, CVD, electroplating, and / or other deposition techniques. In some embodiments, a planarization tool can be used to planarize the interconnect structure 262 after deposition.

[0125] In some embodiments, a first portion of the interconnect layer 218 is constructed in the z-direction within a plurality of via layers (V layers) and metallization layers (M layers). For example, a first portion of a dielectric layer 258 may be formed, a groove may be formed in the first portion of the dielectric layer 258, and a first interconnect structure 262 (e.g., V0 via layer, M0 metallization layer) may be formed in the groove. A second portion of the dielectric layer 258 may be formed, a groove may be formed in the second portion of the dielectric layer 258, and a second interconnect structure 262 (e.g., V1 via layer, M1 metallization layer) may be formed in the groove. The remaining via layers and / or metallization layers of the first portion of the interconnect layer 218 may be formed in a similar manner.

[0126] like Figure 7E and Figure 7F As shown, a second portion of the interconnect layer 218 may be formed, and the second portion of the interconnect layer 218 may include a bonding layer 260 and a bonding structure 264. Figure 7E As shown, a bonding layer 260 may be formed on and / or on the dielectric layer 258 and on and / or on the topmost interconnect structure 262. The bonding layer 260 may be deposited using deposition tools employing PVD, ALD, CVD, oxidation, or another deposition technique. In some embodiments, a planarization tool may be used to planarize the bonding layer 260 after deposition.

[0127] like Figure 7F As shown, a bonding structure 264 can be formed in the bonding layer 260. For example, a patterned masking layer can be formed on the bonding layer 260 using deposition tools, exposure tools, and development tools. Etching tools can be used to etch the bonding layer 260 (e.g., using wet etching techniques, dry etching techniques) to form grooves in the bonding layer 260. Deposition tools and / or plating tools can be used to deposit the bonding structure 264 in the grooves using CVD, PVD, ALD, electroplating, and / or another deposition technique. In some embodiments, a planarization tool can be used to perform a planarization operation on the bonding structure 264 after it has been deposited.

[0128] As mentioned above, Figures 7A to 7F It is provided as an instance. Other instances may differ from those targeted at... Figures 7A to 7F Examples provided.

[0129] Figures 8A to 8F This is a figure illustrating an exemplary embodiment 800 of the image sensor device 210 (or a part thereof) described herein. In some embodiments, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.) may be used to implement the combination. Figures 8A to 8F One or more of the semiconductor processing operations described.

[0130] like Figure 8A and Figure 8B As shown, a bonding operation is performed to bond the circuit system die 206 and the sensor die 208 to form an image sensor device 210. The circuit system die 206 and the sensor die 208 can be bonded at a bonding interface 220, which may include bonding layers 240 and 260 (bonding layers for the circuit system die 206 and the sensor die 208, respectively) and bonding structures 244 and 264 (bonding structures for the circuit system die 206 and the sensor die 208, respectively). A bonding tool can be used to form a dielectric-to-dielectric bond between bonding layers 240 and 260 at the bonding interface 220, and a metal-to-metal bond between bonding structures 244 and 264 at the bonding interface 220.

[0131] like Figure 8B As shown, after assembly, the circuit system die 206 and the sensor die 208 are stacked in the image sensor device 210 in the z-direction or arranged perpendicularly in the image sensor device 210 in the z-direction. The interconnect layer 214 of the circuit system die 206 and the interconnect layer 218 of the sensor die 208 face each other in the image sensor device 210, and the device layer 212 of the circuit system die 206 and the device layer 216 of the sensor die 208 face away from each other.

[0132] like Figure 8CAs shown, a DTI structure 252 can be formed in substrate 246 (e.g., on the back side of substrate 246) and around photodiode 112 in substrate 246. For example, a patterned masking layer can be formed on substrate 246 using deposition tools, exposure tools, and development tools. Substrate 246 can be etched from the back side of substrate 246 using etching tools (e.g., using wet etching techniques or dry etching techniques) to form trenches in the back side of substrate 246. The trenches are located above STI structure 250 and adjacent to photodiode 112.

[0133] Deposition tools can be used to conformally deposit a dielectric pad 256 of the DTI structure 252 in a trench and on the back surface of the substrate 246 using CVD, ALD, and / or another conformal deposition technique. Deposition tools can be used to deposit a dielectric material 254 of the DTI structure 252 in a trench on the dielectric pad 256 and above the substrate 246 using CVD, PVD, ALD, oxidation, and / or another deposition technique. In some embodiments, a planarization tool can perform a planarization operation to planarize the dielectric material 254 located above the substrate 246, wherein the dielectric material 254 may be retained as a buffer layer.

[0134] like Figure 8D As shown, a passivation layer 266 may be formed on and / or on the buffer layer, and a metal layer 272 may be formed on and / or on the passivation layer on the back side of the substrate 246. The passivation layer 266 may be deposited using deposition tools and / or plating tools employing CVD, PVD, ALD, oxidation, and / or another deposition technique. In some embodiments, a planarization tool may perform a planarization operation to planarize the passivation layer 266 after it has been deposited. The metal layer 272 may be deposited using CVD, PVD, ALD, electroplating, and / or another deposition technique. In some embodiments, a planarization tool may perform a planarization operation to planarize the metal layer 272 after it has been deposited.

[0135] like Figure 8EAs shown, various layers and / or structures can be formed in the bonding pad region 228 of the image sensor device 210. For example, grooves can be formed into the dielectric layer 248 through the metal layer 272, through the passivation layer 266, through the buffer layer (corresponding to the dielectric material 254 located above the substrate 246), through the dielectric pad 256, and / or through the substrate 246. In some embodiments, a patterned masking layer can be formed on the metal layer 272 using deposition tools, exposure tools, and development tools. The grooves can be formed by etching (e.g., using wet etching techniques, dry etching techniques) from the back side of the substrate 246 through the metal layer 272, through the passivation layer 266, through the buffer layer, through the dielectric pad 256, and through the substrate 246.

[0136] A dielectric layer 274 may be formed in a groove on dielectric layer 248. A dielectric layer 276 may be formed on dielectric layer 274. Dielectric layers 274 and 276 may be deposited in the groove using deposition tools employing CVD, PVD, ALD, oxidation, and / or another deposition technique.

[0137] Openings can be formed through dielectric layers 248, 274, and 276, allowing the interconnect structure 262 in interconnect layer 218 to be exposed via grooves. Bonding pad structures 284 can be formed in the openings, allowing the bonding pad structures 284 to rest on the interconnect structure 262. Bonding pad structures 284 are also formed on dielectric layer 276.

[0138] In some embodiments, a patterned masking layer may be formed on dielectric layer 276 using deposition tools, exposure tools, and development tools. Etching tools may be used to etch through dielectric layer 276, through dielectric layer 274, and through dielectric layer 248 (e.g., using wet etching techniques, dry etching techniques) to form grooves. Deposition tools and / or plating tools may be used to deposit bonding pad structures 284 in the grooves using CVD, PVD, ALD, electroplating, and / or another deposition technique.

[0139] A dielectric layer 278 may be formed on the bonding pad structure 284, and dielectric layers 280 and 282 may be deposited in the bonding pad region 228 to fill the groove. A bonding pad opening 286 may be formed through the dielectric layers 278, 280 and 282 to expose the bonding pad structure 284.

[0140] Dielectric layers 278, 280, and 282 can be deposited in the trench using deposition tools, CVD, PVD, ALD, oxidation, and / or another deposition technique. In some embodiments, a patterned masking layer can be formed on dielectric layer 282 using deposition tools, exposure tools, and development tools. Etching tools can be used to etch through dielectric layers 278, 280, and 282 (e.g., using wet etching techniques, dry etching techniques) to form bonding pad openings 286.

[0141] like Figure 8F As shown, the metal layer 272 in the pixel sensor array 222 is etched to form a metal grid structure 224. This can be achieved using a combination of... Figures 9A to 9F , Figures 10A to 10D , Figures 11A to 11E , Figures 12A to 12C , Figures 13A to 13D , Figure 14A and / or Figure 14B The described technique forms an anti-reflective structure in and / or on the metal grid structure 224.

[0142] In some implementations, a patterned masking layer can be formed on the metal layer 272 using deposition tools, exposure tools, and development tools. An etching tool can be used to etch through the metal layer 272 to the passivation layer 266 (e.g., using wet etching or dry etching techniques) to remove portions of the metal layer 272. The remaining portion of the metal layer 272 in the pixel sensor array 222 corresponds to the metal grid structure 224 located above the DTI structure 252.

[0143] like Figure 8F As further shown, a color filter region 268 is formed in the opening of the metal grid structure 224, such that the color filter region 268 is located above and / or on the photodiode 112 of the pixel sensor 100. A microlens 270 is formed on the color filter region 268.

[0144] As mentioned above, Figures 8A to 8F It is provided as an instance. Other instances may differ from those targeted at... Figures 8A to 8F Examples provided.

[0145] Figures 9A to 9F This is a figure of an exemplary embodiment 900 in which a nanostructure 304 is formed on a metal lattice structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figures 9A to 9F The techniques described are combined Figure 3A and Figure 3CExamples of pixel sensor array 222 shown and illustrated (e.g., examples in which nanostructure 304 is included on the top surface 306 of metal lattice structure 224) are formed in nanostructure 304. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.). Figures 9A to 9F One or more of the semiconductor processing operations described.

[0146] like Figure 9A As shown, a metal grid structure 224 can be formed above the back surface of substrate 246, such that the metal grid structure 224 is included above DTI structure 252. An etching tool can be used to perform an etching operation for forming the metal grid structure 224 from a metal layer (e.g., metal layer 272). In some embodiments, a dry etching technique, such as plasma-based etching, is used to form the metal grid structure 224, such that the sidewalls 310 of the metal grid structure 224 are angled relative to the top surface 306 of the metal grid structure 224. This results in the metal grid structure 224 forming an approximately trapezoidal cross-sectional profile. One or more parameters of the etching operation can be selected to etch the metal layer to form the approximately trapezoidal cross-sectional profile of the metal grid structure 224. The one or more parameters may include, for example, bias voltage, pressure, temperature, and / or another parameter. Alternatively, the one or more parameters of the etching operation can be selected such that dry etching forms the metal grid structure 224 with an approximately square cross-sectional profile. Compared to forming an approximately trapezoidal cross-sectional profile, the one or more parameters selected for the etching operation can enable more vertical etching to form an approximately square cross-sectional profile.

[0147] like Figure 9B As shown, an antireflective layer 902 can be formed on the metal grid structure 224 and / or on the back surface of the metal grid structure 224 and the substrate 246. The antireflective layer 902 can be deposited using deposition tools employing CVD, PVD, ALD, oxidation, and / or another deposition technique. Specifically, a conformal deposition technique can be used to conformally deposit the antireflective layer 902 such that the antireflective layer 902 conforms to the contour of the metal grid structure 224. The antireflective layer 902 may comprise one or more antireflective materials, such as zinc oxide (ZnO), aluminum-doped zinc oxide (Al:ZnO or AZO), and / or aluminum oxide (Al₂O₃). x O y For example, Al3O4, etc. The anti-reflective layer 902 can be formed as a substrate on which nanostructures 304 are formed or grown.

[0148] like Figure 9CAs shown, a patterned masking layer 904 can be formed on the top surface 306 of the metal grid structure 224. The masking layer can be formed on the back side of the substrate 246 and on the metal grid structure 224 using a deposition tool (e.g., using spin coating and / or another deposition technique). An exposure tool can be used to expose the masking layer to form a pattern within it. A development tool can be used to develop the pattern to form the patterned masking layer 904.

[0149] like Figure 9D As shown, an etching tool can be used to etch the anti-reflective layer 902 to remove a portion of the anti-reflective layer 902 from the back side of the substrate 246 and from the sidewall 310 of the metal grid structure 224. Therefore, the anti-reflective layer 902 remains only on the top surface 306 of the metal grid structure 224. Wet etching, dry etching, and / or another suitable etching technique can be used to remove said portion of the anti-reflective layer 902.

[0150] like Figure 9E As shown, the patterned masking layer 904 can be removed from the top surface 306 of the metal grid structure 224. The patterned masking layer 904 can be removed by etching the patterned masking layer 904, graying the patterned masking layer 904, and / or by using another suitable masking layer removal technique.

[0151] like Figure 9F As shown, a nanostructure 304 is formed on an antireflective layer 902 located on the top surface 306 of a metal lattice structure 224. A thermal annealing operation can be performed to form the nanostructure 304. For example, carbon (or graphite) powder can be deposited onto the antireflective layer 902 and the carbon (or graphite) powder can be annealed to allow the nanostructure 304 to grow from the carbon powder in a highly crystalline manner.

[0152] As mentioned above, Figures 9A to 9F It is provided as an instance. Other instances may differ from those targeted at... Figures 9A to 9F Examples provided.

[0153] Figures 10A to 10D This is a figure of an exemplary embodiment 1000 in which a nanostructure 304 is formed on a metal lattice structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figures 10A to 10D The techniques described are combined Figure 3B and Figure 3DExamples of pixel sensor array 222 shown and illustrated (e.g., examples in which nanostructure 304 is included on the top surface 306 and sidewalls 310 of metal lattice structure 224) are formed in nanostructure 304. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools and / or wafer / die transport tools, etc.). Figures 10A to 10D One or more of the semiconductor processing operations described.

[0154] The exemplary embodiment 1000 is similar to the exemplary embodiment 900 which forms the nanostructure 304 in that: a metal lattice structure 224 is formed; an anti-reflection layer 902 is formed on the top surface 306 and sidewalls 310 of the metal lattice structure 224 and on the back side of the substrate 246; and a portion of the anti-reflection layer 902 is removed using a patterned masking layer 904.

[0155] However, as Figure 10A As shown, in addition to the top surface 306 of the metal grid structure 224, a patterned masking layer 904 is also formed on the sidewalls 310 of the metal grid structure 224. Figure 10B As shown, this allows for the removal of said portion of the antireflective layer 902 from the back side of the substrate 246 without removing the antireflective layer 902 from the top surface 306 and sidewalls 310 of the metal lattice structure 224. Therefore, in the exemplary embodiment 1000 of forming the nanostructure 304, the antireflective layer 902 is included on the top surface 306 and sidewalls 310 of the metal lattice structure 224. Figure 10C As shown, the patterned masking layer 904 is removed after the anti-reflection layer 902 is etched.

[0156] like Figure 10D As shown, in the exemplary embodiment 1000 of forming the nanostructure 304, an anti-reflective layer 902 is retained on the sidewall 310 of the metal grid structure 224, so that the nanostructure 304 can grow on the top surface 306 of the metal grid structure 224 as well as on the sidewall 310 of the metal grid structure 224.

[0157] As mentioned above, Figures 10A to 10D It is provided as an instance. Other instances may differ from those targeted at... Figures 10A to 10D Examples provided.

[0158] Figures 11A to 11E This is a figure of an exemplary embodiment 1100 in which an anti-reflective layer 402 is formed on the metal lattice structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figures 11A to 11E The techniques described are combined Figure 4A and Figure 4C Examples of pixel sensor array 222 shown and illustrated (e.g., examples in which antireflective layer 402 is included on the top surface 306 of metal lattice structure 224) form antireflective layer 402. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.). Figures 11A to 11E One or more of the semiconductor processing operations described.

[0159] like Figure 11A As shown, a metal grid structure 224 can be formed above the back surface of substrate 246, such that the metal grid structure 224 is included above DTI structure 252. An etching tool can be used to perform an etching operation for forming the metal grid structure 224 from a metal layer (e.g., metal layer 272). In some embodiments, a dry etching technique, such as plasma-based etching, is used to form the metal grid structure 224, such that the sidewalls 310 of the metal grid structure 224 are angled relative to the top surface 306 of the metal grid structure 224. This results in the metal grid structure 224 forming an approximately trapezoidal cross-sectional profile. One or more parameters of the etching operation can be selected to etch the metal layer to form the approximately trapezoidal cross-sectional profile of the metal grid structure 224. The one or more parameters may include, for example, bias voltage, pressure, temperature, and / or another parameter. Alternatively, the one or more parameters of the etching operation can be selected such that dry etching forms the metal grid structure 224 with an approximately square cross-sectional profile. Compared to forming an approximately trapezoidal cross-sectional profile, the one or more parameters selected for the etching operation can enable more vertical etching to form an approximately square cross-sectional profile.

[0160] like Figure 11B As shown, an antireflective layer 402 can be formed on the metal grid structure 224 and / or on the back surface of the metal grid structure 224 and the substrate 246. The antireflective layer 402 can be deposited using deposition tools employing CVD, PVD, ALD, oxidation, and / or another deposition technique. Specifically, a conformal deposition technique can be used to conformally deposit the antireflective layer 402 such that the antireflective layer 402 conforms to the contour of the metal grid structure 224.

[0161] like Figure 11CAs shown, a patterned masking layer 1102 can be formed on the top surface 306 of the metal grid structure 224. The masking layer can be formed on the back side of the substrate 246 and on the metal grid structure 224 using a deposition tool (e.g., using spin coating and / or another deposition technique). An exposure tool can be used to expose the masking layer to form a pattern within it. A development tool can be used to develop the pattern to form the patterned masking layer 1102.

[0162] like Figure 11D As shown, an etching tool can be used to etch the anti-reflective layer 402 to remove a portion of the anti-reflective layer 402 from the back side of the substrate 246 and from the sidewall 310 of the metal grid structure 224. Therefore, the anti-reflective layer 402 remains only on the top surface 306 of the metal grid structure 224. Wet etching, dry etching, and / or another suitable etching technique can be used to remove said portion of the anti-reflective layer 402.

[0163] like Figure 11E As shown, the patterned masking layer 1102 can be removed from the top surface 306 of the metal grid structure 224. The patterned masking layer 1102 can be removed by etching the patterned masking layer 1102, graying the patterned masking layer 1102, and / or by using another suitable masking layer removal technique.

[0164] As mentioned above, Figures 11A to 11E It is provided as an instance. Other instances may differ from those targeted at... Figures 11A to 11E Examples provided.

[0165] Figures 12A to 12C This is a figure of an exemplary embodiment 1200 in which an anti-reflective layer 402 is formed on the metal grating structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figures 12A to 12C The techniques described are combined Figure 4B and Figure 4D Examples of pixel sensor array 222 shown and illustrated (e.g., examples in which antireflective layer 402 is included on the top surface 306 and sidewalls 310 of metal grid structure 224) form antireflective layer 402. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools and / or wafer / die transport tools, etc.). Figures 12A to 12C One or more of the semiconductor processing operations described.

[0166] The exemplary embodiment 1200 is similar to the exemplary embodiment 1100 which forms the anti-reflection layer 402 in that: a metal grid structure 224 is formed; the anti-reflection layer 402 is formed on the top surface 306 and sidewalls 310 of the metal grid structure 224 and on the back side of the substrate 246; and a portion of the anti-reflection layer 402 is removed using a patterned masking layer 1102.

[0167] However, as Figure 12A As shown, in addition to the top surface 306 of the metal grid structure 224, a patterned masking layer 1102 is also formed on the sidewalls 310 of the metal grid structure 224. Figure 12B As shown, this allows the portion of the antireflective layer 402 to be removed from the back side of the substrate 246 without removing the antireflective layer 402 from the top surface 306 and sidewalls 310 of the metal grid structure 224. Therefore, in the exemplary embodiment 1200 where the antireflective layer 402 is formed, the antireflective layer 402 is included on the top surface 306 and sidewalls 310 of the metal grid structure 224. Figure 12C As shown, the patterned masking layer 904 is removed after the anti-reflection layer 402 is etched.

[0168] As mentioned above, Figures 12A to 12C It is provided as an instance. Other instances may differ from those targeted at... Figures 12A to 12C Examples provided.

[0169] Figures 13A to 13D This is a diagram of an exemplary embodiment 1300 in which a cavity 502 is formed in the metal grid structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figures 13A to 13D The techniques described are combined Figure 5A , Figure 5B , Figure 5F and Figure 5G Examples of the pixel sensor array 222 shown and illustrated (e.g., examples in which cavity 502 is included in the top surface 306 of the metal grid structure 224) form cavity 502. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.). Figures 13A to 13D One or more of the semiconductor processing operations described.

[0170] like Figure 13AAs shown, a metal grid structure 224 can be formed above the back surface of substrate 246, such that the metal grid structure 224 is included above DTI structure 252. An etching tool can be used to perform an etching operation for forming the metal grid structure 224 from a metal layer (e.g., metal layer 272). In some embodiments, a dry etching technique, such as plasma-based etching, is used to form the metal grid structure 224, such that the sidewalls 310 of the metal grid structure 224 are angled relative to the top surface 306 of the metal grid structure 224. This results in the metal grid structure 224 forming an approximately trapezoidal cross-sectional profile. One or more parameters of the etching operation can be selected to etch the metal layer to form the approximately trapezoidal cross-sectional profile of the metal grid structure 224. The one or more parameters may include, for example, bias voltage, pressure, temperature, and / or another parameter. Alternatively, the one or more parameters of the etching operation can be selected such that dry etching forms the metal grid structure 224 with an approximately square cross-sectional profile. Compared to forming an approximately trapezoidal cross-sectional profile, the one or more parameters selected for the etching operation can enable more vertical etching to form an approximately square cross-sectional profile.

[0171] like Figure 13B and Figure 13C As shown, a masking layer 1302 may be formed on the metal grid structure 224 and on the back side of the substrate 246, and a pattern 1304 may be formed in the masking layer 1302. The masking layer 1302 may be formed on the back side of the substrate 246 and on the metal grid structure 224 using a deposition tool (e.g., using spin coating and / or another deposition technique). The masking layer 1302 may be exposed using an exposure tool to form the pattern 1304 in the masking layer. The pattern 1304 may be developed using a development tool. The pattern 1304 may include openings in the masking layer 1302 located above the top surface 306 of the metal grid structure 224.

[0172] like Figure 13D As shown, an etching tool can be used to etch the top surface 306 of the metal grid structure 224 based on the pattern 1304 in the masking layer 1302 to form a cavity 502 in the top surface 306 of the metal grid structure 224.

[0173] In some embodiments, a wet etching technique can be used to form the cavity 502, in which a wet etchant is provided to the top surface 306 of the metal grid structure 224 via a pattern 1304 in a masking layer 1302, and the wet etchant removes material from the top surface 306 of the metal grid structure 224. This results in the formation of a cavity in the top surface 306 of the metal grid structure 224. In some embodiments, the wet etching technique is used to give the cavity 502 an approximately curved, approximately rounded, and / or approximately semi-circular cross-sectional profile.

[0174] In some embodiments, a dry etching technique can be used to form the cavity 502, in which plasma and / or another type of dry etchant are provided to the top surface 306 of the metal grid structure 224 via a pattern 1304 in a masking layer 1302, and the dry etchant removes material from the top surface 306 of the metal grid structure 224. This results in the formation of a cavity in the top surface 306 of the metal grid structure 224. In some embodiments, the use of a dry etching technique results in the cavity 502 having an approximately V-shaped (or triangular) cross-sectional profile.

[0175] As mentioned above, Figures 13A to 13D It is provided as an instance. Other instances may differ from those targeted at... Figures 13A to 13D Examples provided.

[0176] Figure 14A and Figure 14B This is a figure of an exemplary embodiment 1400 in which a cavity 502 is formed in the metal grid structure 224 of the pixel sensor array 222 described herein. It can be used in conjunction with... Figure 14A and Figure 14B The techniques described are combined Figure 5C , Figure 5D , Figure 5E , Figure 5H , Figure 5I and Figure 5J Examples of the pixel sensor array 222 shown and illustrated (e.g., examples in which cavity 502 is included in the top surface 306 and sidewalls 310 of the metal grid structure 224) form cavity 502. In some embodiments, the combination may be implemented using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools and / or wafer / die transport tools, etc.). Figure 14A and Figure 14B One or more of the semiconductor processing operations described.

[0177] Example embodiment 1400 is similar to example embodiment 1300, which forms a cavity 502 in the metal grid structure 224. However, as Figure 14A As shown, a pattern 1402 is formed in the masking layer 1302, and the pattern 1402 includes openings located on the sidewalls 310 and the top surface 306 of the metal grid structure 224. Figure 14B As shown, an etching tool can be used to etch the top surface 306 of the metal grid structure 224 based on the pattern 1402 in the masking layer 1302 to form cavities 502 in the top surface 306 of the metal grid structure 224 and in the sidewalls 310 of the metal grid structure 224.

[0178] As mentioned above, Figure 14A and Figure 14B It is provided as an instance. Other instances may differ from those targeted at... Figure 14A and Figure 14B Examples provided.

[0179] Figure 15 This is a flowchart of an exemplary process 1500 associated with forming a metal lattice structure for a pixel sensor array. In some embodiments, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transport tools, etc.) are used to perform the process. Figure 15 The diagram shows one or more process blocks.

[0180] like Figure 15 As shown, process 1500 may include forming a plurality of photodiodes (block 1510) in the substrate of the pixel sensor array. For example, as illustrated herein, a plurality of photodiodes 112 may be formed in the substrate 246 of the pixel sensor array 222 using one or more semiconductor processing tools.

[0181] like Figure 15 As further shown, process 1500 may include forming a DTI structure (block 1520) around the plurality of photodiodes in the substrate. For example, as illustrated herein, a DTI structure 252 may be formed around the plurality of photodiodes 112 in the substrate 246 using one or more semiconductor processing tools.

[0182] like Figure 15 As further shown, process 1500 may include forming a metal grid structure (block 1530) over the substrate and over the DTI structure. For example, as illustrated herein, a metal grid structure 224 may be formed over the substrate 246 and over the DTI structure 252 using one or more semiconductor processing tools. In some embodiments, the DTI structure 252 laterally surrounds the plurality of photodiodes 112.

[0183] like Figure 15As further shown, process 1500 may include forming an anti-reflective structure in the top surface of the metal grid structure or at least one of the two locations on the top surface of the metal grid structure (block 1540). For example, as illustrated herein, one or more semiconductor processing tools may be used to form the anti-reflective structure in the top surface 306 of the metal grid structure 224 or at least one of the two locations on the top surface 306 of the metal grid structure 224. In some embodiments, the anti-reflective structure includes an anti-reflective layer 402 located on the top surface 306 of the metal grid structure 224. In some embodiments, the anti-reflective structure includes a plurality of nanostructures 304 located on the top surface 306 of the metal grid structure 224. In some embodiments, the anti-reflective structure includes a plurality of nanostructures 304 formed on the anti-reflective layer 902 located on the top surface 306 of the metal grid structure 224. In some embodiments, the anti-reflective structure includes a plurality of cavities 502 formed in the top surface 306 of the metal grid structure 224.

[0184] Process 1500 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes set forth below and / or in combination with those set forth elsewhere herein.

[0185] In a first embodiment, forming an anti-reflective structure includes depositing a dielectric material layer (e.g., anti-reflective layer 402, anti-reflective layer 902) on a metal grid structure 224 and on a substrate 246, and removing a portion of the dielectric material layer such that the remaining portion of the dielectric material layer corresponds to an anti-reflective layer (e.g., anti-reflective layer 402, anti-reflective layer 902) located on the top surface 306 of the metal grid structure 224.

[0186] In a second embodiment, either alone or in combination with the first embodiment, removing the portion of the dielectric material layer includes removing the portion of the dielectric material layer from the sidewall 310 of the metal grid structure 224.

[0187] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, process 1500 includes performing a thermal annealing operation to form nanowires (e.g., nanostructures 304) on the antireflective layer.

[0188] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, forming the antireflective layer includes forming a pattern (e.g., pattern 1304, pattern 1402) in a masking layer 1302 located on the metal grid structure 224, and etching the top surface 306 of the metal grid structure 224 based on the pattern to form a plurality of cavities 502 in the top surface 306 of the metal grid structure 224, wherein the plurality of cavities 502 correspond to antireflective structures located in the top surface 306 of the metal grid structure 224.

[0189] although Figure 15 An example block of process 1500 is shown; however, in some implementations, compared to Figure 15 The blocks depicted in the diagram, in process 1500, include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner. Alternatively, two or more of the blocks in process 1500 may be executed in parallel.

[0190] In this way, an image sensor device may include one or more types of anti-reflective structures located on a metal grating structure surrounding pixel sensors in a pixel sensor array of the image sensor device. The anti-reflective structure may include an anti-reflective layer, nanostructures extending from the anti-reflective layer, and / or multiple cavities formed in the metal grating structure. The anti-reflective structure may be present in and / or on one or more surfaces of the metal grating structure to reduce the reflection of incident light, which may reduce the likelihood and / or the degree of optical crosstalk between adjacent pixel sensors in the pixel sensor array.

[0191] As described in more detail above, some embodiments described herein provide a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors arranged in a grid and including a plurality of photodiodes located in a substrate. The pixel sensor array includes a DTI structure that laterally surrounds the plurality of photodiodes and is located in the substrate. The pixel sensor array includes a metal grid structure located above the DTI structure and above the substrate, wherein the metal grid structure surrounds the photodiodes. The pixel sensor array includes an anti-reflective layer on the top surface of the metal grid structure. The top surface faces away from the substrate.

[0192] In some embodiments, the metal grating structure has a substantially trapezoidal cross-sectional profile. In some embodiments, the antireflective layer is further included on the sidewalls of the metal grating structure. In some embodiments, the metal grating structure has a substantially square cross-sectional profile. In some embodiments, the metal grating structure further includes a plurality of nanowires located on the antireflective layer. In some embodiments, the plurality of nanowires includes a plurality of carbon nanowires. In some embodiments, the antireflective layer comprises at least one of the following: zinc oxide, aluminum oxide, or aluminum-doped zinc oxide.

[0193] As described in more detail above, some embodiments described herein provide an image sensor device. The image sensor device includes a plurality of pixel sensors arranged in a pixel sensor array and including a plurality of photodiodes located in a substrate of the image sensor device. The image sensor device includes a DTI structure located around the plurality of photodiodes and within the substrate. The image sensor device includes a metal grid structure located above the DTI structure and above the substrate, wherein the metal grid structure surrounds the photodiodes, and wherein the metal grid structure includes a plurality of concave surfaces in the top surface of the metal grid structure.

[0194] In some embodiments, the plurality of concave surfaces have rounded cross-sectional profiles. In some embodiments, the metal grid structure has a substantially trapezoidal cross-sectional profile. In some embodiments, the plurality of concave surfaces have a substantially V-shaped cross-sectional profile. In some embodiments, the metal grid structure includes a plurality of additional concave surfaces located in the sidewalls of the metal grid structure. In some embodiments, the cross-sectional profiles of the plurality of concave surfaces located in the top surface of the metal grid structure are different from the cross-sectional profiles of the plurality of additional concave surfaces located in the sidewalls of the metal grid structure. In some embodiments, the cross-sectional profiles of the plurality of concave surfaces located in the top surface of the metal grid structure are approximately the same as the cross-sectional profiles of the plurality of additional concave surfaces located in the sidewalls of the metal grid structure. In some embodiments, the metal grid structure has a substantially square cross-sectional profile.

[0195] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of photodiodes in a substrate of a pixel sensor array. The method includes forming a digital photodiode (DTI) structure around the plurality of photodiodes in the substrate. The method includes forming a metal grid structure over the substrate and on the DTI structure. The method includes forming an anti-reflective structure in the top surface of the metal grid structure or at at least one of two locations on the top surface of the metal grid structure.

[0196] In some embodiments, forming the antireflective structure includes: depositing a dielectric material layer on the metal lattice structure and on the substrate; and removing a portion of the dielectric material layer such that the remaining portion of the dielectric material layer corresponds to an antireflective layer located on the top surface of the metal lattice structure. In some embodiments, removing the portion of the dielectric material layer includes removing the portion of the dielectric material layer from a sidewall of the metal lattice structure. In some embodiments, the method further includes performing a thermal annealing operation to form nanowires on the antireflective layer. In some embodiments, forming the antireflective structure includes: forming a pattern in a masking layer located on the metal lattice structure; and etching the top surface of the metal lattice structure based on the pattern to form a plurality of cavities in the top surface of the metal lattice structure, wherein the plurality of cavities correspond to the antireflective structure located in the top surface of the metal lattice structure.

[0197] As used in this article, “satisfying the threshold value” may refer to a value greater than, greater than or equal to, less than, less than or equal to, equal to, not equal to, or similar to the threshold value, depending on the context.

[0198] The terms “approximately” and “substantially” can indicate the value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0199] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A pixel sensor array, comprising: comprising: a plurality of pixel sensors arranged in a grid and comprising a plurality of photodiodes located in a substrate; a deep trench isolation structure laterally surrounding the plurality of photodiodes and located in the substrate; a metal grid structure located above the deep trench isolation structure and above the substrate, wherein the metal grid structure surrounds the plurality of photodiodes; and an anti-reflective layer located on a top surface of the metal grid structure, wherein the top surface faces away from the substrate. wherein the metal grid structure has a trapezoidal cross-sectional profile or has a square-shaped cross-sectional profile.

2. The pixel sensor array of claim 1, wherein, wherein the anti-reflective layer further comprises on sidewalls of the metal grid structure.

3. The pixel sensor array of claim 1, wherein, wherein the metal grid structure further comprises a plurality of nanowires located on the anti-reflective layer.

4. The pixel sensor array of claim 1, wherein, wherein the plurality of nanowires comprises a plurality of carbon nanowires.

5. The pixel sensor array of claim 4, wherein, comprising:

6. An image sensor device, characterized by a plurality of pixel sensors arranged in a pixel sensor array and comprising a plurality of photodiodes located in a substrate of the image sensor device; a deep trench isolation structure located around the plurality of photodiodes and located in the substrate; and a metal grid structure located above the deep trench isolation structure and above the substrate, wherein the metal grid structure surrounds the plurality of photodiodes, and wherein the metal grid structure comprises a plurality of recessed surfaces located in a top surface of the metal grid structure. wherein the plurality of recessed surfaces has a rounded cross-sectional profile or has a V-shaped cross-sectional profile. wherein the metal grid structure comprises a further plurality of recessed surfaces located in sidewalls of the metal grid structure.

7. The image sensor device of claim 6, wherein, wherein the cross-sectional profile of the plurality of recessed surfaces located in the top surface of the metal grid structure is a different cross-sectional profile than the cross-sectional profile of the further plurality of recessed surfaces located in the sidewalls of the metal grid structure.

8. The image sensor device of claim 6, wherein, wherein the cross-sectional profile of the plurality of recessed surfaces located in the top surface of the metal grid structure is approximately the same cross-sectional profile as the cross-sectional profile of the further plurality of recessed surfaces located in the sidewalls of the metal grid structure.

9. The image sensor device of claim 8, wherein, ​ 10. The image sensor device of claim 8, wherein, ​

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