Double-capacitor leveling system for cantilever beam

Abstract

The utility model provides a double-capacitor leveling system for a cantilever beam, and the system comprises a piezoelectric region which comprises a bottom electrode layer, a piezoelectric layer, and a top electrode layer; a first capacitor including a bottom electrode layer, a first insulating film, and a primary metal layer electrically connected to the top electrode layer; a diode electrically connected to the bottom electrode layer; and a second capacitor on the diode, the second capacitor including a secondary metal layer electrically connected to the diode, a second insulating film, and a tertiary metal layer electrically connected to the top electrode layer. A MEMS element including a dual capacitance leveling system has a variety of advantages. After the back cavity is released, the position of the cantilever beam can be determined on the wafer during the test of the wafer, rather than after the die is separated and packaged. A bias voltage to be included with the operating voltage may be determined by an algorithm to ensure leveling during operation. Accordingly, a consistent cantilever beam position may be provided to prevent problems such as roll-off, inconsistent operating voltages, and / or pressure loss that may affect sensor readings.

Description

Technical Field

[0001] This utility model relates to a leveling system, and more particularly to a dual-capacitor leveling system for cantilever beams. Background Technology

[0002] Micro-electromechanical systems (MEMS) are technologies that utilize miniature mechanical and electromechanical components (e.g., elements or structures) on a wafer substrate. Utilizing microfabrication techniques, the range of MEMS components can extend from relatively simple structures without moving parts to complex electromechanical systems controlled by integrated microelectronic controllers using various moving parts. Components or structures that can be used in MEMS include microsensors, microactuators, microelectronics, and microstructures. MEMS components can be used in a wide range of applications, including, but not limited to, motion sensors, pressure sensors, inertial sensors, microfluidic devices (e.g., valve, pump, nozzle control), optical devices, imaging devices (e.g., micromachined ultrasonic transducers (MUTs)), capacitive MUTs (CMUTs), and more.

[0003] MEMS structures can be fabricated using a photoresist lithography process that transfers the desired shielding pattern onto a semiconductor wafer using ultraviolet light. The pattern can then be transferred to a layer beneath the photoresist using an etching process. This process is repeated multiple times with different patterns to create different layers on the wafer substrate and fabricate useful components. Utility Model Content

[0004] This invention provides a dual-capacitor leveling system for cantilever beams, comprising: a piezoelectric region including a bottom electrode layer, a piezoelectric layer on the bottom electrode layer, and a top electrode layer on the piezoelectric layer; a first capacitor including the bottom electrode layer, a first insulating film on the bottom electrode layer, and a primary metal layer on the first insulating film, the primary metal layer being electrically connected to the top electrode layer; a diode electrically connected to the bottom electrode layer; and a second capacitor located on the diode, including a secondary metal layer electrically connected to the diode, a second insulating film on the secondary metal layer, and a tertiary metal layer on the second insulating film and electrically connected to the top electrode layer.

[0005] Based on the above, MEMS devices incorporating dual-capacitor leveling systems offer several advantages. The position of the cantilever beam after the back cavity is released can be rapidly determined on the wafer during wafer acceptance testing, rather than after the die has been separated and packaged. The bias voltage to be included with the operating voltage can then be determined by an algorithm to ensure leveling during operation. Therefore, a consistent cantilever beam position can be provided, preventing issues such as roll-off, inconsistent operating voltages, and / or pressure losses that could affect sensor readings. Consistent membrane position also reduces reliance on stringent membrane stress requirements during manufacturing. MEMS devices incorporating cantilever beam / membrane and dual-capacitor leveling systems can be used for leak detection in systems requiring tight sealing, such as acoustic speakers, micropumps, or microvalves.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1A It is a plan view of a sensing system consisting of eight cantilever beams / films, and includes eight dual-capacitor leveling systems (one for each cantilever beam).

[0008] Figure 1B It is an enlarged plan view, depicting a membrane and a dual-capacitor leveling system.

[0009] Figure 2A This is a side cross-sectional view of the first capacitor region 300, including the first capacitor 310, in a dual-capacitor leveling system.

[0010] Figure 2B This is a side cross-sectional view of the second capacitor region 340, which includes the second capacitor 360, in a dual-capacitor leveling system.

[0011] Figure 2C It is a schematic plan view, illustrating the various layers and their arrangement of each component in the dual-capacitor leveling system.

[0012] Figure 2D It is a side cross-sectional view illustrating the electrical interconnection between the piezoelectric capacitors on the cantilever beam / membrane and the dual-capacitor leveling system.

[0013] Figures 3A-3D Together, a flowchart was formed illustrating a first method for forming a dual-capacitor leveling system according to some embodiments.

[0014] Figure 4 Through Figure 2C The Y-axis cross-sectional view of the AA line shows the situation after the first dielectric layer, adhesive layer and bottom electrode layer are formed on the substrate.

[0015] Figure 5 Through Figure 2C The Y-axis cross-section of the AA line shows the situation after the piezoelectric layer is formed on the bottom electrode layer.

[0016] Figure 6 Through Figure 2C The Y-axis cross-section of the AA line shows the situation after the top electrode layer is formed on the piezoelectric layer.

[0017] Figure 7 Through Figure 2C The Y-axis cross-section of the AA line shows the situation after the top electrode layer is patterned to expose the piezoelectric layer.

[0018] Figure 8 Through Figure 2C The Y-axis cross-section of the AA line shows the piezoelectric layer after it has been patterned to expose the bottom electrode layer.

[0019] Figure 9A Through Figure 2C The Y-axis cross-sectional view of the AA line shows the situation after the first intermetallic dielectric (IMD) sublayer is applied to the substrate. Figure 9B This is the corresponding schematic plan.

[0020] Figure 10 Through Figure 2C The Y-axis cross-section of the AA line is shown in the figure, which depicts the first capacitor region after the first IMD layer has been etched to expose a portion of the bottom electrode layer.

[0021] Figure 11 Through Figure 2C The Y-axis cross-sectional view of the AA line shows the situation after the first capacitor region is applied to the substrate.

[0022] Figure 12 Through Figure 2C The Y-axis cross-sectional view of the AA line shows the situation after the first capacitor region is patterned in the first insulating film.

[0023] Figure 13A Through Figure 2C The Y-axis cross-sectional view of the AA line shows the situation after the first capacitor region is applied to the substrate following the application of the second IMD sublayer. The first insulating film is thus covered by the second IMD sublayer. Figure 13B This is a Y-axis cross-sectional view, illustrating the second capacitor region after the second IMD sublayer is applied to the substrate.

[0024] Figure 14 Through Figure 2CThe Y-axis cross-section of the BB line is shown in this figure, illustrating the situation after the IMD layer has been etched to expose a portion of the second capacitor region of the bottom electrode layer.

[0025] Figure 15 Through Figure 2C The Y-axis cross-sectional view of the BB line shows the second capacitor region after the diode layer is applied to the substrate.

[0026] Figure 16 Through Figure 2C The Y-axis cross-section of the BB line is shown in this figure, illustrating the second capacitor region after the diode layer is patterned to form the diode.

[0027] Figure 17 Through Figure 2C The Y-axis cross-sectional view of the BB line shows the second capacitor region after the application of the third IMD sublayer on the substrate. The diode is thus covered by the third IMD sublayer.

[0028] Figure 18 Through Figure 2C The Y-axis cross-section of the BB line is shown in this figure, illustrating the second capacitor region after the third IMD sublayer is patterned to expose one end of the diode.

[0029] Figure 19 Through Figure 2C The Y-axis cross-sectional view of the BB line shows the second capacitor region after the first metal layer is applied to the substrate.

[0030] Figure 20 Through Figure 2C The Y-axis cross-sectional view of the BB line shows the second capacitor region after the second insulating film is applied to the substrate.

[0031] Figure 21 Through Figure 2C The Y-axis cross-sectional view of the BB line shows the second capacitor region after the first metal layer and the second insulating film have been patterned.

[0032] Figure 22 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line shows the situation after the fourth IMD sublayer is applied to the substrate.

[0033] Figure 23 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-section of the second capacitance region of the BB line is shown in this figure, illustrating the situation after the IMD layer is patterned to expose the top electrode layer in the piezoelectric region.

[0034] Figure 24 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line is shown in the figure after the IMD layer is patterned to expose the ends of the first and second insulating films.

[0035] Figure 25 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line is shown in the figure after the second metal layer has been applied to the substrate.

[0036] Figure 26 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line is shown in the figure after the second metal layer is patterned to expose the IMD layer above the central region of the first and second insulating films.

[0037] Figure 27 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line shows the situation after a passivation layer is applied to the substrate.

[0038] Figure 28 Through Figure 2C The first capacitance region of the AA line and through Figure 2C The Y-axis cross-sectional view of the second capacitor region of the BB line is shown in the figure after the back cavity is etched in the substrate.

[0039] Figure 29 It includes two diagrams illustrating the tensile and compressive stresses in a cantilever beam, and the circuits they generate.

[0040] Figure 30 It is a flowchart illustrating a cantilever beam calibration method according to some embodiments.

[0041] Explanation of reference numerals in the attached figures

[0042] 101: MEMS structure;

[0043] 102: Die (grain);

[0044] 103: Scribe lines;

[0045] 105: Dashed circle;

[0046] 110: Piezoelectric capacitor;

[0047] 112: Bottom electrode layer;

[0048] 114: Piezoelectric layer;

[0049] 116: Top electrode layer;

[0050] 120: Cantilever beam, cantilever / membrane beam;

[0051] 130: substrate;

[0052] 132: edge;

[0053] 134: backside cavity;

[0054] 140: First dielectric layer;

[0055] 142: Second dielectric layer;

[0056] 150: Adhesion layer;

[0057] 160: Bottom electrode layer;

[0058] 170: Piezoelectric layer;

[0059] 172: Upper surface;

[0060] 180: Top electrode layer;

[0061] 190: First intermetal dielectric sublayer, first IMD sublayer;

[0062] 191: Recess;

[0063] 194: Second IMD sublayer;

[0064] 198: Third IMD sublayer;

[0065] 199: Recess;

[0066] 202: Fourth IMD sublayer;

[0067] 210: Intermetal dielectric (IMD) layer, IMD layer;

[0068] 211, 212, 213, 214, 215, 216: Recess;

[0069] 217, 218: portion;

[0070] 219: IMD region;

[0071] 220: First insulator film;

[0072] 222, 252, 282, 352, 382: First end;

[0073] 224, 254, 354: Central region;

[0074] 226, 284, 256, 356, 384: Second end;

[0075] 230: Diode layer;

[0076] 240: First metal layer;

[0077] 242: portion;

[0078] 250: Second insulator film;

[0079] 260: Second metal layer;

[0080] 270: Passivation layer;

[0081] 280: Dual-capacitor leveling system;

[0082] 290: Piezoelectric region;

[0083] 300: First capacitor region;

[0084] 310: Capacitor, first capacitor, first metal-insulator-metal (MIM) capacitor, first MIM capacitor;

[0085] 330: Primary metal layer;

[0086] 332, 334: Section;

[0087] 340: Second capacitor region;

[0088] 350: Diode;

[0089] 360: Capacitor, second capacitor, second MIM capacitor;

[0090] 370: Secondary metal layer;

[0091] 380: Tertiary metal layer;

[0092] 390: Interconnects;

[0093] 392: Metal pad, first metal pad;

[0094] 394: Metal pad, second metal pad;

[0095] 396: Metal pad, third metal pad;

[0096] 398: Metal pad, fourth metal pad;

[0097] 400: First method;

[0098] 405, 410, 415, 420, 425, 430, 435, 440, 445, 450, 455, 460, 465, 470, 475, 480, 485, 490, 495, 500, 505, 510, 515, 520, 525, 530, 535, 540, 545, 550: Steps;

[0099] 590: Circuit diagrams, three-branch parallel circuit;

[0100] 592: First branch;

[0101] 594: Second branch;

[0102] 596: Third branch;

[0103] 600: Method;

[0104] 605, 610, 615, 620, 625, 630, 635, 640: Steps. Detailed Implementation

[0105] The following disclosure provides many different embodiments or examples to implement the various features of this invention. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second feature are in direct contact, or embodiments where an additional feature is formed between the first and second feature, so that the first and second feature may not be in direct contact. Furthermore, reference numerals and / or text may be repeated in various examples of this disclosure. This repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0106] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein to describe the relationship between one element or feature and another, as illustrated in the figures. In addition to the orientations shown in the figures, these spatial relative terms are also intended to encompass different orientations of elements during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0107] Numerical values ​​in the specification and claims of this application should be understood to include the same numerical value when reduced to the same number of significant digits, as well as numerical values ​​that differ from the stated value by less than the experimental error of conventional measurement techniques of the type described in this disclosure. All ranges disclosed herein include the stated endpoints.

[0108] The word "about" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "about" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also indicates a range "from 2 to 4". The word "about" may refer to plus or minus 10% of the number being referred to.

[0109] This disclosure relates to structures composed of different layers. When the terms "on" or "above" are used to refer to two different layers (including the substrate), they simply mean that one layer is on or above the other. These terms do not require that the two layers be in direct contact and allow other layers to be located between them. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" may be used to mean that two layers are in direct contact with each other without any other layers present. Furthermore, when referring to processing steps on or on the substrate, it should be understood, depending on the context, that such steps are performed on any layers that may be present on the substrate.

[0110] As used herein, the term "cantilever" refers to a projecting structure that is fixed at only one end.

[0111] This disclosure relates to a dual-capacitor leveling system particularly suitable for micro-electromechanical system (MEMS) structures, applicable to various components such as cantilevers and membranes. These structures often fail to maintain leveling (i.e., remain flat relative to a given reference plane) after release due to residual stress or changes in intra-wafer physical properties caused by process tooling. These structures can be sensitive, and the inability to maintain this capability can lead to performance degradation, especially for applications requiring symmetrical leveling of multiple cantilevers / membranes. Examples include roll-off, inconsistencies in operating voltage, or pressure losses during operation (which affect sensors). After the dies on the wafer are packaged, time-consuming post-calibration is required, and each die needs individual manual calibration.

[0112] This disclosure provides a novel system capable of determining the amount / degree of deformation of a cantilever beam or membrane upon back-side release, as well as the direction (positive or negative) of the deformation. This is useful, for example, in actuator and / or sensor designs. The electrical signal is stored in two capacitors. Upon reading, the bias voltage can be determined and then included along with the operating voltage to ensure consistent cantilever beam / membrane positioning during operation. This consistent positioning also reduces the stress requirements on the cantilever beam / membrane material itself.

[0113] Figure 1A This is a plan view of a first example implementation of a MEMS structure 101 for a sensor system, based on some embodiments disclosed herein. Figure 1B This is an enlarged view of a part of a MEMS structure.

[0114] First refer to Figure 1A In this example, the MEMS structure is formed on a grain 102 defined by cut lines 103. The structure illustrated here includes multiple cantilever beams / films 120 (eight are illustrated here) that together form a sensing system. Each cantilever beam 120 is electrically connected to its own dual-capacitor leveling system 280. Each cantilever beam also includes a piezoelectric capacitor 110. Each piezoelectric capacitor 110 includes a bottom electrode layer 112, a piezoelectric layer 114, and a top electrode layer 116. As shown here, the bottom electrode layer 112 covers the surface of the grain 102. The eight cantilever beams 120 each have a triangular shape and meet at the center of an opening (dashed circle 105). In this example, the cantilever beams can be used to sense fluid or gas passing through the opening. Cantilever beams are typically formed as a single section and then etched into two or more separate sections. However, this is just an example, and a structure with only one cantilever beam / film is also considered.

[0115] Now for reference Figure 1BOnly a cantilever beam 120 and a dual-capacitor leveling system 280 are shown here. The piezoelectric capacitor 110 is visible. The dual-capacitor leveling system 280 includes a first capacitor 310, a diode 350, and a second capacitor 360 electrically connected to the diode. Two metal pads 392 and 394 are electrically connected to provide a method for reading the charge stored in the first capacitor 310. Two metal pads 396 and 398 are electrically connected to provide a method for reading the charge stored in the second capacitor 360.

[0116] According to some embodiments disclosed herein, Figure 2A This is a side cross-sectional view of a dual-capacitor leveling system 280, showing a piezoelectric region 290 and a first capacitor region 300 including a first capacitor 310. Initially, a first dielectric layer 140 is present. An optional adhesive layer 150 is present on the first dielectric layer 140. A bottom electrode layer 160 is present on the first dielectric layer 140. These layers 140, 150, and 160 extend from a first end 282 of the leveling system to a second end 284 of the leveling system. (Back) Figure 1B The first end 282 of the leveling system is close to the cantilever beam 120.

[0117] Continuing the explanation, piezoelectric region 290 is located near the first end 282 of the leveling system, while the first capacitor region 300 is located near the second end 284 of the leveling system. In piezoelectric region 290, piezoelectric layer 170 contacts the bottom electrode layer 160 near the first end 282. Top electrode layer 180 also contacts the piezoelectric layer 170 near the first end 282. It is noteworthy that the upper surface 172 of piezoelectric layer 170 is exposed, but this is not necessary. It should also be noted that the bottom electrode layer 160, piezoelectric layer 170, and top electrode layer 180 of the dual-capacitor leveling system 280 are... Figure 1A and Figure 1B The bottom electrode layer 112, piezoelectric layer 114, and top electrode layer 116 of the piezoelectric capacitor 110 seen in the image are physically separate. In the first capacitor region 300, the bottom electrode layer 160 is not covered by the piezoelectric layer 170 or the top electrode layer 180.

[0118] An intermetallic dielectric (IMD) layer 210 is present, extending from the first end 282 of the leveling system to the second end 284 of the leveling system. The IMD layer 210 covers the top electrode layer 180 and the bottom electrode layer 160, removing two regions such that the top electrode layer 180 is exposed through the IMD layer in the piezoelectric region 290, and the bottom electrode layer 160 is exposed through the IMD layer in the first capacitance region 300. As will be explained further later, the IMD layer 210 is formed by depositing multiple IMD sublayers at different points in the semiconductor manufacturing process.

[0119] A first insulating film 220 is present in the first capacitor region. The first insulating film includes a raised first end 222, a raised second end 226, and a central region 224 between the two ends. The central region 224 contacts the exposed portion of the bottom electrode layer 160 and may be considered to be lower in height than the two ends. The raised first end 222 and the raised second end 226 rest on a portion of the IMD layer 210. A portion 217 of the IMD layer 210 is also present on the central region 224 of the first insulating film. The first end 222 and the second end 226 of the first insulating film are exposed through the IMD layer.

[0120] Next, a primary metal layer 330 exists on top of the IMD layer 210. The primary metal layer 330 also contacts the top electrode layer 180, the first end 222 of the first insulating film, and the second end 226 of the first insulating film through the IMD layer. A portion 217 of the IMD layer 210 exists on the central region 224 of the first insulating film to divide the primary metal layer 330 into two parts. Therefore, the combination of the primary metal layer 330, the first insulating film 220, and the IMD layer 210, along with the bottom electrode layer 160, forms a first metal-insulator-metal (MIM) capacitor 310. The first capacitor 310 is indicated by the dashed frame.

[0121] The top electrode layer 180 is electrically connected to a portion of the primary metal layer 330 on the first end 222 of the first insulating film. Then, a passivation layer 270 formed of dielectric material covers the piezoelectric region 290 and the first capacitance region 300. Above the central region 224 of the first insulating film, the passivation layer 270 contacts the IMD layer 210 and separates the two portions of the primary metal layer 330.

[0122] As previously described, two metal pads are provided to read the charge stored in the first capacitor 310. The first metal pad 392 is electrically connected to the primary metal layer 330. The second metal pad 394 is electrically connected to the bottom electrode layer 160 located in the first capacitor region 300. They are connected via interconnect 390.

[0123] Continuing, the first dielectric layer 140 is located above the substrate 130. The substrate 130 is located below the first capacitance region 300. However, the substrate is not located below the piezoelectric region 290.

[0124] According to some embodiments disclosed herein, Figure 2BThis is a side cross-sectional view of the dual-capacitor leveling system 280, showing the piezoelectric region 290 and the second capacitor region 340 including the second capacitor 360. Initially, the piezoelectric region 290 is located near the first end 282 of the leveling system, while the second capacitor region 340 is located near the second end 284. The first dielectric layer 140, optional adhesive layer 150, bottom electrode layer 160 are as previously described, as are the piezoelectric layer 170 and the top electrode layer 180 of the piezoelectric region. In the second capacitor region 340, the bottom electrode layer 160 is also not covered by the piezoelectric layer 170 or the top electrode layer 180. Again, the substrate 130 is located below the second capacitor region 340, but not below the piezoelectric region 290.

[0125] As seen in this cross-sectional view, the IMD layer 210 still extends from the first end 382 of the leveling system to the second end 384 of the leveling system. The IMD layer 210 still covers the top electrode layer 180 and the bottom electrode layer 160, and removes two regions so that the top electrode layer 180 is exposed through the IMD layer in the piezoelectric region 290, and the bottom electrode layer 160 is exposed through the IMD layer in the second capacitance region 340.

[0126] A diode 350 is present in the second capacitor region. This diode includes a raised first end 352, a raised second end 356, and a central region 354 between the two ends. The central region 354 contacts an exposed portion of the bottom electrode layer 160 and may be considered to be lower in height than the two ends. The raised first end 352 and the raised second end 356 rest on a portion of the IMD layer 210. A portion 218 of the IMD layer is also present on the central region 354 of the diode. One end of the diode is exposed through the IMD layer, while the other end of the diode remains covered by the IMD layer. As shown here, the second end 356 is exposed.

[0127] The secondary metal layer 370 contacts the exposed end of the diode. A second insulating film 250 covers the secondary metal layer 370. The second insulating film 250 includes a first end 252, a second end 256, and a central region 254 between the two ends. A tertiary metal layer 380 is present, contacting the top electrode layer 180, the first end 252 of the second insulating film, and the second end 256 of the second insulating film through the IMD layer. Above the central region 254 of the second insulating film, a portion 242 of the IMD layer 210 is present to divide the tertiary metal layer 380 into two parts. Therefore, the secondary metal layer 370, the second insulating film 250, and the tertiary metal layer 380 form a second MIM capacitor 360. The second capacitor 360 is indicated by the dashed frame.

[0128] The top electrode layer 180 is electrically connected to a portion of the tertiary metal layer 380 on the first end 252 of the second insulating film. The passivation layer 270 covers the piezoelectric region 290 and the second capacitance region 340. Above the central region 254 of the second insulating film, the passivation layer 270 contacts the IMD layer 210 and separates the two portions of the tertiary metal layer 380.

[0129] As previously described, two additional metal pads are provided to read the charge stored in the second capacitor 360. A third metal pad 396 is electrically connected to the tertiary metal layer 380. A fourth metal pad 398 is electrically connected to the bottom electrode layer 160 located in the second capacitor region 340. They are connected via interconnect 390. Notably, the circuitry thus extends through the second capacitor 360 and the diode 350.

[0130] According to some embodiments disclosed herein, Figure 2C This is a schematic plan view illustrating the various layers and their arrangement for each component in the dual-capacitor leveling system 280. This diagram has been manipulated to make all layers visible and should not be interpreted as providing information about the relative surface area of ​​each layer / component, or as representing the pyramidal shape of the various components in the actual structure. Furthermore, the passivation layer 270 is omitted. Therefore, the component depiction in this plan view will not strictly correspond to... Figure 2A and Figure 2B Side view.

[0131] exist Figure 2C In the diagram, piezoelectric region 290 is shown at the first end 282. First capacitor region 300 and second capacitor region 340 are separated on the X-axis by IMD layer 210, such that first capacitor 310 and second capacitor 360 are electrically isolated from each other (except through piezoelectric region 290 and bottom electrode layer 160). IMD region 219 separates piezoelectric layer 170 from first insulating film 220 and second insulating film 250 on the X-axis. Primary metal layer 330 is divided into two parts. Part 332 electrically connects top electrode layer 180 to first capacitor 310, and part 334 electrically connects top electrode layer 180 to second capacitor 360.

[0132] The four metal pads 392, 394, 396, and 398 can be made conductive from above, which is useful for wafer acceptance testing (WAT) and calibration. It is important to note that the position of the four metal pads relative to the two capacitors 310 and 360 is not critical, as long as they are electrically connected to the two capacitors 310 and 360 as described above.

[0133] Line AA passes through piezoelectric region 290 and first capacitance region 300. Line BB passes through piezoelectric region 290 and second capacitance region 340.

[0134] Figure 2DThis is a side sectional view illustrating the electrical interconnection between the piezoelectric capacitor 110 on the cantilever beam / membrane 120 and the dual-capacitor leveling system 280. (Refer to...) Figure 2C and Figure 2D The top electrode layer 116 of the piezoelectric capacitor 110 is electrically connected to the top electrode layer 180 of the piezoelectric region 290 in the dual-capacitor leveling system 280. Similarly, the bottom electrode layer 112 of the piezoelectric capacitor 110 is electrically connected to the bottom electrode layer 160 of the piezoelectric region 290 in the dual-capacitor leveling system 280. The piezoelectric capacitor 110 and the dual-capacitor leveling system 280 are physically separate. The electrical interconnects between these piezoelectric capacitors 110 and the dual-capacitor leveling system 280 can be, for example, AlCu interconnects in an interconnect layer (e.g., a redistribution layer, RDL). Here, the cantilever beam 120 is illustrated as being formed by a second dielectric layer 142, which may be different from the first dielectric layer 140.

[0135] According to some embodiments, Figures 3A-3D Together, they formed a flowchart illustrating a first method 400 for fabricating a dual-capacitor leveling system for cantilever beams. Some steps of this method are also... Figures 4-28 The diagrams are illustrated below. These diagrams provide different perspectives for better understanding. Although the methods and steps discussed below are for forming a single leveling system, this discussion should also be broadly understood to apply to forming multiple leveling systems simultaneously.

[0136] exist Figure 3A In step 405, and referring to Figure 4 A first dielectric layer 140 is formed on a substrate 130. In an optional step 410, an adhesive layer 150 is formed on the first dielectric layer. Then, in step 415, a bottom electrode layer 160 is formed on the adhesive layer or on the first dielectric layer. Figure 4 The resulting structure is illustrated, and optional adhesive layers are included.

[0137] The substrate 130 may be a wafer made of a semiconductor material. This semiconductor material may include silicon, such as silicon in crystalline Si form. In other embodiments, the substrate may be made of other basic semiconductors, such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In a particular embodiment, the substrate is silicon. Back Figure 1A It should be noted that although the entire die is typically fabricated on a substrate, for the purpose of discussing the fabrication of a dual-capacitor leveling system, the term "substrate" should be interpreted as referring only to the portion of the wafer on which the leveling system is fabricated, and not necessarily the entire wafer itself. For example, a photoresist layer may be applied to areas of the wafer that are not intended for the fabrication of a leveling system.

[0138] The first dielectric layer 140 can be formed by any suitable method, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, or other suitable methods. In certain embodiments, the first dielectric layer is made of silicon dioxide (SiO2). In some embodiments, the thickness of the first dielectric layer is from about 1 micrometer to about 3 micrometers, although other ranges and values ​​are also within the scope of this disclosure.

[0139] The selective adhesive layer 150 helps prevent the bottom electrode layer 160 from separating or peeling off from the first dielectric layer 140. The adhesive layer may also have dielectric properties. In some embodiments, the adhesive layer is made of a material that can act as a barrier layer to reduce or prevent bottom electrode material from entering the first dielectric layer 140. Some non-limiting examples of suitable materials for the adhesive layer include titanium dioxide (TiO2) and aluminum oxide (Al2O3). In some embodiments, the thickness of the adhesive layer is from about 200 angstroms to about 1500 angstroms, although other ranges and values ​​are also within the scope of this disclosure. The adhesive layer can also be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0140] The bottom electrode layer 160 can be formed of any conductive metal or conductive oxide. Suitable metals may include copper, aluminum, nickel, chromium, gold, germanium, silver, titanium, tungsten, platinum, tantalum, ruthenium, cobalt, rhenium, palladium, or zirconium; composites like TiN, WN, or TaN; or alloys like AlCu. Suitable conductive oxides may include indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), aluminum zinc oxide (AlZnO), indium oxide (InO), or cadmium oxide (CdO). The bottom electrode material can be deposited by evaporation or sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods. In some embodiments, the thickness of the bottom electrode layer is from about 1000 angstroms to about 3000 angstroms. In further embodiments, the impedance of the bottom electrode layer is less than 1000 ohms / sq. Other ranges and values ​​of these properties are within the scope of this disclosure.

[0141] Next, in Figure 3A Step 420 and as Figure 5As shown, a piezoelectric layer 170 is formed on top of the bottom electrode layer 160. The piezoelectric layer is typically made of piezoelectric ceramic. Suitable examples of ceramic materials may include lead zirconium titanate (PZT), aluminum nitride (AlN), potassium sodium niobate (KNN), or barium titanate (BTO). The piezoelectric layer can be formed by, for example, physical vapor deposition (PVD) or sol-gel deposition. In some embodiments, the thickness of the piezoelectric layer is from about 0.5 micrometers to about 3 micrometers, although other ranges and values ​​are within the scope of this disclosure.

[0142] Next, in Figure 3A Step 425 and as Figure 6 As shown, the top electrode layer 180 is formed on top of the piezoelectric layer 170. The discussion of the bottom electrode layer applies here as well.

[0143] Then, in Figure 3A In optional step 430, such as Figure 7 As shown, the top electrode layer 180 is patterned. Next, in... Figure 3A In optional step 435, such as Figure 8 As shown, the piezoelectric layer 170 is patterned. Patterning is typically performed by dry etching. As a result, the bottom electrode layer 160 is exposed from above. The portion still including the piezoelectric layer 170 and the top electrode layer 180 forms the piezoelectric region 290 of the dual-capacitor leveling system.

[0144] Please note that in Figure 8 In this process, a portion of the upper surface 172 of the piezoelectric layer 170 is also exposed, but this is not necessary. It should also be noted that these two patterning steps are optional. For example, the same resulting structure can be obtained by applying a photoresist layer near the second end 284 of the substrate and forming the piezoelectric layer 170 and the top electrode layer 180 only at the desired locations.

[0145] Next, in Figure 3A In step 440, the bottom electrode layer 160 is patterned and etched on the side of the grain. (Review) Figure 1A This etching is performed along the dicing path 103 and helps to subsequently separate individual grains on the wafer from each other.

[0146] Continue, as Figure 3A Step 445 and Figure 9A and Figure 9BAs shown, a first intermetallic dielectric (IMD) sublayer 190 is applied to the substrate. The first IMD sublayer 190 is a conformal layer that covers the top electrode layer 180, the piezoelectric layer 170, and the bottom electrode layer 160. In a particular embodiment, the IMD material is silicon dioxide (SiO2). The first IMD sublayer can be formed by any suitable method, including chemical vapor deposition or physical vapor deposition. In some embodiments, the thickness of the first IMD sublayer is from about 1000 angstroms to about 3000 angstroms, although other ranges and values ​​are within the scope of this disclosure.

[0147] Figure 9B This is a schematic plan view illustrating the various layers in the current manufacturing process. See here for reference. Figure 2C The piezoelectric region 290, including the piezoelectric layer and the top electrode layer, is indicated by a dashed box at one end of the substrate. The first capacitor region 300 and the second capacitor region 340 are also indicated by dashed boxes. The first IMD sublayer 190 covers the entire surface of the substrate.

[0148] Continue, as Figure 3B Step 450 and Figure 10 As shown, the first IMD sublayer 190 is patterned to expose the bottom electrode layer 160 in the first capacitor region 300. A recess 191 in the first IMD sublayer is visible here.

[0149] Next, as Figure 3B Steps 455 and Figure 11 As shown, a first insulating film 220 is applied to the substrate. As illustrated here, the first insulating film is a conformal film that covers the piezoelectric region 290 and the first capacitive region 300. The first insulating film is a dielectric material. Suitable materials may include hafnium dioxide (HfO2) or zirconium dioxide (ZrO2), although other dielectric materials may also be used. The first insulating film can be formed by any suitable method, such as ALD. In some embodiments, the thickness of the first insulating film is approximately 200 angstroms to approximately 500 angstroms, although other ranges and values ​​are also within the scope of this disclosure.

[0150] Continue, in Figure 3B Step 460 and Figure 12As shown, the first insulating film is patterned such that it exists only in the first capacitor region 300. As seen here, the first insulating film 220 remains within the recess 191 and on the portion of the first IMD sublayer 190 adjacent to the recess. The first insulating film can be described as including a first end 222, a central region 224, and a second end 226, which are connected together. The first and second ends can also be referred to as “protruding ends,” and / or the central region can be referred to as “lower central region.”

[0151] Then, in Figure 3B In step 465, such as Figure 13A As shown, the second IMD sublayer 194 is applied to the substrate. Figure 13A As seen, the second IMD sublayer 194 covers the first insulating film 220 of the first capacitor region 300. The second IMD sublayer is also a conformal layer and can be formed by any suitable method, including CVD or PVD. In some embodiments, the thickness of the second IMD sublayer is approximately 1000 angstroms to approximately 3000 angstroms, although other ranges and values ​​are within the scope of this disclosure. Notably, the two IMD sublayers form the thicker IMD layer 210 within the piezoelectric region 290.

[0152] continue, Figure 13B The diagram illustrates the second capacitance region 340 after the second IMD sublayer is applied to the substrate. In this regard, it is noteworthy that the various layers applied to the first capacitance region during steps 455-465 are also applied to the second capacitance region. The first IMD sublayer 190 acts as an etch stop layer during the patterning of the first insulating film. Therefore, the IMD layer 210 in the second capacitance region at this stage is formed by a combination of the first IMD sublayer 190 and the second IMD sublayer 194. Dashed lines are added to illustrate the contribution of each sublayer.

[0153] Next, in Figure 3C Step 470 and such Figure 14 As shown, the IMD layer 210 is patterned to expose the bottom electrode layer 160 in the second capacitor region 340. The recess 211 of the IMD layer is visible here.

[0154] Then, in Figure 3C Step 475 and as Figure 15As shown, diode layer 230 is applied to the substrate. As illustrated here, the diode layer is a conformal layer covering piezoelectric region 290 and second capacitive region 340. The diode layer is typically formed as a multi-film stack of p-type and n-type semiconductors. A non-limiting example of the material for the diode layer is a two-film stack of ZnO / ZnO:Al. The diode layer can be formed by any suitable means, such as PVD or ALD. In some embodiments, the thickness of the diode layer is approximately 200 angstroms to approximately 500 angstroms, although other ranges and values ​​are within the scope of this disclosure.

[0155] Continue, in Figure 3C Step 480 and Figure 16 As shown, the diode layer is patterned to form diode 350, such that the diode exists only in the second capacitor region 340. As seen here, diode 350 remains within recess 211 and on a portion of the IMD layer 210 adjacent to the recess. The diode can be described as comprising a first end 352, a central region 354, and a second end 356, which are connected together. The first and second ends can also be referred to as “raised ends,” and / or the central region can be referred to as “lower central region.” The first end 352 and the second end 356 can also be described as being located on the second IMD sublayer 194.

[0156] Then, in Figure 3C Step 485 and such Figure 17 As shown, the third IMD sublayer 198 is applied to the substrate. Figure 13A As shown, the third IMD sublayer 198 covers the diode 350 of the second capacitor region 340. The third IMD sublayer is also a conformal layer and can be formed by any suitable method, including CVD or PVD. In some embodiments, the thickness of the third IMD sublayer is approximately 1000 angstroms to approximately 3000 angstroms, although other ranges and values ​​are within the scope of this disclosure. Notably, the deposition of the third IMD sublayer increases the thickness of the piezoelectric region IMD layer 210.

[0157] Next, in Figure 3C Step 490 and such Figure 18 As shown, the third IMD sublayer 198 is patterned to expose the diode 350 located in the second capacitor region 340. The recess 199 in the third IMD sublayer is visible here, exposing the second terminal 356 of the diode.

[0158] Next, in Figure 3C Step 495 and such Figure 19As shown, a first metal layer 240 is applied to the substrate. The first metal layer can be any conductive metal previously described. The first metal layer is also a conformal layer and can be formed by any suitable method, such as PVD. In some embodiments, the thickness of the first metal layer is about 1000 angstroms to 3000 angstroms, although other ranges and values ​​are within the scope of this disclosure. As seen herein, the first metal layer 240 contacts the exposed second end 356 of the recessed diode 350.

[0159] Next, in Figure 3C Step 500 and such Figure 20 As shown, a second insulating film 250 is applied to the substrate. The second insulating film is a conformal film that covers the piezoelectric region 290 and the second capacitive region 340. The second insulating film is a dielectric material, as previously described with respect to the first insulating film. The second insulating film can be formed by any suitable method, such as ALD. In some embodiments, the thickness of the second insulating film is approximately 200 angstroms to 500 angstroms, although other ranges and values ​​are within the scope of this disclosure. The second insulating film 250 also extends into the recess 199 of the third IMD sublayer.

[0160] Continue, in Figure 3C Step 505 and Figure 21 As shown, the first metal layer 240 and the second insulating film 250 are patterned so that they exist only in the second capacitor region 340. As seen here, they remain within the recess 199 and on a portion of the third IMD sublayer 198 adjacent to the recess. A secondary metal layer 370 is formed in the patterned portion of the first metal layer in the second capacitor region.

[0161] Then, in Figure 3D Step 510 and as follows Figure 22 As shown, a fourth IMD sublayer 202 is applied to the substrate. The fourth IMD sublayer is also a conformal layer and can be formed by any suitable method, including CVD or PVD. In some embodiments, the thickness of the fourth IMD sublayer is approximately 1000 angstroms to approximately 3000 angstroms, although other ranges and values ​​are within the scope of this disclosure. The resulting structure of the first capacitance region 300 is shown on the left, and the resulting structure of the second capacitance region 340 is shown on the right.

[0162] As shown in the diagram of the first capacitor region 300 on the left, the deposition of the third IMD sublayer 198 and the fourth IMD sublayer 202 increases the thickness of the piezoelectric region and the IMD layer 210 in the first capacitor region 300 (compared to Figure 13). As shown in the diagram of the second capacitor region 340 on the right, the fourth IMD sublayer 202 covers the second insulating film 250 and the secondary metal layer 370.

[0163] As described above, the structure in the first capacitor region 300 is first formed in steps 450-465, while the structure in the second capacitor region 340 is formed in steps 470-505. These steps can be reversed. However, doing so would increase complexity because more steps are required, which could potentially reduce overall wafer yield.

[0164] Then, in Figure 3D Step 515 and as follows Figure 23 As shown, the IMD layer 210 of the piezoelectric region is patterned to expose the top electrode layer 180. A recess 212 in the IMD layer is visible here. Notably, the recess extends along the X-axis to be close to the first capacitor region 300 and the second capacitor region 340.

[0165] Next, in Figure 3D Step 520 and as Figure 24 As shown, the IMD layer 210 is patterned to expose the first end 222 and the second end 226 of the first insulating film 220 in the first capacitor region 300. Therefore, a portion 217 of the IMD layer remains between the first and second ends of the first insulating film. Similarly, in Figure 3D In step 525, the IMD layer is patterned to expose the first end 252 and the second end 256 of the second insulating film 250 in the second capacitor region 340. Therefore, a portion 218 of the IMD layer remains between the first end and the second end of the second insulating film. Figure 24 The resulting structures in the first capacitor region 300 and the second capacitor region 340 are illustrated. Recesses 213 and 214 exist in the first capacitor region 300, and recesses 215 and 216 exist in the second capacitor region 340. It should be noted that the two etching steps 520 and 525 can be performed in any order. They can also be performed simultaneously depending on the selectivity of the IMD layer material and the insulating film material.

[0166] Next, in Figure 3D Step 530 and as follows Figure 25 As shown, a second metal layer 260 is applied to the substrate. The second metal layer can be any conductive metal previously described and can be formed in the manner previously described. In some embodiments, the thickness of the second metal layer is about 10,000 angstroms to about 15,000 angstroms, although other ranges and values ​​are within the scope of this disclosure. As seen herein, the second metal layer fills the recess 212 above the top electrode layer 180 and the recesses 213, 214, 215, and 216 in the first capacitor region 300 and the second capacitor region 340.

[0167] Then, in Figure 3D Step 535 and as Figure 26As shown, the second metal layer is patterned to form a recess, exposing a portion 217 of an IMD layer between the first end 222 and the second end 226 of the first insulating film in the first capacitor region 300, and a portion 218 of an IMD layer between the first end and the second end of the first metal layer in the second capacitor region. Therefore, a first capacitor 310 is formed in the first capacitor region 300, and a second capacitor 360 is formed in the second capacitor region 340. (Reference) Figure 26 The first capacitor region 300 is shown on the left, and the second metal layer is formed thereon. Figure 2A The primary metal layer 330 mentioned above. Similarly, a second metal layer is formed in... Figure 2B The 380-layer tertiary metal layer mentioned above. Furthermore... Figure 2A and Figure 2B The metal pads 392, 394, 396, 398 and their electrical interconnects are also formed by the second metal layer, which is designated as step 540.

[0168] exist Figure 26 In the diagram, the second capacitor 360 is shown as being formed on the second terminal 356 of the diode. The second capacitor 360 can also be formed on the first terminal 352 of the diode with appropriate modifications to the process steps.

[0169] Continue, in Figure 3D Steps 545 and as follows Figure 27 As shown, a passivation layer 270 is applied to the substrate 130. The passivation layer is made of a dielectric material, and in one particular embodiment, it is formed of silicon nitride (SiN). The passivation layer can be made by any suitable method. In some embodiments, the thickness of the passivation layer is about 3000 angstroms to about 7000 angstroms, although other ranges and values ​​are within the scope of this disclosure. If desired, the passivation layer can be further patterned to obtain the desired shape.

[0170] Then, in Figure 3D Step 550 and as Figure 28 As shown, the substrate beneath the piezoelectric region 290 or piezoelectric layer 170 is removed to form the back-side cavity 134. (See previous text.) Figure 1A This step is typically performed in conjunction with removing the substrate from the cantilever beam 120 to obtain an opening in the grain. In other words, the piezoelectric layer and the top electrode layer are located outside the edge 132 of the substrate 130 or above the back cavity 134.

[0171] Ideally, chemical-mechanical planarization (CMP) was not used to form the dual-capacitor leveling system. The piezoelectric layer 170 is sensitive to the pressure applied during CMP, which could potentially cause problems that are desirable to avoid.

[0172] The structures and methods disclosed herein include a variety of different dielectric layers. These dielectric layers can generally be made of any suitable dielectric material or a combination thereof, although the properties of any particular layer may be further defined. Examples of dielectric materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon oxynitride (SiO2). x N y ), hafnium oxynitride (HfO) x N y ) or zirconium oxynitride (ZrO) x N y ), or hafnium silicates (ZrSi) x O y or zirconium silicates (ZrSi) x O y or silicon carboxynitride (SiC) x O y N z Alternatively, it could be hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), silicon nitride nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0173] It should also be noted that some conventional steps were not explicitly described in the above discussion. For example, a pattern / structure can be formed in a given layer by coating a photoresist layer, then patterning the photoresist layer, developing the photoresist layer, and then etching it.

[0174] Generally, photoresist layers can be applied using methods such as spin coating, spray coating, roller coating, dip coating, or extrusion coating. In a typical spin coating process, the substrate is placed on a rotating platform, which may include a vacuum chuck, to hold the substrate in place. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to uniformly diffuse the photoresist from the center of the substrate to its edges. By fixing the rotation speed of the platform, the final thickness of the photoresist layer can be controlled.

[0175] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, the baking temperature is approximately 90°C to 110°C. Baking can be performed using a hot plate or oven, or similar equipment. In this way, a photoresist layer is formed on the substrate.

[0176] The photoresist layer is then patterned by exposure to radiation. This radiation can be any wavelength of light carrying the desired shielding pattern. In a particular embodiment, EUV light with a wavelength of approximately 13.5 nanometers (nm) is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation while others are not. This exposure makes some portions of the photoresist soluble in the developer, while other portions remain insoluble.

[0177] After exposure to radiation, an additional photoresist baking step (post-exposure bake, or PEB) may be performed. For example, this may help release acid leaving groups (ALGs) or other molecules that are important in chemical amplification photoresist.

[0178] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. During the development step, the soluble portions of the photoresist layer are dissolved and washed away, leaving the photoresist pattern. A common example of a developer is the water-soluble tetramethylammonium hydroxide (TMAH). Generally, any suitable developer can be used. Sometimes, a post-development bake or "hard bake" may be performed to stabilize the developed photoresist pattern for optimal performance in subsequent steps.

[0179] Continuing, the portion of the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other stripping agents at elevated temperatures, or by dry etching using oxygen plasma.

[0180] Generally, any etching step described herein may use wet etching, dry etching, or plasma etching processes, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or combinations thereof, as applicable. Etching may be anisotropic. Depending on the material, etchants may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorocarbons, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), etc., or combinations thereof, in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4 and / or H2.

[0181] The resulting dual-capacitor leveling system 280 can be used for calibration. Figure 1A The cantilever beam 120 is illustrated in the figure. In this respect, after the substrate is etched to form a back-side cavity, the cantilever beam may deviate from the planar reference plane due to stress. Figure 29 Two diagrams of this stress are provided. As shown here, the tensile stress of the piezoelectric capacitor 110 on the Z-axis causes compression on the Y-axis, causing the cantilever beam 120 to bend upward relative to the substrate 130. Conversely, the compressive stress of the piezoelectric capacitor 110 on the Z-axis causes extension on the Y-axis, causing the cantilever beam 120 to bend downward.

[0182] Figure 29 Two circuit diagrams 590 are also provided, illustrating how the dual-capacitor leveling system provides information about the cantilever beam. A first capacitor 310, a second capacitor 360, a diode 350, and a piezoelectric capacitor 110 located on the cantilever beam are electrically connected as shown. The circuit diagram is a parallel circuit, comprising three parallel branches between two nodes. The first branch 592 includes the first capacitor 310. The second branch 594 includes the second capacitor 360 and the diode 350 connected in series. The third branch 596 includes the piezoelectric capacitor 110 located on the cantilever beam. When a back-side cavity is formed to release the cantilever beam, charge caused by any deformation or deflection is stored in the first capacitor 310 and the second capacitor 360. The voltage difference across the piezoelectric capacitor 110 will change direction depending on the presence of tensile or compressive stress. By reading the charge passing through the first and second branches, the degree and direction of deformation of the cantilever beam can be determined. Then, when the working voltage is applied, a bias voltage can be applied to the piezoelectric capacitor, so that the cantilever beam is flat on the desired reference plane.

[0183] According to some embodiments, Figure 30 It's a flowchart illustrating method 600 for leveling a cantilever beam. You can refer to it. Figure 29 Follow the steps.

[0184] In step 605, a cantilever beam is formed on the substrate. In step 610, a piezoelectric capacitor 110 is formed on the cantilever beam. In step 615, a three-branch parallel circuit 590 is formed between the piezoelectric capacitor and the previously described dual-capacitor leveling system. A first capacitor is located in the first branch 592, a diode and a second capacitor are connected in series with each other in the second branch 594, and the piezoelectric capacitor is located in the third branch 596. In step 620, the cantilever beam is released from the substrate. This results in charge being stored in the first and second capacitors. In step 625, the charge in the first capacitor is read through the first branch. In step 630, the charge in the second capacitor is read through the second branch. In step 635, the readings are used to determine the bias voltage applied to the piezoelectric capacitor to level the cantilever beam. This can be done using an algorithm. It is also considered that such calibration can be performed multiple times on multiple cantilever beams, and then based on the readings, the data can be used to extrapolate the required bias voltage for all other chips / wafers. In step 640, a bias voltage is applied to the operating voltage, which is then sent to the piezoelectric capacitor to level the cantilever beam during operation.

[0185] The MEMS components disclosed herein, including the dual-capacitor leveling system, offer several advantages. The position of the cantilever after the back cavity is released can be rapidly determined on the wafer during wafer acceptance testing, rather than after the die has been separated and packaged. The bias voltage to be included with the operating voltage can then be determined by an algorithm to ensure leveling during operation. This provides a consistent cantilever beam position, preventing issues such as roll-off, inconsistent operating voltages, and / or pressure losses that could affect sensor readings. Consistent membrane positioning also reduces reliance on stringent membrane stress requirements during manufacturing. MEMS components incorporating the cantilever beam / membrane and dual-capacitor leveling systems can be used for leak detection in systems requiring tight sealing, such as acoustic speakers, micropumps, or microvalves.

[0186] Some embodiments disclosed herein relate to a method for fabricating a dual-capacitor leveling system for a cantilever beam. A bottom electrode layer, a piezoelectric layer on the bottom electrode layer, and a top electrode layer on the piezoelectric layer are formed. A first capacitor is formed, comprising a bottom electrode layer, a first insulating film on the bottom electrode layer, and a primary metal layer on the first insulating film and electrically connected to the top electrode layer. A diode electrically connected to the bottom electrode layer is formed. A second capacitor is formed on the diode. The second capacitor comprises a secondary metal layer electrically connected to the diode, a second insulating film on the secondary metal layer, and a tertiary metal layer on the second insulating film and electrically connected to the top electrode layer. In one embodiment, the aforementioned primary metal layer of the first capacitor and the aforementioned secondary metal layer of the second capacitor are formed simultaneously. In one embodiment, the first capacitor is formed by: applying a first intermetallic dielectric (IMD) sublayer onto the bottom electrode layer; patterning the first IMD sublayer to expose the bottom electrode layer in a first capacitor region; forming a first insulating film on the bottom electrode layer in the first capacitor region, the first insulating film including a first end, a central region, and a second end; applying a second IMD sublayer to cover the first insulating film on the first capacitor region; patterning the second IMD sublayer to expose the first insulating film in the first capacitor region; and applying the primary metal layer onto the first insulating film to form the first capacitor. In one embodiment, the second capacitor is formed by: applying a first intermetallic dielectric (IMD) sublayer to the bottom electrode layer; patterning the first IMD sublayer to expose the bottom electrode layer in the second capacitor region; forming a diode in the second capacitor region; applying a third IMD sublayer to the second capacitor region; patterning the third IMD sublayer to expose the diode; forming a first metal layer on the exposed diode; forming a second insulating film on the first metal layer; and applying a tertiary metal layer on the second insulating film to form the second capacitor. In one embodiment, the method further includes: forming a first metal pad electrically connected to the primary metal layer of the first capacitor; forming a second metal pad electrically connected to the bottom electrode layer of the first capacitor; forming a third metal pad electrically connected to the tertiary metal layer of the second capacitor; and forming a fourth metal pad electrically connected to the bottom electrode layer below the diode. In one embodiment, the first capacitor and the second capacitor are formed on a substrate; and the piezoelectric layer and the top electrode layer are located outside the edge of the substrate. In one embodiment, the aforementioned method further includes forming the aforementioned bottom electrode layer on the first dielectric layer. In one embodiment, the aforementioned method further includes applying a passivation layer on the aforementioned first capacitor and the aforementioned second capacitor. In one embodiment, the aforementioned diode is formed of an n-type semiconductor and a p-type semiconductor. In one embodiment, the aforementioned piezoelectric layer comprises piezoelectric ceramic. In one embodiment, planarization is not used when forming the aforementioned first capacitor or the aforementioned second capacitor.In one embodiment, the aforementioned method further includes forming electrical interconnects from the aforementioned top electrode layer and the aforementioned bottom electrode layer to the piezoelectric capacitor on the aforementioned cantilever beam.

[0187] In various embodiments, a dual-capacitor leveling system for cantilever beams is also disclosed, comprising a piezoelectric region, a first capacitor, a diode, and a second capacitor. The piezoelectric region includes a bottom electrode layer, a piezoelectric layer on the bottom electrode layer, and a top electrode layer on the piezoelectric layer. The first capacitor includes a bottom electrode layer, a first insulating film on the bottom electrode layer, and a primary metal layer on the first insulating film and electrically connected to the top electrode layer. The diode is electrically connected to the bottom electrode layer. The second capacitor is located on the diode. The second capacitor includes a secondary metal layer electrically connected to the diode, a second insulating film covering the secondary metal layer, and a tertiary metal layer on the second insulating film and electrically connected to the top electrode layer. In one embodiment, the aforementioned system further includes: a first metal pad electrically connected to the aforementioned primary metal layer of the first capacitor; a second metal pad electrically connected to the aforementioned bottom electrode layer of the first capacitor; a third metal pad electrically connected to the aforementioned tertiary metal layer of the second capacitor; and a fourth metal pad electrically connected to the aforementioned bottom electrode layer below the diode. In one embodiment, the aforementioned system further includes an intermetallic dielectric (IMD) region separating the piezoelectric layer from the first insulating film and the second insulating film. In one embodiment, the first capacitor and the second capacitor are located above the substrate; and the piezoelectric region is not located above the substrate. In one embodiment, the aforementioned system further includes a piezoelectric capacitor located on the cantilever beam and electrically connected to the piezoelectric region.

[0188] Other embodiments disclosed herein relate to methods for fabricating a dual-capacitor leveling system. A first dielectric layer is formed on a substrate. An adhesive layer is formed on the first dielectric layer. A bottom electrode layer is formed on the adhesive layer. A piezoelectric layer is formed on the bottom electrode layer. A top electrode layer is formed on the piezoelectric layer. The top electrode layer and the piezoelectric layer are patterned to expose the bottom electrode layer. A first intermetallic dielectric (IMD) sublayer is applied to the substrate. The first IMD sublayer is patterned to expose the bottom electrode layer in a first capacitance region of the substrate. A first insulating film is formed in the first capacitance region, the first insulating film including a first end, a central region, and a second end. A second IMD sublayer is applied to the substrate to cover the first insulating film in the first capacitance region and form an IMD layer. The IMD layer is patterned to expose the bottom electrode layer in a second capacitance region of the substrate. A diode is formed in the second capacitance region, the diode including a first end, a central region, and a second end. A third IMD sublayer is applied to the substrate to cover the diode in the second capacitance region and extends to the IMD layer. The third IMD sublayer is patterned to expose the diode. A secondary metal layer is formed on the diode. A second insulating film is formed on a secondary metal layer. A fourth IMD sublayer is applied to the substrate to cover the second insulating film in the second capacitor region and is added to the IMD layer. The IMD layer is patterned to expose the top electrode layer. The IMD layer is patterned to expose the first and second ends of the first insulating film in the first capacitor region, with a portion of the IMD layer still located above the central region of the first insulating film. The IMD layer is also patterned to expose the first and second ends of the second insulating film in the second capacitor region, with a portion of the IMD layer still located above the central region of the second insulating film. A second metal layer is deposited on the substrate. The second metal layer covers the first and second ends of the first insulating film and the first and second ends of the second insulating film. Thus, a first capacitor is formed in the first capacitor region, and a second capacitor is formed in the second capacitor region. The substrate below the piezoelectric layer is then removed to form a back cavity. In one embodiment, the aforementioned method further includes: forming a first metal pad electrically connected to the second metal layer in the first capacitor region; forming a second metal pad electrically connected to the bottom electrode layer in the first capacitor region; forming a third metal pad electrically connected to the second metal layer in the second capacitor region; and forming a fourth metal pad electrically connected to the bottom electrode layer in the second capacitor region. In one embodiment, the aforementioned method further includes depositing a passivation layer on the substrate.

[0189] This disclosure also describes methods for leveling a cantilever beam in various embodiments. The cantilever beam is formed on a substrate. A piezoelectric capacitor is formed on the cantilever beam. A dual-capacitor leveling system is formed, comprising a first capacitor and a second capacitor having a diode connected in series. A three-branch circuit is formed, wherein the first capacitor is in the first branch, the diode and second capacitor connected in series are in the second branch, and the piezoelectric capacitor is in the third branch. The cantilever beam is then released from the substrate, such that charge is stored in the first and second capacitors. The charge passing through the first branch is read, and the charge passing through the second branch is read. These readings are performed by an algorithm to determine the voltage bias applied to the piezoelectric capacitor to level the cantilever beam.

[0190] Finally, this disclosure also relates to various embodiments of MEMS devices including a housing, a cantilever beam within the housing, a piezoelectric capacitor in contact with the cantilever beam, and a leveling system. The leveling system has the structure described above. In some embodiments, the housing is solid, and the cantilever beam is used to detect the presence of one or more leaks within the housing. In other embodiments, the housing also includes openings, and the cantilever beam can be used alone to cover the openings, or in combination with other cantilever beams, to cover the openings to detect fluid flow through the openings.

[0191] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purpose and / or obtain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made within this scope without departing from the spirit and scope of this disclosure.

Claims

1. A dual capacitance levelling system for a cantilever beam, characterised in that, comprising: a piezoelectric region comprising a bottom electrode layer, a piezoelectric layer on the bottom electrode layer, and a top electrode layer on the piezoelectric layer; a first capacitor comprising the bottom electrode layer, a first insulating film on the bottom electrode layer, and a primary metal layer on the first insulating film, the primary metal layer electrically connected to the top electrode layer; a diode electrically connected to the bottom electrode layer; and a second capacitor on the diode comprising a secondary metal layer electrically connected to the diode, a second insulating film on the secondary metal layer, and a tertiary metal layer on the second insulating film and electrically connected to the top electrode layer. further comprising:

2. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, a first metal pad electrically connected to the primary metal layer of the first capacitor; a second metal pad electrically connected to the bottom electrode layer of the first capacitor; a third metal pad electrically connected to the tertiary metal layer of the second capacitor; and a fourth metal pad electrically connected to the bottom electrode layer below the diode. further comprising an intermetallic dielectric (IMD) region separating the piezoelectric layer from the first insulating film and the second insulating film. wherein the first capacitor and the second capacitor are above a substrate; and wherein the piezoelectric region is not above the substrate.

3. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, further comprising a piezoelectric capacitor on the cantilever beam and electrically connected to the piezoelectric region.

4. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, further comprising electrical interconnects from the top electrode layer and the bottom electrode layer to the piezoelectric capacitor on the cantilever beam.

5. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, further comprising a first dielectric layer, wherein the bottom electrode layer is on the first dielectric layer.

6. The dual capacitance leveling system for a cantilever beam of claim 5, wherein, further comprising an adhesion layer on the first dielectric layer.

7. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, wherein the diode comprises an n-type semiconductor and a p-type semiconductor.

8. The dual capacitance leveling system for a cantilever beam according to claim 7, wherein, further comprising a passivation layer on the first capacitor and the second capacitor.

9. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, ​ 10. The dual capacitance leveling system for a cantilever beam of claim 1, wherein, ​

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