Integrated circuit

Abstract

The embodiment of the utility model provides an integrated circuit which comprises a plurality of active components operably coupled with each other to form the integrated circuit, and the plurality of active components are arranged above the front surface of a substrate; a plurality of dummy components, each of the plurality of dummy components being laterally disposed proximate one or more of the active components, where the plurality of dummy components are formed over the front face; the internal connection structure is arranged on the back surface of the substrate, is opposite to the front surface of the substrate, and is used for bearing power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and disposed laterally within a respective one of the active component or the dummy component; and a second via structure extending vertically through the substrate and extending laterally within a respective one of the dummy components, extending laterally along an edge between one of the active components and one of the dummy components, or extending laterally along an edge between the adjacent active components.

Description

Technical Field

[0001] Embodiments of this novel invention relate to an integrated circuit. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] Some embodiments of this invention provide an integrated circuit, comprising: a plurality of active components operably coupled to each other to form an integrated circuit, wherein the plurality of active components are disposed above a front side of a substrate; a plurality of dummy components, each of the plurality of dummy components being laterally configured adjacent to one or more of the active components, wherein the plurality of dummy components are formed above the front side; an interconnect structure disposed on a back side of the substrate, opposite to the front side of the substrate, and carrying a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a corresponding one of the active components or dummy components; and a second via structure extending vertically through the substrate and laterally extending within a corresponding one of the dummy components, laterally extending along an edge between one of the active components and one of the dummy components, or laterally extending along an edge between adjacent active components.

[0004] Furthermore, other embodiments of the present invention provide an integrated circuit, comprising: a plurality of active components operably coupled to each other to form an integrated circuit, wherein the plurality of active components are disposed above a front side of a substrate, and an interconnect structure is disposed on a back side of the substrate, opposite to the front side of the substrate, and carries a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a corresponding one of the active components; and a second via structure extending vertically through the substrate and laterally extending along an edge between one of the active components, or laterally extending along an edge between adjacent components of the active components. Attached Figure Description

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 A block diagram of an integrated circuit design system according to some embodiments is shown.

[0007] Figure 2 An exemplary flowchart of a method for operating an integrated circuit design system according to some embodiments is shown.

[0008] Figure 3 An example flowchart of a method for designing an integrated circuit according to some embodiments is shown.

[0009] Figure 4A and Figure 4B The layout design of an exemplary integrated circuit according to some embodiments is shown.

[0010] Figure 5 A cross-sectional view of an exemplary integrated circuit according to some embodiments is shown.

[0011] Figure 6 A cross-sectional view of an exemplary integrated circuit according to some embodiments is shown.

[0012] Figure 7 The layout design of an exemplary integrated circuit according to some embodiments is shown.

[0013] Figure 8 An example block diagram depicting the layout or analog integrated circuit according to some embodiments is shown.

[0014] Figure 9 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0015] Figure 10 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0016] Figure 11 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0017] Figure 12 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0018] Figure 13 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0019] Figure 14 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0020] Figure 15 The layout design of an exemplary integrated circuit according to some embodiments is shown.

[0021] Figure 16 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0022] Figure 17 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown.

[0023] Figure 18 An example system suitable for designing integrated circuits according to some embodiments is shown.

[0024] Figure 19 A block diagram illustrating an exemplary integrated circuit manufacturing system and manufacturing process according to some embodiments is shown.

[0025] Figure 20 An exemplary flowchart of a method for manufacturing an integrated circuit according to some embodiments is shown. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Because components in various embodiments may be positioned in multiple different orientations, directional terms are for illustrative purposes only and are in no way limiting. When used in conjunction with layers of integrated circuits, semiconductor devices, or electronic devices, directional terms are intended to be interpreted broadly and should not be construed as excluding the presence of one or more intervening layers or other intervening features or components. Therefore, a given layer described herein as being formed on, above, or below another layer, or situated on, above, or below another layer, can be separated from the subsequent layer by one or more additional layers.

[0028] Although the functionality of integrated circuits has shrunk, the pre-simulation of the effects of physical / layout aspects in integrated circuit design has become increasingly popular. For integrated circuit design, process design kits (PDKs) or process access kits (PAKs) are commercially available for building integrated circuits. Generally, a PDK includes a geometric description and device model, such as transistors, diodes, resistors, capacitors, etc. Circuit design engineers convert the PDK into transistor netlists and / or gate-level netlists for circuit simulation, such as simulations using a Simulation Program with Integrated Circuit Emphasis (SPICE). Based on the simulation results, circuit design engineers predict and / or modify the integrated circuit design.

[0029] The embodiments disclosed herein provide techniques for automatically generating layouts of analog integrated circuits. Integrated circuits are typically constructed using cells, where cells may include some or all of the circuitry or components. An analog cell is a cell in which some or all of the cells include analog circuitry or analog components. In some embodiments, an analog cell may include one or more definable parameters (e.g., parameter values ​​may vary). In some embodiments, analog cells may have a more uniform structure. In one embodiment, some or all of the non-final layout of the integrated circuit is constructed using analog cells.

[0030] In analog design, power and ground (P / G) and signals can be routed on the front end of integrated circuits. However, this approach often encounters challenges related to limited wiring area, leading to significant voltage drop (IR drop) issues within analog circuits. The area loss on the front side of integrated circuits necessitates the use of superpower rails (SPRs) as a solution. However, introducing SPRs requires careful consideration of how to implement backside vias (VBs) and feed-through vias (FTVs). These components play a crucial role in effectively connecting different layers and sides of the circuit, ensuring seamless power delivery and signal routing.

[0031] In the context of Super Power Rail (SPR) processes, the placement of bumps formed on the back side of integrated circuits presents a unique set of challenges. A solution is urgently needed to efficiently route signals to the back side, ensuring seamless operation of analog components. Furthermore, FTV designs raise the issue of high-density cut metal gate (CMG) structures, where the basic rule is typically set at approximately 25%, resulting in CMG densities ranging from approximately 71% to approximately 35%. This increased CMG density introduces process risks that require careful consideration and mitigation strategies.

[0032] Furthermore, the SPR process aims to eliminate the limitations imposed by this rule, which can potentially affect the overall design and performance of analog circuits. Therefore, in-depth impact assessments are crucial for evaluating the consequences and adapting to the evolving requirements of this process.

[0033] This disclosure introduces a novel proposal for routing VB and FTV signals to the back side, providing a unique method for efficiently routing signals in this manner. Additionally, this disclosure employs a dual CMG structure to mitigate challenges associated with high polycrystalline cut (CPO) density. Another innovation includes a redesigned guard ring (GR) structure that eliminates regular constraints, resulting in a significant area saving of approximately 3.71% within the analog cube.

[0034] The advantages and benefits of these features are significant. Cell-to-cell FTV integration does not incur additional area loss, promoting efficient space utilization. Ensuring consistent parasitic resistance (R) for each finger improves mismatch characteristics, thereby enhancing overall performance. Furthermore, the implementation of back-side routing for power, ground, and / or signal connections effectively reduces IR drop issues, contributing to improved robustness and reliability of analog circuits. This disclosure introduces Super Power Rail (SPR) analog cells and establishes an automated migration process using a one-to-one cell mapping approach to ensure compliance with design rules.

[0035] Figure 1 A block diagram of an integrated circuit design system according to some embodiments is shown. The integrated circuit design system 100 may be part of a PDK implemented using EDA tools. It should be understood that... Figure 1 The block diagrams are simplified for illustrative purposes; therefore, the integrated circuit design system 100 may include any of a variety of other components / blocks while still remaining within the scope of this disclosure.

[0036] The integrated circuit design system 100 can reduce the number of iterations performed during the layout design process by providing a unique and complete design flow that autonomously merges multiple device array layouts and generates CAD layers to surround the merged device array layouts. The integrated circuit design system 100 also allows dummy patterns to be inserted around the CAD layers to verify the accuracy of the electrical design or performance of the layout compared to design specifications.

[0037] As shown in the figure, the integrated circuit design system 100 includes a schematic editor 102, a layout editor 104, a user interface 106, a device array editor 108, and a design rule constraint database 110, which are communicatively coupled to each other. In various embodiments disclosed herein, the schematic editor 102, the layout editor 104, and the device array editor 108 may each include one or more sets of executable instructions executed by at least one processor or similar device.

[0038] Schematic editor 102 can generate and edit schematic designs of integrated circuits (e.g., circuits) under design. Schematic editor 102 can perform pre-layout simulations (e.g., SPICE simulations with integrated circuit focus) on the schematic design. According to various embodiments, schematic editor 102 includes a set of executable instructions for generating or inducing pre-layout simulations of the schematic design. In other embodiments, a separate device (e.g., a simulator) communicating with schematic editor 102 can generate pre-layout simulations of the schematic design. Layout editor 104 can generate and edit the layout of integrated circuits (e.g., device array layouts) based on the schematic design generated by schematic editor 102. References will follow. Figure 2 The method will be discussed in more detail regarding the components of the integrated circuit design system 100.

[0039] User interface 106 can receive and display circuit schematics from schematic editor 102, layouts can receive and display circuit schematics from layout editor 104, and any calculated circuit performance parameters. User interface 106 can receive user input to adjust circuit schematics, device array layouts, and integrated circuit layouts, and select specific devices to display the circuit performance parameters of the user-selected specific devices.

[0040] Figure 2 A flowchart of an exemplary method 200 for designing an integrated circuit according to various embodiments is shown. Method 200 can be derived from... Figure 1 The integrated circuit design system 100 is used to execute this method; therefore, the following discussion of method 200 will sometimes refer to... Figure 1Components (e.g., schematic editor 102, layout editor 104). It should be noted that method 200 is merely an example and is not intended to limit this invention. Therefore, it should be understood that... Figure 2 Method 200 provides additional operations before, during, and after, and some other operations can be simply described here.

[0041] Method 200 can generate a schematic design of an integrated circuit starting from operation 210. In various embodiments, schematic editor 102 can generate the schematic design based on a set of design rule constraints. Schematic editor 102 can query an applicable set of design rules in design rule constraint database 110 and generate the schematic design of the integrated circuit. The schematic of the integrated circuit can include multiple circuit components. The multiple components can be operatively coupled to each other. At least one of the multiple components can be electrically coupled to a power supply voltage. For example, each circuit component can be represented as a transistor, which can be implemented as an analog cell by integrated circuit design system 100. In some other embodiments, the circuit components can be implemented as any of a variety of other analog cells, while still within the scope of this disclosure. The schematic of the integrated circuit can also include layout-dependent effect (LDE) related information for each circuit component in a component description format (CDF). LDE related information can include the dimensions of the individual features of the circuit components (e.g., the number of active regions, channel width, channel length, number of gate structures, gate oxide thickness, etc., which can be implemented as fin structures).

[0042] In various embodiments, LDE-related information may include matching groups (MGs) of one or more circuit components, which may be defined by or otherwise received by the schematic editor 102. Specifically, matching groups may be associated with corresponding circuit functions. Such matching groups may be user-defined by the integrated circuit design system 100. For example, a matching group may include one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a frequency-sensitive circuit. In some embodiments, LDE-related information may optionally include the size of the component array layout corresponding to the individual circuit components.

[0043] Next, method 200 can proceed to operation 220, performing pre-layout simulation on the schematic design of the integrated circuit. In various embodiments, the schematic editor 102 can simulate the schematic design of the integrated circuit. The pre-layout simulation can be performed on a simulator, such as one commercially available from Synopsys, Inc. (San Jose, California). Available commercially from Cadence Design Systems, Inc. (San Jose, California) Or any commercially available pre-layout simulator. After the pre-layout simulation is completed, the layout of the integrated circuit can be generated by the layout editor 104, including one or more CAD layers, each of which defines the boundaries of certain active circuit components, which will be discussed in detail below.

[0044] Furthermore, in various embodiments, the schematic editor 102 can simulate the schematic design based on matching groups of the schematic design with corresponding scaling factors. For example, the schematic editor 102 can identify whether each circuit component is associated with a corresponding matching group. If so (i.e., associated with a specified matching factor), the schematic editor 102 can run pre-layout simulations (including Monte Carlo simulations) with a relatively small factor; if not (i.e., associated with no matching factor), the schematic editor 102 can run pre-layout simulations (including Monte Carlo simulations) with a relatively large factor.

[0045] Next, method 200 can proceed to operation 230 to generate a design layout for the integrated circuit. In various embodiments, layout editor 104 can generate the layout based on the schematic design (generated at operation 210) and pre-simulation results (generated at operation 220). For example, layout editor 104 can initially use a tool such as those commercially available from Cadence Design Systems, Inc. (San Jose, California). Platforms like these generate layouts based on schematic design and pre-simulation results. A layout can include multiple adjacent cells. Each of the multiple components may correspond to a corresponding cell. Simultaneously or subsequently, the layout editor 104 can update, adjust, or otherwise modify the layout by adding interconnect structures (e.g., super power rails (SPRs)), one or more feedthrough vias (FTVs), and / or one or more via structures (VBs), such as operations 232, 234, and 236.

[0046] For example, in operation 232, layout editor 104 may determine a first pattern. The first pattern may be one or more interconnect structure locations. The first pattern may be configured to form interconnect structures. The interconnect structures may be disposed on the back side of the substrate opposite the front side of the substrate and may carry power supply voltages. In some embodiments, the interconnect structure may be a super power rail (SPR). An SPR may refer to a dedicated power distribution network or power rail designed to efficiently deliver power to various components and portions within an integrated circuit.

[0047] In operation 234, the layout editor 104 can determine multiple second patterns, which will refer to... Figure 4A and Figure 4B This will be discussed in more detail. The second pattern location can be the via VB location. Each of the plurality of second patterns can be configured to form a first via structure. In some embodiments, the first via structure can be a via VB. The first via structure can electrically couple a power supply voltage to one or more components (e.g., a transistor). The first via structure can have a first resistance.

[0048] In operation 236, layout editor 104 can determine the third pattern, which will refer to... Figure 4A and Figure 4B This will be discussed in more detail. The third pattern can be configured as a second via structure. The second via structure can be one or more feedthrough vias (FTVs). The second via structure can electrically couple a power supply voltage to one or more components (e.g., transistors). The second via structure can have a second resistance that is significantly lower than the first resistance.

[0049] Next, method 200 can proceed to layout verification operation 240. In various embodiments, the integrated circuit design system 100 may include multiple verification tools to verify or otherwise inspect the layout. Examples of such inspections include design rule checks (DRC), layout-versus-schematic (LVS) checks (e.g., layout vs. schematic comparison), layout parasitic extraction (LPE) (e.g., MOS, resistors, capacitors, inductors, and / or other semiconductor devices), resistance and capacitance extraction (RCX) (e.g., interconnect parasitic resistance and capacitance extraction for timing simulation), and other verification steps.

[0050] After the layout (or corresponding schematic design) passes inspection, method 200 can proceed to operation 250 to perform post-layout simulation of the integrated circuit schematic design. In various embodiments, the schematic editor 102 can simulate the integrated circuit schematic design. Post-layout simulation can be performed on a simulator, such as one commercially available from Synopsys, Inc. (San Jose, California). Available commercially from Cadence Design Systems, Inc. (San Jose, California) Or any commercially available pre-layout simulator.

[0051] In post-layout simulation, various layout-related effects are considered, ensuring that the generated circuit performance parameters more accurately reflect the actual circuit. These performance parameters are then compared to the design specifications related to the schematic design. If the circuit performance parameters meet the design specifications, the schematic design is approved. Otherwise, the design process returns to the schematic generation and editing steps, which include pre-layout simulation (operation 220), layout creation (operation 230), design verification (operation 240), and post-layout simulation (operation 250). The schematic design is then modified repeatedly. This process is repeated until the circuit performance parameters meet the design specifications.

[0052] Figure 3 The summary of various embodiments is shown by integrated circuit design system 100 ( Figure 1 The above operations are performed by one or more components of ) Figure 2 At least some of the methods in the 300 flowchart. Furthermore, Figure 4A and Figures 4B-17 Together, they provide an example integrated circuit designed through method 300, therefore, they will combine Figure 4A and Figures 4B-17 The following discussion provides an explanation of method 300. It should be noted that method 300 is merely an example and is not intended to limit the scope of this invention. Therefore, it should be understood that other methods can be applied... Figure 3 Method 300 provides additional operations before, during, and after, and some other operations can be simply described here.

[0053] In various embodiments, method 300 may begin with operation 310, wherein a schematic of an integrated circuit is received by layout editor 104. This schematic may include multiple components (e.g., transistors) operatively coupled to each other. At least one of the multiple components may be electrically coupled to a power supply voltage. Multiple components may be formed on the front side of a substrate.

[0054] Next, method 300 can proceed to operation 320, where layout editor 104 can generate a layout based on the schematic of the integrated circuit. The layout may include a plurality of adjacent cells. Each of the plurality of components may correspond to a corresponding one of the plurality of cells. In some embodiments, operation 320 may also determine a first pattern (e.g., BMO). The first pattern may be configured to form an interconnect structure disposed on a back side of the substrate opposite the front side of the substrate. The interconnect structure may carry a power supply voltage. The interconnect structure may extend along a first lateral or a second lateral. In some embodiments, operation 320 may also determine a plurality of second patterns. Each of the plurality of second patterns may be configured to form a first via structure (e.g., via VB) electrically coupling a power supply voltage to one or more components. The first via structure may have a first resistance. In some embodiments, operation 320 may also determine a third pattern. The third pattern may be configured to form a second via structure (e.g., FTV). The second via structure electrically couples a power supply voltage to one or more components. The second via structure may have a second resistance significantly lower than the first resistance.

[0055] For example, in Figure 4A and Figure 4B In this configuration, layout editor 104 can generate layout 400a or layout 400b. In some embodiments, layout 400a or layout 400b may also include: a first of one of a plurality of cells 402 corresponding to one or more components; and a second of the plurality of cells 404 disposed adjacent to the first cell along a first lateral direction (e.g., the X direction) or a second lateral direction (e.g., the Y direction). The first cell 402 may include a pair of first active regions 406 extending along the first lateral direction (e.g., the X direction). The second cell 404 may include a pair of second active regions 408 extending along the first lateral direction (e.g., the X direction). Each second pattern 410 (e.g., VB) may extend from a first edge 410a to a second edge 410b of a corresponding one of the first active regions 406 and the second active regions 408 along the second lateral direction (e.g., the Y direction).

[0056] In some embodiments, the third pattern 412 (e.g., between cells FTV) may extend along the edge between the first cell 402 and the second cell 404 in a first lateral direction (e.g., the X direction), such as Figure 4AAs shown. In some embodiments, the third pattern 412 (e.g., between cell FTVs) may extend along the edge between the first cells 402 in a first lateral direction (e.g., the X direction). The cell FTV design may involve strategically placing the FTV cells at the center of the oxide diffusion (OD). VB can connect the back power / ground to the front circuit source, while VD / VDR connects MD to M0. Isolation between the source or drain sidewalls prevents short circuits, and an open circuit in MD isolates the source or drain. Precautions are taken to prevent direct connections between PO and FTV cells to ensure reliable integration.

[0057] In some embodiments, the third pattern 412 (e.g., intracellular FTV) may extend along a first lateral direction (e.g., the X direction) between a pair of second active regions 408 of the second cell 404, such as Figure 4B As shown. A guard ring (GR) (e.g., within a cell) FTV design may involve positioning the FTV cell within an analog GR. VD or VDR connections may overlap with MD to enable connections to M0. M1 connections may be established perpendicular to the inner GR and may provide connections to multiple components (e.g., transistors).

[0058] Figure 5 A cross-sectional view of an exemplary integrated circuit (with a through-hole VB) 500 according to some embodiments is shown. The integrated circuit 500 may include a bottom metal layer 0 (BM0) 502, a through-hole VB (VB) 504, a source or drain (S / D) 506, a metal layer (MD) 508, a VD 510, a metal layer 0 (M0) 512, and a metal layer 1 (M1) 514. BM0 502 can act as a base layer for routing signals and power throughout the circuit. The through-hole VB 504 can provide a bridge between components on the back and front sides of the circuit, thereby facilitating communication and power distribution. The S / D 506 can play a key role in controlling the current within these devices. The MD 508 can facilitate interconnecting components and routing signals. The VD 510 can enable vertical data transfer between different circuit layers, such as from the MD 508 to the M0 512. The M0 512 and M1 514 can provide connectivity and routing components. In some embodiments, via VB 504 can connect the rear power / ground to the front circuit source, while VD / VDR 510 can connect to MD 508 to M0512. Separation between the sidewalls of the source or drain 506 prevents short circuits, and a break in MD 508 isolates the source or drain.

[0059] Figure 6A cross-sectional view of an exemplary integrated circuit (with FTV) 600 according to some embodiments is shown. The integrated circuit 600 may include a bottom metal layer 0 (BM0) 602, a feedthrough via (FTV) 604, a metal layer (MD) 608, a VD 610, a metal layer 0 (M0) 612, and a metal layer 1 (M1) 614. BM0 602 can act as a base layer for routing signals and power throughout the circuit. FTV 604 can enable connections between different layers or sides of the integrated circuit. MD 608 can facilitate interconnect components and signal routing. VD 610 can enable vertical data transfer between different circuit layers, such as from MD 608 to M0 612. M0 612 and M1 614 can provide connection and routing components. Compared to via VB 504, FTV 604 can have lower via resistance.

[0060] Figure 7 This describes the transition from a non-super power rail (SPR) to an SPR in an N2 analog cell. This transition may involve specific methods of implementing back-side vias (VB) and feed-through vias (FTV).

[0061] VB Method: In this process, a direct connection to the source can be established using a 702 via on the back, ensuring that the front-end trace (FEOL) of the non-SPR cell remains unchanged. The key here is to rewire power and ground from the back while maintaining the integrity of the main functions, such as... Figure 7 As shown.

[0062] FTV (Fixed-to-Vessel) Approach: When dealing with small oxide diffusion (OD) widths, FTVs can be seamlessly merged through cell-cell mapping, effectively filling available space. For scenarios with large OD widths, interconnection can be achieved by connecting FTVs via nearby inner guard rings (GRs). This approach optimizes FTV layout and routing based on OD width, ensuring efficient signal transmission and power distribution within SPR (Simulated Resonance Processing) analog cells.

[0063] Figure 8 An exemplary block diagram of a simulation cell layout / structure according to some embodiments is shown. In some embodiments, the simulation cell layout 800 includes multiple cells. Cells can be of different cell types. Cell types may include guard ring_C (corner simulation guard ring), guard ring_V (vertical simulation guard ring), guard ring_H (horizontal simulation ring), guard ring_I (inner simulation guard ring), and active simulation Cell_A (simulation cell). Corner / horizontal / vertical / inner guard rings may be adjacent to outer guard ring blocks. These cells can employ a guard ring structure to encapsulate analog circuitry, providing protection against noise interference while meeting latch-up protection (LUP) requirements.

[0064] In the illustrated embodiment, the simulated cell layout 800 may include a fill region 804. Fill cells (guard rings_I) 806, 808, 810, 812, and 814 may be inserted into the fill region 804. Although Figure 8 The illustration shows a specific number of guard rings_C, guard rings_V, guard rings_H, active simulation cells_A, and filler cells (guard rings_I), but other embodiments are not limited to this implementation. Additionally, the shape of the filler region 804 can be shown as a cross or a "+" shape. In other embodiments, the filler region can have any suitable shape. For example, the shape of the filler region 804 can be a square, a rectangle, a rectangle elongated along a horizontal or vertical direction (e.g., along a row or column), an "L" shape, or a "T" shape.

[0065] In one embodiment, fill cells 806, 808, 810, 812, and 814 may be inserted as a result of changes to a non-final layout. These changes may be described in engineering change orders or requests and / or other documents documenting design changes. Therefore, the number and / or placement of fill cells may change over time (e.g., for each change or for selected changes). A fill cell may include one or more components included in an active cell, but these components are not used or functioning within the fill cell. Alternatively, a fill cell may be a blank area without any components.

[0066] Figure 9 An exemplary super power rail (SPR) simulation cell layout 900 according to some embodiments is shown. Layout 900 corresponds to... Figure 4A The shown is a feed-through-cell (FTV) layout 400a. Layout 900 may include multiple active components 402, multiple dummy components 404, and interconnect structures ( Figure 9 (Not shown in the image) Multiple first via structures 410 and second via structures 412. Multiple active components 402 can be operatively coupled to each other to form an integrated circuit 900. The multiple active components can be disposed above the front side of the substrate. Multiple dummy components 404 can each be laterally configured adjacent to one or more active components 402. The multiple dummy components can be formed above the front side. Interconnect structures 502 and 602 can be disposed on the back side of the substrate opposite to the front side of the substrate, such as... Figure 5 and Figure 6 As shown. Multiple first via structures 410 can each extend vertically through the substrate, such as... Figure 5 As shown. Multiple first through-hole structures 410 can be laterally arranged within a corresponding one of the active components or dummy components, such as... Figure 9 As shown. The second via structure 412 can extend vertically through the substrate, as... Figure 6As shown. The second through-hole structure 412 can extend laterally within a corresponding one of the dummy components 412, and laterally along the edge between one of the active components 402 and one of the dummy components 404, or laterally along the edge between adjacent active components 402, as shown. Figure 9 As shown.

[0067] In some embodiments, the second via structure 412 (e.g., between cell FTVs) may extend along the edge between the first cells 402 in a first lateral direction (e.g., the X direction). In some embodiments, the second via structure 412 (e.g., between cell FTVs) may extend along the edge between the first cell 402 and the second cell 404 in a first lateral direction (e.g., the X direction). In some embodiments, the second cell 404 may form part of a protective ring for a plurality of components (e.g., transistors).

[0068] Figure 10 An exemplary super power rail (SPR) simulated cell layout 1000 according to some embodiments is shown. Figure 10 The layout of 1000 is basically similar Figure 4A Layout 400a and Figure 4B The layout 400b, apart from the settings of the interconnecting structures (e.g., horizontal BM0) and the second pattern 410 (e.g., through-hole VB), is similar to the specific operation of other components, which has been discussed in detail in the paragraphs above and will be omitted here for the sake of brevity, unless it is necessary to introduce related concepts. Figure 10 The components are shown in their operational relationship. An interconnecting structure 1002 (e.g., BMO) may extend along a first lateral direction (e.g., the X-axis). A plurality of second patterns 410 (e.g., through-holes VB) may be positioned relative to each other along an oblique direction between the first (e.g., the X-axis) and second (e.g., the Y-axis) lateral directions.

[0069] Figure 11 An exemplary super power rail (SPR) simulated cell layout 1100 according to some embodiments is shown. Figure 11 The layout of 1100 is basically similar. Figure 4A Layout 400a and Figure 4B The layout 400b, except for the settings of the interconnecting structures (e.g., vertical BM0) and the second pattern 410 (e.g., through-hole VB), is similar to the one described above. The specific operations of such components have been discussed in detail above and will be omitted here for brevity, unless it is necessary to introduce them in conjunction with... Figure 11 The components are shown in their operational relationship. An interconnecting structure 1002 (e.g., BMO) may extend along a second lateral direction (e.g., the Y-axis). Some of the plurality of second patterns 410 (e.g., through-holes VB) may be aligned with each other along the second lateral direction (e.g., the Y-axis).

[0070] Figure 12 An exemplary super power rail (SPR) simulated cell layout 1200 according to some embodiments is shown. Figure 12 The demonstration shows the routing of the power switch signal into and out of the back of BM0. For the source signal, there are two paths: one through BM0, FTV, MD, and EPI, and the other through BM0 and VB, ultimately connecting to EPI. For the drain signal, the drain signal can follow one of two routes: one through EPI, MD, and FTV, returning to BM0, and the other through EPI and VB, also connecting to BM0.

[0071] Figure 13 An exemplary super power rail (SPR) simulated cell layout 1300 according to some embodiments is shown. Figure 13 An SPR analog cell layout 1300 for implementing a dual-cut metal gate (CMG) in an analog SPR design is demonstrated. Dual CMGs can be used to prevent unintended connections (e.g., source or drain connections) between the gate mesh and the feedthrough via (FTV). Large CMG structures can present challenges associated with high CMG densities, leading to process risks. However, by employing a dual CMG strategy, the design becomes more process-friendly, effectively mitigating the problems associated with excessive CMG density. The SPR analog cell layout 1300 ensures reliable and efficient operation in analog SPR configurations while maintaining design integrity.

[0072] Figure 14 An exemplary super power rail (SPR) simulated cell layout 1400 according to some embodiments is shown. Figure 14 Visual representations of various strategies designed to optimize the utilization of space within a design are presented. The relaxation of tapping rules in SPR design is demonstrated, allowing for a more compact layout. Furthermore, Figure 14 The reduction in the analog guard ring is shown, which is crucial for circuit protection and helps to make efficient use of space. Another optimization involves removing the vertical guard ring within the OD structure, retaining only the boundary shell, which simplifies the design while saving space. The SPR analog cell layout 1400 shows an area saving of approximately 33.25% for the near-pad guard ring (Pad-GR) and approximately 3.87% for the OD injector in the overall design, highlighting the importance of these area-saving strategies in achieving an efficient SPR configuration.

[0073] Figure 15 and Figure 16Layout designs of exemplary integrated circuits 1500 and 1600, according to some embodiments, are illustrated by utilizing analog cell SPR FTVs as heat sinks. This design is driven by specific background considerations, including issues related to electromigration (EM) requiring adjustments to cell height or M0 track width. Furthermore, various threshold voltage (VT) adjacency requirements need to be met. Additionally, the lack of a good pick-up mechanism in SPR configurations raises concerns about self-heating delta-T. To address these challenges, this disclosure repurposes inter-cell FTVs as effective heat sinks. Guiding principles are proposed to facilitate proper placement of GR-FTV structures, particularly in high-current and electromagnetically dense environments. Furthermore, double-sided signal wiring can provide source / drain (S / D) and epitaxial (EPI) layers as heat sinks, thereby enhancing thermal management within analog cell SPR configurations.

[0074] Figure 17 An exemplary super power rail (SPR) simulated cell layout according to some embodiments is shown. Figure 17 This disclosure presents a method for enhancing thermal management. This can be achieved by effectively thickening the bottom metal layer 0 (BM0) 1702, thereby expanding the heat sink's channels. In addition to thickening BM0 in the vertical direction, it is noteworthy that BM0 can be configured with different widths along the Y-axis, such as... Figure 17 As shown in 1702 and 1704. Each of these configurations extends horizontally across the entire OD. It should be emphasized that... Figure 17 The representations in the text are primarily for illustrative and comparative purposes, showcasing various width configurations of BM0 to illustrate design possibilities.

[0075] The layout employs feedthrough vias (FTVs) connected to a thickened BM01704, facilitating an efficient heat dissipation mechanism within the integrated circuit. This design incorporates guidelines for arranging guard rings (GRs) in an array, ensuring they are correctly positioned to extend the heatsink's path. Figure 16 The layout is designed to enhance thermal management within the circuit, optimize heat dissipation, and maintain efficient operation.

[0076] Figure 18 An example system suitable for designing integrated circuits according to some embodiments is illustrated. The design process can be implemented via a computer system (e.g., an ECAD system). Some or all of the operations disclosed herein for design (e.g., placement) methods can be performed as part of a design process executed in a design room.

[0077] In some embodiments, system 1800 includes an automated place and route (APR) system. In some embodiments, system 1800 includes a processing device 1802 and a non-transitory computer-readable storage medium 1804 (“storage device”). Processing device 1802 is any suitable processing device or apparatus. Exemplary processing devices include, but are not limited to, central processing units, microprocessors, distributed processing systems, application-specific integrated circuits (ASICs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), or combinations thereof.

[0078] Storage device 1804 may be encoded or stored, for example, computer program code (e.g., a set of executable instructions 1806). Execution (at least partially) of the executable instructions 1806 by processing device 1802 represents an ECAD tool that implements some or all of the methods described herein to produce the designs of the structures and ICs disclosed herein. Additionally, manufacturing tools 1808 may be included for IC placement and physical implementation. In one or more embodiments, storage device 1804 is a non-transient electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage device 1804 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random-access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, storage device 1804 includes compact disk-read-only memory (CD-ROM), compact disk-read / write optical disk (CD-R / W), and / or digital video disc (DVD).

[0079] Processing device 1802 is operatively connected to storage device 1804 via and bus 1810. Processing device 1802 is also operatively connected via bus 1810 to input / output (I / O) interface 1812 and network interface 1814. Network interface 1814 is operatively connected to network 1816, enabling processing device 1802 and storage device 1804 to connect to external component vias and network 1816. In one or more embodiments, network 1816 is an illustration of any type of wired and / or wireless network, such as an internal network and / or a distributed computing network (e.g., the Internet).

[0080] Network interface 1814 allows system 1800 to communicate with other computing or electronic devices (not shown) via and network 1816. Network interface 1814 includes a wireless network interface and / or a wired network interface. Example wireless network interfaces include Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA. Example wired network interfaces include Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods disclosed herein are implemented in the distributed system via and network 1816.

[0081] Processing device 1802 is configured to execute executable instructions 1806 encoded in storage device 1804 to make system 1800 available for executing some or all of the programs and / or methods described herein. For example, an electronic design application (e.g., in an ECAD system or as a standalone application) can be configured to execute... Figures 1-17 The methods and techniques shown are beyond the capabilities of human thought, given the complexity of integrated circuits and the fact that they comprise thousands, millions, or billions of components. Figures 1-17 The methods and techniques described herein. Unlike human thought, electronic design applications are capable of performing actions similar to... Figures 1-17 Related operations.

[0082] In one or more embodiments, storage device 1804 stores executable instructions 1806 configured such that system 1800 can be used to execute some or all of the processes and / or methods. In one or more embodiments, storage device 1804 also stores some or all of the information that facilitates the execution of the processes and / or methods. In one or more embodiments, storage device 1804 stores a cell library 1818 comprising (at least partially) standard and / or previously designed cells.

[0083] I / O interface 1812 is operatively connected to I / O device 1820. In one or more embodiments, I / O device 1820 includes one or more of an image capture device, microphone, scanner, keyboard, keypad, mouse, touchpad, touchscreen, and / or cursor arrow keys for transmitting messages and commands to processing device 1802. I / O device 1820 may also include one or more displays, one or more speakers, printer, headphones, haptic or haptic feedback devices, etc.

[0084] System 1800 is configured to receive messages via I / O interface 1812. The information received via I / O interface 1812 includes one or more of the following: instructions, data, design rules, cell libraries, and / or other parameters processed by processing device 1802. Messages are transmitted to processing device 1802, vias, and bus 1810. System 1800 is also configured to receive information related to the user interface (UI) via I / O interface 1812. This information is stored in storage device 1804 as UI 1822 or used for presentation in UI 1822.

[0085] In some embodiments, part or all of the process and / or method is implemented as a standalone software application (e.g., EDA) executed by a processing device (e.g., processing device 1802). In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by system 1800. In some embodiments, a layout diagram including standard and / or previously designed cells is generated using tools such as VIRTUOSO, available from Cadence Design Systems, Inc. (San Jose, California), or another suitable layout generation tool.

[0086] In some embodiments, these programs are implemented as the functions of a program stored in a non-transitory computer-readable storage medium (e.g., storage device 1804). Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory cells, such as optical discs (e.g., DVDs), magnetic disks, such as hard disks, semiconductor memory, such as ROM, RAM, memory cards, and one or more of the like.

[0087] As described above, embodiments of system 1800 may include manufacturing tool 1808 for implementing processes and / or methods stored in storage device 1804. For example, synthesis may be performed on a design, wherein the desired behavior and / or functionality of the design is transformed into a functionally equivalent logic gate circuit description by matching the design with cells selected from a cell library 1818. Synthesis produces a functionally equivalent logic gate circuit description, such as a gate netlist. Based on the gate netlist, a photomask for fabricating analog integrated circuits using manufacturing tool 1808 can be generated.

[0088] Figure 19A flowchart illustrating an exemplary method for manufacturing analog integrated circuits is provided. Initially, as shown in block 1900, a layout diagram of the analog integrated circuit is received. In some embodiments, the layout diagram is obtained using... Figures 1-17 It is generated by one or more operations as shown. For example, the layout diagram can be... Figure 2 The final layout is generated at block 250. Based on the received layout, an analog integrated circuit is fabricated at block 1902.

[0089] Figure 20 An exemplary flowchart of a method 2000 for manufacturing an integrated circuit according to some embodiments is shown. It should be understood that, in order to better understand the concepts disclosed herein, Figure 20 It has been simplified. Therefore, it should be noted that it is possible to... Figure 1 Additional processing is provided before, during, and after the method, and only a few of these additional processes can be briefly described here.

[0090] Now for reference Figure 20 Operation 2010 can form multiple active components of an integrated circuit on the front side of a substrate. The substrate can have a front side and a back side opposite each other. The substrate can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped.

[0091] Next, method 2000 proceeds to operation 2020, where a plurality of dummy components are formed on the front side of the substrate, each dummy component being laterally disposed next to one or more active components. The plurality of dummy components are disposed adjacent to one or more active components along a first lateral direction or a second lateral direction. The plurality of dummy components form part of a guard ring for the plurality of active components.

[0092] Next, method 2000 proceeds to operation 2030, forming a plurality of first via structures extending vertically through the substrate from the back side to the front side. Each first via structure is laterally disposed within a corresponding active component or dummy assembly. The plurality of first via structures are disposed relative to each other along an inclined direction between a first lateral direction and a second lateral direction. Some of the plurality of first via structures are aligned with each other along the second lateral direction.

[0093] Next, method 2000 proceeds to operation 2040, forming a plurality of second via structures extending vertically through the substrate from the back side to the front side. The second via structures extend laterally within one of the corresponding dummy components, along the edge between one of the active components and one of the dummy components, or along the edge between adjacent active components. In some embodiments, the second via structures extend along the edge between a first cell and a second cell in a first lateral direction. In some embodiments, the second via structures extend along the first lateral direction between a pair of second active regions and a second cell.

[0094] Next, proceeding from method 2000 to operation 2050, a second interconnect structure is formed on the back side of the substrate. The second interconnect structure, coupled to an active component through at least one of the first or second via structures, is configured to carry a power supply voltage for the integrated circuit.

[0095] This invention provides a method for fabricating an integrated circuit, comprising: forming a plurality of active components of the integrated circuit on the front side of a substrate; forming a plurality of dummy components on the front side of the substrate, each dummy component being laterally disposed adjacent to one or more of the active components; forming a plurality of first via structures extending vertically from the back side of the substrate through the substrate to the front side, wherein each of the first via structures is laterally disposed within a corresponding active component or dummy component; forming a second via structure extending vertically from the back side of the substrate through the substrate to the front side of the substrate, wherein the second via structure extends laterally within one of the corresponding dummy components, extends laterally along an edge between one of the active components and one of the dummy components, or extends laterally along an edge between adjacent active components; and forming a second interconnect structure on the back side of the substrate, wherein the second interconnect structure is coupled to the active components through at least one of the first via structures or the second via structure, and is configured to carry a power supply voltage of the integrated circuit.

[0096] In a further embodiment of this novel method, the method further includes: forming a plurality of first interconnect structures on the active component and the dummy component.

[0097] In this novel embodiment, the plurality of dummy components are disposed along a first lateral direction or a second lateral direction adjacent to one or more of the active components.

[0098] In this novel embodiment, the plurality of first through-hole structures are arranged relative to each other along an inclined direction between the first lateral direction and the second lateral direction.

[0099] In this novel embodiment, some of the plurality of first through-hole structures are aligned with each other along the second lateral direction.

[0100] In this novel embodiment, the plurality of dummy components form part of a protection ring for the plurality of active components.

[0101] In this novel embodiment, each of the plurality of active components corresponds to a corresponding one of the plurality of adjacent cells.

[0102] In this novel embodiment, the plurality of cells further includes: one of the first plurality of cells corresponding to the plurality of active components; and one of the second plurality of cells disposed adjacent to the first cell along a first lateral direction or a second lateral direction.

[0103] In this novel embodiment, the first cell includes a pair of first active regions extending along the first lateral direction, and the second cell includes a pair of second active regions extending along the first lateral direction.

[0104] In this novel embodiment, each of the first through-hole structures extends along the second lateral direction from a first edge of a corresponding one of the first active region and the second active region to a second edge.

[0105] In this novel embodiment, the second through-hole structure extends along the edge between the first cell and the second cell in the first lateral direction.

[0106] In this novel embodiment, the second through-hole structure extends along the first lateral direction between the second active region and the second cell.

[0107] An embodiment of the present invention provides an integrated circuit, comprising: a plurality of active components operably coupled to each other to form an integrated circuit, wherein the plurality of active components are disposed above a front side of a substrate; a plurality of dummy components, each of the plurality of dummy components being laterally configured adjacent to one or more of the active components, wherein the plurality of dummy components are formed above the front side; an interconnect structure disposed on a back side of the substrate, opposite to the front side of the substrate, and carrying a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a corresponding one of the active components or dummy components; and a second via structure extending vertically through the substrate and laterally extending within a corresponding one of the dummy components, extending laterally along an edge between one of the active components and one of the dummy components, or extending laterally along an edge between adjacent active components.

[0108] In this novel embodiment, the plurality of dummy components are disposed adjacent to the one or more active components along a first lateral direction or a second lateral direction.

[0109] In this novel embodiment, the plurality of first through-hole structures are arranged relative to each other along an inclined direction between the first lateral direction and the second lateral direction.

[0110] In this novel embodiment, some of the plurality of first through-hole structures are aligned with each other along the second lateral direction.

[0111] In this novel embodiment, the plurality of dummy components form part of a protection ring for the plurality of active components.

[0112] An embodiment of the present invention provides an integrated circuit, comprising: a plurality of active components operably coupled to each other to form an integrated circuit, wherein the plurality of active components are disposed above a front side of a substrate, and an interconnect structure is disposed on a back side of the substrate, opposite to the front side of the substrate, and carries a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a corresponding one of the active components; and a second via structure extending vertically through the substrate and laterally extending along an edge between one of the active components, or laterally extending along an edge between adjacent components of the active components.

[0113] In this novel embodiment, the integrated circuit further includes: a plurality of dummy components, each of the plurality of dummy components being laterally configured adjacent to one or more of the active components, wherein the plurality of dummy components are formed on the front side.

[0114] In this novel embodiment, the plurality of dummy components are disposed adjacent to one or more of the active components along a first lateral direction or a second lateral direction.

[0115] As used herein, the terms “about” and “approximately” generally indicate a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may represent a given quantity of value that varies within, for example, 10-30% of that value (e.g., 10%, ±20%, or ±30% of that value)

[0116] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, characterized by comprise: a plurality of active components operatively coupled to one another to form an integrated circuit, wherein the plurality of active components are disposed over a front side of a substrate; a plurality of dummy components, each of the plurality of dummy components disposed laterally adjacent to one or more of the active components, wherein the plurality of dummy components are formed over the front side; an interconnect structure disposed on a back side of the substrate, opposite the front side of the substrate, and carrying a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a respective one of the active components or dummy components; and a second via structure extending vertically through the substrate and laterally within one of the dummy components, along an edge between one of the active components and one of the dummy components, or along an edge between adjacent ones of the active components. The plurality of dummy components are disposed adjacent to the one or more of the active components along a first lateral direction or a second lateral direction.

2. The integrated circuit of claim 1, wherein, The plurality of first via structures are disposed relative to one another along an oblique direction between the first lateral direction and the second lateral direction.

3. The integrated circuit of claim 2, wherein, Some of the plurality of first via structures are aligned with one another along the second lateral direction.

4. The integrated circuit of claim 2, wherein, The plurality of dummy components form a portion of a guard ring for the plurality of active components.

5. The integrated circuit of claim 2, wherein, Each of the plurality of active components corresponds to a respective one of a plurality of cells that are contiguous with one another.

6. The integrated circuit of claim 1, wherein, The plurality of cells further comprise:

7. The integrated circuit of claim 6, wherein, a first cell of the plurality of cells corresponding to the plurality of active components; and a second cell of the plurality of cells disposed laterally adjacent to the first cell along a first lateral direction or a second lateral direction. comprise:

8. An integrated circuit, characterized by a plurality of active components operatively coupled to one another to form an integrated circuit, wherein the plurality of active components are disposed over a front side of a substrate, an interconnect structure disposed on a back side of the substrate, opposite the front side of the substrate, and carrying a power supply voltage; a plurality of first via structures, each of the plurality of first via structures extending vertically through the substrate and laterally disposed within a respective one of the active components; and a second via structure extending vertically through the substrate and laterally along an edge between one of the active components or along an edge between adjacent ones of the active components. further comprise:

9. The integrated circuit of claim 8, wherein, a plurality of dummy components, each of the plurality of dummy components disposed laterally adjacent to one or more of the active components, wherein the plurality of dummy components are formed over the front side. The plurality of dummy components are disposed adjacent to the one or more of the active components along a first lateral direction or a second lateral direction.

10. The integrated circuit of claim 9, wherein, ​

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