Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure. The semiconductor structure comprises a first interconnection structure arranged above a first semiconductor substrate, a plurality of thermal sensors embedded in the first interconnect structure and sensing a temperature change in the semiconductor structure; and a first bonding structure disposed on the first interconnect structure and electrically coupled to the first interconnect structure. The thermal sensor is electrically isolated from the conductive feature of the first interconnect structure and the conductive feature of the first bonding structure. The thermal sensor is arranged in a first interconnect structure of the semiconductor structure to increase the accuracy of the thermal sensing device and establish a three-dimensional temperature profile of the semiconductor structure, thereby achieving accurate temperature sensing.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor structure, and more particularly to a semiconductor structure having a thermal sensor. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration of various devices. To a large extent, these improvements in integration stem from the continuous reduction in the smallest feature size, allowing more devices to be integrated into a given area. Technological advancements in integrated circuit (IC) design have resulted in several generations of ICs, each generation being smaller and more complex than the last. High device density can generate heat, leading to performance degradation. Thermal sensors may be needed to monitor and control this heat generation. While existing semiconductor structures with thermal sensors are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Utility Model Content

[0003] An embodiment of this utility model provides a semiconductor structure including a first interconnect structure disposed above a first semiconductor substrate, a plurality of thermal sensors embedded in the first interconnect structure and sensing temperature changes in the semiconductor structure, and a first bonding structure disposed on and electrically coupled to the first interconnect structure. The thermal sensors are electrically isolated from the conductive characteristics of the first interconnect structure and the conductive characteristics of the first bonding structure.

[0004] Embodiments of this invention provide a semiconductor structure including a hot spot region above a semiconductor substrate, an interconnect structure above the semiconductor substrate, and multiple thermal sensors embedded at different horizontal heights in the interconnect structure. The thermal sensors include multiple first sensors for monitoring temperature changes in the hot spot region and multiple second sensors for monitoring temperature changes in areas outside the hot spot region, with the first sensors arranged in a more densely packed manner than the second sensors.

[0005] Based on the above, thermal sensing devices within a semiconductor structure can be integrated into semiconductor circuits fabricated through back-end processes. The thermal sensing device can be formed from materials compatible with the back-end processes and can have a temperature-dependent resistance. Feedback circuitry connected to the thermal sensing device can be configured to dynamically control the power input to the corresponding layer of the semiconductor structure. The placement of the thermal sensing device can be flexible. More than one thermal sensing device can be placed at various locations throughout the semiconductor structure to obtain high-precision temperature readings in sensitive areas. Multiple thermal sensing components can be arranged within the semiconductor structure to increase the accuracy of the thermal sensing device and establish a 3D temperature distribution map, thereby achieving precise temperature sensing.

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 , Figure 2A , Figure 3-6 A schematic cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure with a thermal sensor according to some embodiments is shown.

[0008] Figure 2B Illustrations are shown according to some embodiments Figure 2A A schematic top view of the structure to show the location of the thermal sensor and the area to be monitored.

[0009] Figure 2C and Figure 2D Partial views of different types of thermal sensors according to some embodiments are shown.

[0010] Explanation of reference numerals in the attached figures

[0011] 10: Semiconductor structure; 11H: First region; 11L: Second region; 111, 111': Semiconductor substrate; 111a: Front side; 111b, 111b': Back side; 112: First device; 112P: Conductive plug; 114: Through-hole / TSV; 114a: First end; 114b: Second end; 115: Interconnect structure; 116: Thermal sensing device; 116-1: First group; 116-2: Second group; 117: First bonding structure; 117t, 118t: Bonding surfaces; 118: Second bonding structure; 121: Carrier; 122: Heat dissipation assembly; 1131: Interlayer dielectric layer / ILD layer; 1151: Dielectric layer; 1151a: First dielectric layer; 1151b: Second dielectric layer; 1151c: Third dielectric layer; 1151d: Fourth dielectric layer; 1152: Conductive layer; 115 2a: First conductive sublayer; 1152b: Second conductive sublayer; 1152c: Third conductive sublayer; 1152d: Fourth conductive sublayer; 1161: Thermal sensing component; 1161A: Metallization pattern; 1161B: 2-terminal device; 1161B1: 2D material layer; 1161B2: Terminal; 1161v: Via; 1162: Second device; 1162C: Channel layer; 1162GD: Gate Dielectric layer; 1162SD: S / D contact; 1162f: Conductive feature; 1171: First bonding dielectric layer; 1171t, 1172t, 1181t, 1182t: Exposed surfaces; 1172: First bonding feature; 1181: Second bonding dielectric layer; 1182: Second bonding feature; D1, D2, D3: Orientation; IF1: Bonding interface; T1: First layer; T2: Second layer. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0013] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0014] The high device density resulting from advanced transistors can generate heat, and the accumulation of heat in the semiconductor structure can lead to performance degradation. The embodiments discussed herein provide a semiconductor structure including a thermal sensor, wherein the thermal sensor can be configured to monitor and / or measure temperature changes within the semiconductor structure. The thermal sensor can be fabricated via back-end-of-line (BEOL) processes and can be formed from materials compatible with BEOL processes. It should be noted that, in this document, the technical terms "thermal sensor" and "temperature sensor" are used interchangeably.

[0015] According to some embodiments, Figure 1 , Figure 2A , Figure 3-6 The diagram shows a schematic cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure with a thermal sensor. Figure 2B It shows Figure 2A A schematic top view of the structure is provided to show the location of the thermal sensor and the area to be monitored. Figure 2C and Figure 2D A partial view of a similar thermal sensor is shown. For clarity, the orthogonal axes of the coordinate system upon which the view is oriented are shown in the accompanying drawings. For example, Figure 1 , Figure 2A , Figure 2D , Figure 3-6 It is a cross-sectional view along the D1-D3 plane (e.g., the XZ plane or the YZ plane), where direction D1 is substantially perpendicular to direction D3. Figure 2B and Figure 2C This can be a top view along the D1-D2 plane (e.g., the XY plane), where direction D1 is substantially perpendicular to direction D2. Furthermore, the manufacturing methods described below are merely illustrative and not limited thereto. Additional steps may be provided before, during, and after the manufacturing methods and some steps, and some steps may be replaced, eliminated, or moved for additional embodiments of the methods. For brevity, not all steps are described in detail herein. Additionally, unless otherwise stated, similar reference numerals throughout the description and in different embodiments denote similar features having similar structures and compositions.

[0016] Reference Figure 1 A semiconductor substrate 111 is provided. For example, the semiconductor substrate 111 may be in the form of a wafer, a chip, a panel, etc. The semiconductor substrate 111 may include a front side 111a (or an active surface) and a back side 111b opposite to the front side 111a. The semiconductor substrate 111 may include one or more semiconductor materials (e.g., silicon, germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0017] In some embodiments, one or more first devices 112 may be formed on the front side 111a of the semiconductor substrate 111. The first devices 112 may be active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, inductors, etc.), combinations thereof, and / or the like. The first devices 112 may be or include high-power devices and / or low-power devices. In some embodiments, the first devices 112 are formed using a suitable front-end-of-line (FEOL) process and may be referred to as FEOL devices. It should be understood that although two first devices 112 are shown and represented by transistors, the first devices 112 may have a different number and type than those shown. In some embodiments, an inter-layer dielectric (ILD) layer 1131 is formed over the front side 111a of the semiconductor substrate 111 to surround and cover the first devices 112. The ILD layer 1131 may include one or more dielectric materials, such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or combinations thereof. In some embodiments, a conductive plug 112P extends through the ILD layer 1131 to be electrically and physically coupled to the first device 112. The conductive plug 112P may be formed of W, Co, Ni, Cu, Ag, Au, Al, alloys, the like, or combinations thereof. For example, when the first device 112 is a transistor, the conductive plug 112P may be coupled to the gate and source / drain (S / D) regions of the transistor. Although shown as formed in the same cross-section, it should be understood that each conductive plug 112P coupled to the gate and S / D region may be formed in a different cross-section to avoid short circuits in the contacts. It should be noted that, depending on the context, one or more S / D regions may individually or collectively refer to the source or drain.

[0018] Continue to refer to Figure 1One or more vias 114 may be formed in the semiconductor substrate 111 and may pass through the ILD layer 1131. For example, the vias 114 are formed by depositing one or more diffusion barrier layers or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., W, Ti, Al, Cu, any combination thereof, and / or the like) into trenches in the ILD layer 1131 and the underlying semiconductor substrate 111. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), grinding, etching, or a combination thereof) is performed on the vias 114 and the ILD layer 1131 such that the vias 114 and the ILD layer 1131 are substantially flush (or coplanar) within a range of process variations. For example, the via 114 includes a first end 114a substantially flush with the ILD layer 1131 and a second end 114b opposite to the first end 114a, wherein, in this stage, the second end 114b may be buried in the semiconductor substrate 111.

[0019] Reference Figure 2A And refer to Figure 1 Interconnect structures 115 may be formed on the front side 111a of the semiconductor substrate 111. For example, interconnect structures 115 are formed on the ILD layer 1131, vias 114, and conductive plugs 112P. In some embodiments, interconnect structures 115 are formed by back-end-of-line (BEOL) processes. For example, interconnect structures 115 include a dielectric layer 1151 and one or more conductive layers 1152 embedded in the dielectric layer 1151. The dielectric layer 1151 may include one or more dielectric materials, such as low dielectric constant dielectric materials (e.g., PSG, BPSG, fluorosilicate glass (FSG), spin-coated glass, spin-coated polymers, silicon carbide materials, combinations thereof, etc.) or any suitable dielectric material. In some embodiments, dielectric layer 1151 is referred to as an inter-metal dielectric (IMD) layer. For example, dielectric layer 1151 includes a first dielectric layer 1151a overlying ILD layer 1131, a second dielectric layer 1151b overlying the first dielectric layer 1151a, a third dielectric layer 1151c overlying the second dielectric layer 1151b, and a fourth dielectric layer 1151d overlying the third dielectric layer 1151c. The first, second, third, and fourth dielectric layers (1151a, 1151b, 1151c, and 1151d) may comprise the same material or different materials. It should be understood that although four dielectric layers are shown, dielectric layer 1151 may comprise more than four dielectric layers or fewer than four dielectric layers, depending on the requirements of the circuit and product.

[0020] In some embodiments, conductive layers 1152 may each include conductive features (e.g., wires, vias, pads, etc.). The vias of conductive layer 1152 may pass through the plane of adjacent sublayers and provide electrical connections between adjacent sublayers. Conductive layer 1152 may include one or more conductive materials, such as Ti, Cu, Ni, Ag, Au, Al, alloys, the like, or combinations thereof. For example, conductive layer 1152 is electrically interconnected with first device 112 via conductive plug 112P to form an integrated circuit. Conductive layer 1152 may be electrically connected to via 114. Figure 2A In this circuit, the via 114 is physically connected to the bottommost layer of the conductive layer 1152; however, depending on the requirements of the circuit and the product, the via 114 may be extended to connect to any layer of the conductive layer 1152.

[0021] In some embodiments, the conductive layer 1152 includes a first conductive sublayer 1152a formed in the first dielectric layer 1151a and connected to the first conductive plug 112P and the through hole 114, a second conductive sublayer 1152b formed in the second dielectric layer 1151b and connected to the first conductive sublayer 1152a, a third conductive sublayer 1152c formed in the third dielectric layer 1151c and connected to the second conductive sublayer 1152b, and a fourth conductive sublayer 1152d formed in the fourth dielectric layer 1151d and connected to the third conductive sublayer 1152c. In some embodiments, the size and linewidth / spacing of the fourth conductive sublayer 1152d are greater than those of the third conductive sublayer 1152c, the size and linewidth / spacing of the third conductive sublayer 1152c are greater than those of the second conductive sublayer 1152b, and the size and linewidth / spacing of the second conductive sublayer 1152b are greater than those of the first conductive sublayer 1152a. It should be understood that although four conductive sublayers are shown, conductive layer 1152 may include more or fewer than four conductive sublayers, depending on the requirements of the circuit and product.

[0022] Continue to refer to Figure 2A One or more thermal sensing devices (also referred to as heat / temperature sensors) 116 may be embedded in the interconnect structure 115. The thermal sensing device 116 may be electrically isolated from the conductive layer 1152 and may be used to monitor the resulting semiconductor structure (see...). Figure 6 The thermal sensing device 116 monitors or senses the temperature of one or more devices / areas / paths within the semiconductor structure (see [link to documentation]). In some embodiments, one or more materials and fabrication methods of the thermal sensing device 116 are compatible with the BEOL process. For example, the thermal sensing device 116 is fabricated using the BEOL process. The thermal sensing device 116 integrated into the interconnect structure 115 can be configured to monitor or sense the temperature of the resulting semiconductor structure (see [link to documentation]). Figure 6Temperature changes or variations in the device / area / path. In some embodiments, when the temperature exceeds a predetermined threshold, the thermal sensing device 116 can warn the circuit to slow down (or shut down) the corresponding device to reduce power consumption, thereby lowering the temperature and preventing overheating that could lead to device failure. Dynamic power control of the circuit can prevent device degradation or failure due to high temperatures. For example, a feedback circuit (not shown separately) is connected to the thermal sensing device 116 and configured to dynamically control the power input of the resulting semiconductor structure. In response to the sensed / measured temperature, circuit operation can be adjusted. For example, adjustments to circuit operation include adjusting one or more operating parameters (e.g., reducing voltage, current, or power levels) or performing one or more actions (e.g., entering a reduced power mode or triggering an alarm) to reduce or avoid overheating conditions, thereby enhancing the performance and reliability of the resulting semiconductor structure.

[0023] Continue to refer to Figure 2A The corresponding thermal sensing device 116 may include one or more thermal sensing components 1161 embedded in the interconnect structure 115. The corresponding thermal sensing components 1161 may be surrounded and covered by a dielectric layer 1151. One or more thermal sensing components 1161 may be disposed adjacent to one or more conductive layers 1152. In some embodiments, the interconnect structure 115 includes patterned dense regions and patterned sparse regions, wherein the patterned sparse regions may have a lower density of conductive layers 1152 (or wider spacing between conductive features) than the patterned dense regions. The thermal sensing components 1161 may be disposed on the patterned sparse regions of the interconnect structure 115. In some embodiments where multiple thermal sensing components 1161 are disposed on different sublayers of the dielectric layer 1151, one or more vias 1161v may pass through the plane of adjacent sublayers and provide electrical connection between the thermal sensing components 1161 disposed on adjacent sublayers. It should be understood that although the thermal sensing components 1161 are disposed on each sublayer of the dielectric layer 1151, the thermal sensing components 1161 may have a different number and arrangement than those shown. The thermal sensing components 1161 may be or include sensing circuitry or any type of sensing device / assembly. (Refer to...) Figure 2C-2D The thermal sensing component 1161 is described in more detail.

[0024] Still refer to Figure 2AThe corresponding thermal sensing device 116 may include one or more second devices 1162 embedded in the interconnect structure 115. For example, the thermal sensing component 1161 is electrically coupled to the second device 1162 and electrically isolated from the first device 112. In some embodiments, the second device 1162 is a control device (e.g., a transistor) included in a control circuit, wherein the control circuit electrically coupled to the thermal sensing component 1161 may be configured to receive voltage and generate control signals. In some embodiments, the corresponding second device (e.g., a transistor) 1162 is used in a thermal sensor by using the temperature-dependent threshold voltage of the transistor. For example, the corresponding second device 1162 is surrounded and covered by a dielectric layer 1151. One or more second devices 1162 may be disposed adjacent to one or more conductive layers 1152 and one or more thermal sensing components 1161. For example, the topmost one of the second device 1162 and the thermal sensing component 1161 is arranged side by side and electrically connected by a conductive feature 1162f (e.g., a wire, a conductive pad, a via, or a combination thereof). In some embodiments, one or more materials and forming methods of the second device 1162 and the thermal sensing component 1161 are compatible with the BEOL process. For example, the second device 1162 and the thermal sensing component 1161 are manufactured using the BEOL process. The second device 1162 and the thermal sensing component 1161 can be considered as a BEOL device / component.

[0025] In some embodiments, the corresponding second device 1162 (represented by a transistor) includes a gate electrode 1162G, an S / D contact 1162SD, a channel layer 1162C disposed below the gate electrode 1162G and laterally between the S / D contact 1162SD, and a gate dielectric layer 1162GD vertically interposed between the gate electrode 1162G and the channel layer 1162C. For example, the material of the channel layer 1162C includes metal oxides (e.g., IGZO, In2O3, InWO, SnO, TaSnO, TiSnO, etc.), amorphous silicon, polycrystalline silicon, two-dimensional (2D) materials (e.g., MoS2, WS2, MoSe2, WSe2, MoTe2, etc.), or any suitable channel material compatible with BEOL processes. In some embodiments of the second device 1162, which is a transistor based on 2D materials, the channel layer 1162C is formed of one or more 2D materials and can be formed by metal-organic chemical vapor deposition (MOCVD) at low temperatures (e.g., less than 400°C or similar). In some embodiments, the channel layer 1162C is formed of one or more metal oxide materials and / or polysilicon and can be deposited by sputtering or any suitable deposition process. The gate electrode 1162G and the S / D contact 1162SD may include one or more conductive materials, such as Co, W, Cu, Ti, Ta, Al, Zr, Hf, combinations thereof, or other suitable metallic materials. In some embodiments, the gate electrode 1162G and the S / D contact 1162SD are formed by sputtering or any suitable deposition process. The gate dielectric layer 1162GD may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant dielectric, or combinations thereof, and can be formed by sputtering or any suitable deposition process. It should be noted that although two second devices 1162 are shown and represented by transistors, the second devices 1162 may have a different number and type than those shown.

[0026] In an alternative embodiment, the second device 1162 is omitted, and a portion of the first device 112 (e.g., a transistor) formed by the FEOL process is included in the thermal sensing device 116 to serve as a control transistor. For example, said portion of the first device 112 is disposed below the bottommost one of the thermal sensing components 1161 and electrically connected to the bottommost one of the thermal sensing components 1161 via conductive features (not shown; e.g., wires, conductive pads, vias, combinations thereof, etc.). While the second device 1162 is represented by a transistor, in some other embodiments, the second device 1162 is a diode or any other control device whose operation depends on temperature.

[0027] Reference Figure 2B And refer to Figure 2A Thermal sensing devices 116 can be sufficiently close and thermally coupled to the device / region / path to be monitored / sensed. In some embodiments, in a given region, a first group 116-1 of thermal sensing devices 116 is arranged in a denser configuration than a second group 116-2 of thermal sensing devices 116. For example, the first group 116-1 of thermal sensing devices 116 is located near a first region 11H, with a smaller spacing between adjacent thermal sensing devices 116 in the first group 116-1. In some embodiments, one or more high-power devices can be formed in the first region 11H, and the first region 11H can be a higher temperature region in the resulting semiconductor structure. In some embodiments, the first region 11H is a region with a sharp local temperature peak (referred to as a hot spot) or any region / path with a high thermal bottleneck requiring thermal control. The first region 11H can be a hot spot region. A region / path with a thermal bottleneck can be a region / path where heat flow is more restricted than in other regions / paths in the resulting semiconductor structure. The first group 116-1 of thermal sensing devices 116 may be arranged more densely around the first region 11H to provide temperature feedback to the controller for thermal control. In some embodiments, the first group 116-1 of thermal sensing devices 116 arranged more densely may be positioned near the subsequently formed first bonding structure 117 (see [link]). Figure 3 ).

[0028] In some embodiments, adjacent thermal sensing devices 116 in the second group 116-2 of thermal sensing devices 116 have a larger spacing and can be distributed in a sparser arrangement than the first group 116-1 of thermal sensing devices 116. The second group 116-2 of thermal sensing devices 116 may be disposed near the second region 11L. In some embodiments, one or more lower power devices may be formed in the second region 11L, and the second region 11L may be a lower temperature region in the resulting semiconductor structure. Compared with low-power devices, high-power devices can consume a relatively large amount of power and therefore generate a relatively large amount of heat. It should be understood that... Figure 2B The number of the first group 116-1 and the second group 116-2 of thermal sensing devices shown is for illustrative purposes, and the first group 116-1 and the second group 116-2 of thermal sensing devices may have different arrangements and numbers than those shown. By arranging the thermal sensing devices 116 near specific and temperature-sensitive areas, temperature data can be better correlated with the actual temperature of the monitored device / area / path location.

[0029] Reference Figure 2C-2D And refer to Figure 2AVarious embodiments are used for the thermal sensing component 1161. In some embodiments, the corresponding thermal sensing component 1161 is implemented by a resistor (e.g., a metal resistor, a TiN resistor, an implanted resistor, the like, combinations thereof, etc.) or any suitable resistive component. One or more resistors may have a resistance value related to heat. Figure 2C As schematically shown in the top view, the resistor includes a metallized pattern 1161A that meanders along the D1-D2 plane. (See reference...) Figure 2C and Figure 2A The metallization pattern 1161A can be physically and electrically connected to the conductive feature 1162f and / or the via 1161v. The metallization pattern 1161A can be disposed adjacent to the conductive layer 1152 and formed using any suitable patterning and / or deposition process. In some embodiments, the metallization pattern 1161A is formed on or above the fourth layer (referred to as M4) of the interconnect structure 115. The metallization pattern 1161A can be formed of one or more conductive materials, such as TaN, TiN, W, Ru, combinations thereof, and the like. The thickness of the metallization pattern 1161A, measured in direction D3, can range from about 0.1 μm to about 1 μm. The total length of the metallization pattern 1161A can range from about 10 μm to about 100 μm. The width of the metallization pattern 1161A can range from about 1 μm to about 10 μm. The total resistance of the metallization pattern 1161A can range from about 1 Ω to 100 Ω. Depending on the requirements of the product and circuit, the metallization pattern 1161A may have other suitable values.

[0030] The temperature coefficient of resistance (TCR) of a resistor is determined by measuring its resistance over a temperature range. The metallization pattern 1161A can provide a known TCR. In some embodiments, the metallization pattern 1161A (e.g., a metal resistor) has a TCR of approximately 0.2 to 0.5% / K. In some embodiments, the thermal sensing component 1161 is formed of a material with a relatively high TCR, such that a small temperature change results in a large resistance change. However, the material of the resistor does not necessarily need to be a material with a high TCR. A material can be used to form the thermal sensing component 1161 if its TCR is known / repeatable / predictable and / or measurable with precision. In some embodiments, both resistance and TCR are functions of the resistor's size and arrangement. Based on the monitored resistance and the known TCR of the resistor, a temperature can be obtained from the known TCR, and the changed temperature can be sensed / measured in the resulting semiconductor structure. Therefore, the thermal sensing device 116 can be used for temperature measurements representing one or more power devices / hot spots.

[0031] Continue to refer to Figure 2D and Figure 2A The thermal sensing component 1161 may be implemented by one or more two-terminal devices 1161B. The one or more two-terminal devices 1161B may be disposed adjacent to the conductive layer 1152 and formed using any suitable deposition process. In some embodiments, the one or more two-terminal devices 1161B are formed in or above a fourth layer (referred to as M4) in the interconnect structure 115. The corresponding two-terminal device 1161B may include a 2D material layer 1161B1 and one or more terminals 1161B2 connected to the 2D material layer 1161B1. In the illustrated embodiment, two terminals 1161B2 are disposed on opposite sides of the 2D material layer 1161B1. The terminals 1161B2 may have a different number and arrangement than shown. The terminals 1161B2 may be physically and electrically connected to the conductive feature 1162f and / or the via 1161v. Terminal 1161B2 may include one or more conductive materials, such as Co, W, Cu, Ti, Ta, Al, combinations thereof, or other suitable metallic materials.

[0032] The 2D material layer 1161B1 may include MoS2, WS2, MoSe2, WSe2, MoTe2, similar materials, combinations thereof, etc. In some embodiments, the thickness of the 2D material layer 1161B1, measured in direction D3, may range from about 1 μm to about 100 μm. In some embodiments, the thickness of the 2D material layer 1161B1 is less than the thickness of the corresponding terminal 1161B2 and / or less than the thickness of the conductive layer 1152 at the same horizontal height. The length of the 2D material layer 1161B1 may range from about 1 μm to about 10 μm. The width of the 2D material layer 1161B1 may range from about 1 μm to about 10 μm. The total resistance of the 2D material layer 1161B1 may range from about 10 kΩ to 10 MΩ. In some embodiments, the TCR of the 2D material layer 1161B1 is about 0.2% to 2% / K. The 2D material layer 1161B1 may have other suitable values, depending on the requirements of the product and circuit. Based on the monitored resistance and the known temperature coefficient of resistance (TCR) of the 2D material layer 1161B1, the temperature can be obtained from the known TCR, and the temperature change in the resulting semiconductor structure can be determined or sensed. The thermal sensing device 116 can be used for temperature measurement (e.g., temperature-dependent resistance measurement).

[0033] The aforementioned structure for implementing the thermal sensing component 1161 is provided for illustrative purposes. Various types of thermal sensing components 1161 are within the scope of this disclosure. The thermal sensing component 1161 may have characteristics that vary according to its temperature, and the thermal sensing component 1161 may be sufficiently close to the device / area / path to be monitored / sensed. The thermal sensing component 1161 may be arranged at different horizontal heights of the interconnect structure 115 to monitor the resulting semiconductor structure (see...). Figure 6 Temperature at different depths within the semiconductor structure. For example, thermal sensing component 1161 is used to establish the resulting semiconductor structure (see...). Figure 6 The temperature distribution is arranged in the manner of a temperature distribution map.

[0034] Reference Figure 3 And refer to Figure 2A A first bonding structure 117 may be formed on the interconnect structure 115. Since the first bonding structure 117 is formed on the front side of the semiconductor substrate 111, it can be considered a front-side bonding structure. For example, the first bonding structure 117 includes a first bonding dielectric layer 1171 and one or more first bonding features 1172 covered by the first bonding dielectric layer 1171. The first bonding dielectric layer 1171 may be formed on the topmost of one of the dielectric layers (e.g., 1151d) of the dielectric layer 1151. The first bonding dielectric layer 1171 may be a single layer or include multiple stacked dielectric layers. The material of the first bonding dielectric layer 1171 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonoxynitride, or combinations thereof. The first bonding dielectric layer 1171 may be formed using suitable manufacturing techniques (e.g., spin coating, CVD, ALD, PVD, or similar).

[0035] The first bonding feature 1172 may include one or more conductive materials, such as Cu, Co, W, Ti, Ta, Al, alloys, combinations thereof, or other suitable metallic materials. In some embodiments, the first bonding feature 1172 is formed by a damascene process (e.g., single damascene and / or double damascene). The first bonding feature 1172 may be or include one or more conductive pads, one or more vias, combinations thereof, etc. The first bonding feature 1172 may be electrically connected to the conductive layer 1152. For example, the first bonding feature 1172 is located on the topmost one of the conductive sublayers (e.g., 1152d) of the conductive layer 1152. In some embodiments, the first bonding feature 1172 is electrically isolated from the thermal sensing device 116. In some embodiments, a planarization process (e.g., polishing, CMP, etching, combinations thereof, or the like) is performed on the first bonding structure 117. After planarization, the exposed surfaces 1171t of the first bonding dielectric layer 1171 and 1172t of the first bonding feature 1172 can be substantially flush (or coplanar) within the range of process variations. The exposed surfaces (1171t and 1172t) can be collectively referred to as the bonding surface 117t of the first bonding structure 117.

[0036] Reference Figure 4 And refer to Figure 3Thinning processes (e.g., polishing, CMP, etching, combinations thereof) can be performed on the back side of the semiconductor substrate 111. After the thinning process, at least a portion of the second end 114b of the corresponding through-hole 114 can be exposed in an accessible manner from the back side 111b' of the semiconductor substrate 111'. According to some embodiments, the through-hole 114 may be referred to as a through-substrate via (TSV) 114 because it penetrates the semiconductor substrate 111'. In some embodiments, a carrier 121 is disposed on the first bonding structure 117. For example, the carrier 121 is bonded to the bonding surface 117t of the first bonding structure 117. In some embodiments, the carrier 121 is a temporary carrier for supporting the underlying structure during processes (e.g., thinning processes, bonding processes, monomerization processes, etc.) and can be removed once the bonding process is complete. In some embodiments, the carrier 121 provides mechanical and structural support in the resulting semiconductor structure. The carrier 121 may comprise any suitable material with sufficient rigidity to provide support for the underlying structure. In some embodiments, the carrier 121 includes one or more thermally conductive materials to facilitate heat dissipation from the underlying structure to the external environment or to the upper structure (if any). For example, the carrier 121 includes silicon (e.g., bulk silicon), metal (e.g., steel), glass, ceramic, combinations thereof, multilayers thereof, or the like. Bonding of the carrier 121 may be performed prior to the thinning process of the semiconductor substrate 111. Alternatively, the carrier 121 may be bonded to the first bonding structure 117 after the semiconductor substrate 111 has been thinned.

[0037] Reference Figure 5 And refer to Figure 4A second bonding structure 118 may be formed on the TSV 114 and the semiconductor substrate 111'. Since the second bonding structure 118 is formed on the back side of the semiconductor substrate 111', it can be considered a back-side bonding structure. The second bonding structure 118 may include a second bonding dielectric layer 1181 and one or more second bonding features 1182 covered by the second bonding dielectric layer 1181. The second bonding dielectric layer 1181 may be formed on the back side 111b' of the semiconductor substrate 111'. The material of the second bonding dielectric layer 1181 may be similar to the material of the first bonding dielectric layer 1171. The second bonding feature 1182 may be located on the second end 114b of the TSV 114 and electrically connected to the interconnect structure 115 via the TSV 114. The material of the second bonding feature 1182 may be similar to the material of the first bonding feature 1172. In some embodiments, a planarization process (e.g., polishing, CMP, etching, a combination thereof, or the like) is performed on the second bonding structure 118. After planarization, the exposed surfaces 1181t of the second bonding dielectric layer 1181 and the exposed surfaces 1182t of the second bonding feature 1182 can be substantially flush (or coplanar) within the range of process variations. The exposed surfaces (1181t and 1182t) can be collectively referred to as the bonding surface 118t of the second bonding structure 118.

[0038] Reference Figure 6 And refer to Figure 5 , Figure 5 The structure shown can be bonded to another structure to form semiconductor structure 10, the other structure being similar to Figure 5 The structure shown is a semiconductor structure 10. The semiconductor structure 10 may include a first layer T1 and a second layer T2 stacked on and bonded to the first layer T1. It should be noted that, for illustrative purposes, a semiconductor structure 10 comprising two layers is shown; however, according to some embodiments, the semiconductor structure may include two or more layers stacked on top of each other. The second layer T2 may be... Figure 5 The structure excluding the carrier 121. The first layer T1 may be similar to the second layer T2. Differences between the first layer T1 and the second layer T2 may include: the first layer T1 may or may not include a TSV, the semiconductor substrate 111 of the first layer T1 may or may not be thinned, and the thermal sensing device 116 in the first layer T1 may or may not be arranged in a different manner than the thermal sensing device 116 in the second layer T2. In some embodiments, each of the first layer T1 and the second layer T2 includes one or more thermal sensing devices 116 for sensing temperature. Alternatively, one of the first layer T1 and the second layer T2 includes a thermal sensing device 116 and the other of the first layer T1 and the second layer T2 does not have a thermal sensor.

[0039] In some embodiments, repeatable Figure 1 , Figure 2A , Figure 3 , Figure 4 and Figure 5 The aforementioned steps are used to form multiple layers to be bonded. Layer bonding may include wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, or the like. In some embodiments where die-to-wafer bonding or die-to-die bonding will be performed, Figure 5 The structures shown can be monomerized to form multiple dies prior to bonding. In some embodiments, the bonding process includes at least the following steps. For example, surface preparation (e.g., cleaning, activation, combinations thereof) can be performed on the bonding surfaces 118t of the second layer T2 and 117t of the first layer T1. After surface preparation, the second layer T2 can be substantially aligned with the first layer T1. For example, each of the second bonding features 1182 of the second layer T2 can be substantially aligned with a corresponding one of the first bonding features 1172 of the first layer T1. Then, the bonding surface 118t of the second bonding structure 118 of the second layer T2 can contact the bonding surface 117t of the first bonding structure 117 of the first layer T1.

[0040] After the second layer T2 is brought into contact with the first layer T1, a bonding process can be performed. For example, the bonding process includes heat treatment for dielectric bonding and thermal annealing for conductor bonding. After thermal annealing, the first bonding dielectric layer 1171 of the first layer T1 can be melted to the second bonding dielectric layer 1181 of the second layer T2, and the first bonding feature 1172 of the first layer T1 can be bonded to the second bonding feature 1182 of the second layer T2. The bonding at the bonding interface IF1 between the first layer T1 and the second layer T2 can include dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), any combination thereof, and / or similar. The bonding interface IF1 can be substantially planar and / or flat. The first and second bonding features (1172 and 1182) can be pad-to-pad bonding, via-to-via bonding, or via-to-pad bonding, depending on product requirements.

[0041] Continue to refer to Figure 6The bonding of semiconductor structure 10 can be considered as a front-to-back bonding, wherein the first bonding structure 117 of the first layer T1 is bonded to the second bonding structure 118 of the second layer T2. In some other embodiments, depending on product requirements, front-to-front bonding (e.g., the first bonding structure 117 of the first layer T1 is bonded to the first bonding structure 117 of the second layer T2) or back-to-back bonding (e.g., the second bonding structure 118 of the first layer T1 is bonded to the second bonding structure 118 of the second layer T2) may be applied. It should be understood that although a bonding of the second layer T2 to the first layer T1 has been described, alternative connection schemes may be possible, with corresponding modifications to the bonding interface.

[0042] Still refer to Figure 6 The semiconductor structure 10 may include a heat dissipation component 122 disposed on a carrier 121. The heat dissipation component 122 may be formed of a material with high thermal conductivity (e.g., steel, stainless steel, copper, or combinations thereof, or any material with good thermal conductivity for a heat dissipation mechanism). In some embodiments, the heat dissipation component 122 is coated with another metal. The heat dissipation component 122 may be a single continuous material or may include multiple segments having the same or different materials. The heat dissipation component 122 may be or include a heat sink, heat spreader, lid, etc. Figure 6 The heat dissipation component 122 is provided for illustrative purposes, and the heat dissipation component 122 can be provided in any suitable form (e.g., plate, fin, etc.).

[0043] In some embodiments, the heat dissipation component 122 is attached to the carrier 121 by an adhesive (not shown separately). The adhesive may be epoxy, glue, or the like, and may include thermally conductive materials or any material capable of heat transfer. The heat dissipation component 122 may be thermally coupled to the underlying structure by an adhesive. The adhesive may be deposited at one or more intended locations to allow the heat dissipation component 122 to adhere to the carrier 121. Alternatively, the carrier 121 may be omitted and the heat dissipation component 122 may be directly coupled to the second layer T2. In other embodiments, the heat dissipation component 122 is omitted. It should be noted that the heat dissipation component 122 may be any type of heat dissipation mechanism that meets the heat dissipation requirements of the semiconductor structure 10. In some embodiments, a monomerization process is performed to dicing the bonded structure into multiple semiconductor structures 10. Then, depending on requirements, the respective semiconductor structures 10 may be packaged or coupled to another package assembly.

[0044] Embodiments may have one or a combination of the following features and / or advantages. Embodiments of thermal sensing device 116 may be integrated into semiconductor circuitry fabricated using a BEOL process. Thermal sensing device 116 may be routed to a front-end device (e.g., first device 112) to measure temperature, or the measurement circuitry may be constructed on a back-end using a back-end device (e.g., second device 1162). Thermal sensing device 116 may include control circuitry configured to receive temperature-related parameters and generate control signals. The control circuitry including second device 1162 may be formed of BEOL-compatible materials for rapid and accurate temperature sensing. Thermal sensing device 116 may include a thermal sensing component 1161 thermally coupled to the device / area / path to be monitored and implemented via resistors, two-terminal devices, combinations thereof, or the like. Thermal sensing device 116 may be formed of BEOL-compatible materials and may have a temperature-dependent resistance. Feedback circuitry connected to thermal sensing device 116 may be configured to dynamically control the power input to the corresponding layer of semiconductor structure 10. For example, the circuit operation is adjusted in response to the sensed / measured temperature to reduce or avoid overheating, thereby enhancing the performance and reliability of the semiconductor structure 10.

[0045] The placement of the thermal sensing device 116 can be flexible. More than one thermal sensing device 116 can be placed at various locations throughout the semiconductor structure 10. For example, the thermal sensing devices 116 can be spaced above areas of the interconnect structure 115 to obtain heat distribution of corresponding layers. The thermal sensing devices 116 can be placed near temperature-sensitive circuits / devices / areas / paths to obtain high-precision temperature readings in sensitive areas. Arranging multiple thermal sensing components 1161 in an array within different layers of the semiconductor structure 10 can increase the accuracy of the thermal sensing devices 116 and establish a 3D temperature distribution map, thereby achieving precise temperature sensing.

[0046] According to some embodiments, a semiconductor structure includes a first interconnect structure disposed above a first semiconductor substrate, a plurality of thermal sensors embedded in the first interconnect structure and sensing temperature changes in the semiconductor structure, and a first bonding structure disposed on and electrically coupled to the first interconnect structure. The thermal sensors are electrically isolated from the conductive features of the first interconnect structure and the conductive features of the first bonding structure.

[0047] In some embodiments, the semiconductor structure further includes a plurality of first transistors and a plurality of second transistors. The first transistors are disposed above the first semiconductor substrate and below the first interconnect structure, and are electrically coupled to the conductive features of the first interconnect structure. The second transistors, included in the thermal sensor, are embedded in the first interconnect structure above the first transistors and are electrically isolated from the conductive features of the first interconnect structure. In some embodiments, the second transistors include a two-dimensional material channel layer. In some embodiments, the semiconductor structure further includes a plurality of transistors disposed above the first semiconductor substrate and below the first interconnect structure. The transistors include a first transistor electrically coupled to the conductive features of the first interconnect structure and a second transistor electrically coupled to the thermal sensor. In some embodiments, the thermal sensor includes a plurality of thermal sensing components at different horizontal heights of the first interconnect structure, and the thermal sensing components include a heat-related resistance value. In some embodiments, the thermal sensing components include a two-dimensional material layer. In some embodiments, the thermal sensing components include at least one metal resistor. In some embodiments, the semiconductor structure further includes a plurality of first devices and a plurality of second devices. The first devices are disposed on a first region, and a first group of thermal sensors is arranged to sense temperature changes in the first region. The second devices are disposed on a second region, and a second group of thermal sensors is arranged to sense temperature changes in the second region. The first devices consume more power than the second devices, wherein the distribution density of the first group of thermal sensors is greater than the distribution density of the second group of thermal sensors. In some embodiments, the first bonding structure includes a first bonding dielectric layer and a first bonding feature covered by the first bonding dielectric layer and electrically coupled to the conductive feature of the first interconnect structure. The bonding surface of the first bonding dielectric layer and the bonding surface of the first bonding feature are substantially flush. In some embodiments, the semiconductor structure further includes a second interconnect structure disposed above a second semiconductor substrate, a substrate via penetrating the second semiconductor substrate and electrically coupled to the second interconnect structure, and a second bonding structure disposed below the second semiconductor substrate and electrically coupled to the second interconnect structure through the substrate via. The second bonding structure is bonded to the first bonding structure, and the bonding interface of the first bonding structure and the bonding interface of the second bonding structure are substantially flush.

[0048] According to some embodiments, a semiconductor structure includes a hot spot region above a semiconductor substrate, an interconnect structure above the semiconductor substrate, and a plurality of thermal sensors embedded at different horizontal heights in the interconnect structure. The thermal sensors include a plurality of first sensors for monitoring temperature changes in the hot spot region and a plurality of second sensors for monitoring temperature changes in regions outside the hot spot region, with the first sensors arranged in a more dense manner than the second sensors.

[0049] In some embodiments, each of the thermal sensors includes a control transistor comprising a channel layer, wherein the channel layer of the control transistor comprises a material different from the channel material of a transistor disposed above the semiconductor substrate and below the interconnect structure. In some embodiments, the material of the channel layer of the control transistor has a higher temperature coefficient of resistance than the conductive material of the conductive characteristics of the interconnect structure. In some embodiments, each of the thermal sensors includes at least one control transistor covered by a dielectric layer of the interconnect structure and a plurality of sensing components connected to the at least one control transistor and distributed at different horizontal heights of the interconnect structure, the sensing components being disposed near the hot spot region. In some embodiments, the sensing components comprise a material having a higher temperature coefficient of resistance than the conductive material of the conductive characteristics of the interconnect structure.

[0050] According to some embodiments, a method for manufacturing a semiconductor structure includes: forming an interconnect structure over a semiconductor substrate using a BEOL process; forming a plurality of thermal sensors over the semiconductor substrate and in the interconnect structure, wherein the thermal sensors are formed of a material compatible with the BEOL process; and forming a bonding structure over the interconnect structure, wherein the thermal sensors are electrically isolated from the conductive features of the interconnect structure and the conductive features of the bonding structure.

[0051] In some embodiments, the manufacturing method further includes forming a plurality of first transistors over the semiconductor substrate via a front-end process and forming a plurality of second transistors in the interconnect structure via a back-end process, wherein the interconnect structure covers and is electrically coupled to the first transistors, and the second transistors are included in the thermal sensor. In some embodiments, forming the thermal sensor includes forming a plurality of metal resistors at different horizontal heights of the interconnect structure. In some embodiments, forming the thermal sensor includes forming a plurality of thermal sensing components at different horizontal heights of the interconnect structure, wherein the thermal sensing components include a two-dimensional material layer. In some embodiments, the manufacturing method further includes planarizing the bonding structure to make the bonding surface of the bonding structure flat.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor structure, characterized by, comprise: a first interconnect structure disposed over a first semiconductor substrate; a plurality of thermal sensors embedded in the first interconnect structure and sensing temperature changes in the semiconductor structure; and a first bonding structure disposed on and electrically coupled to the first interconnect structure, the thermal sensors being electrically isolated from conductive features of the first interconnect structure and conductive features of the first bonding structure.

2. The semiconductor structure of claim 1, wherein, further comprising: a plurality of first transistors disposed over the first semiconductor substrate and under the first interconnect structure, the first transistors being electrically coupled to the conductive features of the first interconnect structure; and a plurality of second transistors included in the thermal sensors, embedded in the first interconnect structure over the first transistors, and electrically isolated from the conductive features of the first interconnect structure.

3. The semiconductor structure of claim 2, wherein, wherein the second transistors comprise a two-dimensional material channel layer.

4. The semiconductor structure of claim 1, wherein, further comprising: a plurality of transistors disposed over the first semiconductor substrate and under the first interconnect structure, the transistors comprising first transistors electrically coupled to the conductive features of the first interconnect structure and second transistors electrically coupled to the thermal sensors.

5. The semiconductor structure of claim 1, wherein, wherein the thermal sensors comprise a plurality of thermal sensor components at different horizontal levels of the first interconnect structure, and the thermal sensor components comprise a resistance value related to heat.

6. The semiconductor structure of claim 1, wherein, wherein the first bonding structure comprises a first bonding dielectric layer and a first bonding feature covered by the first bonding dielectric layer and electrically coupled to the conductive features of the first interconnect structure, and bonding surfaces of the first bonding dielectric layer and the first bonding feature are substantially flush.

7. The semiconductor structure of claim 1, wherein, further comprising: a second interconnect structure disposed over a second semiconductor substrate; a substrate via through the second semiconductor substrate and electrically coupled to the second interconnect structure; and a second bonding structure disposed under the second semiconductor substrate and electrically coupled to the second interconnect structure through the substrate via, the second bonding structure bonded to the first bonding structure, bonding interfaces of the first bonding structure and the second bonding structure being substantially flush.

8. A semiconductor structure, characterized by comprise: a hotspot region over a semiconductor substrate; an interconnect structure over the semiconductor substrate; and a plurality of thermal sensors embedded in different horizontal levels of the interconnect structure, the thermal sensors comprising a plurality of first sensors monitoring temperature changes of the hotspot region and a plurality of second sensors monitoring temperature changes of an area outside the hotspot region, and the first sensors are arranged in a denser manner than the second sensors.

9. The semiconductor structure of claim 8, wherein, wherein each of the thermal sensors comprises: a control transistor comprising a channel layer, wherein the channel layer of the control transistor comprises a material different from a channel material of a transistor disposed over the semiconductor substrate and under the interconnect structure.

10. The semiconductor structure of claim 9, wherein, wherein the material of the channel layer of the control transistor has a higher temperature coefficient of resistance than a conductive material of a conductive feature of the interconnect structure.

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