Power semiconductor packaging structure

Abstract

The utility model discloses a power semiconductor packaging structure which comprises a substrate, a power semiconductor chip, a PCB and a packaging sealing layer. The substrate upper conductive metal layer comprises a left side metal layer and a right side metal layer which are physically separated by a separation groove and are electrically insulated; a sinking left mounting platform is arranged on the side, close to the separation groove, of the left metal layer, a sinking right mounting platform is arranged in the middle of the right metal layer, the right mounting platform is used for arranging a chip, and the PCB is erected on the left mounting platform and the right mounting platform; the drain electrode of the chip is interconnected with the right mounting platform; the left side metal layer is connected to a chip source electrode through the PCB, the PCB is provided with an extension part used for being connected with an external driving circuit of the power semiconductor packaging structure on the edge of one side of the right side metal layer, and the extension part enables a grid electrode and the source electrode of the chip to be connected with a driving circuit of an external circuit. A substrate connecting part electrically connected with the left mounting platform is arranged on the back surface of the PCB; and a chip connecting part interconnected with the source electrode of the chip is arranged on the back surface of the PCB.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device technology, and more specifically to a power semiconductor packaging structure. Background Technology

[0002] Power semiconductor packaging is an industrial product that enables power semiconductor chips to make electrical connections to external circuit boards, provide thermal conductivity to external heat sinks, and protect the power semiconductor chips. Power semiconductor packaging has the following functions: providing electrical contact with the semiconductor chip, typically achieved through bonding wires, ensuring connection to external electrical interfaces; providing adequate connections for heat sinks and cooling systems to dissipate hundreds or thousands of watts of heat loss; and protecting the semiconductor from environmental influences, particularly moisture intrusion.

[0003] Existing power semiconductor packaging structures are very diverse. For example, CN 219435850U discloses a MOSFET chip power semiconductor packaging structure, which includes a plastic encapsulation shell and a silicon chip disposed within the plastic encapsulation shell. The plastic encapsulation shell also contains multiple copper strips bonded to the top of the silicon chip, source pins and gate pins bonded to one end of different copper strips, drain pins bonded to the bottom of the silicon chip, and a thermally conductive base plate connected to the bottom of the drain pins. A metal shell is bonded to the plastic encapsulation shell. Heat is conducted to the PCB base plate through the drain pins and the thermally conductive base plate, providing more heat dissipation contact area and carrying heat away from the silicon chip. At the same time, by having a metal shell on the plastic encapsulation shell, and by having the metal shell wrap around the extension end of the drain pin, heat can also be conducted to the metal shell. Heat dissipation through the metal shell is better, and it can still meet the heat dissipation requirements when the current demand increases, avoiding PCB thermal saturation.

[0004] The fabrication process of the power semiconductor device packaging structure disclosed in document CN110676176B, by setting a flexible conductive layer and an insulating plate with a double-sided conductive layer, ensures that the E electrode does not directly act on the chip assembly. The current of the chip assembly reaches the E electrode through the flexible conductive layer, and the heat of the chip assembly is conducted vertically through the flexible conductive layer to the heat dissipation medium (e.g., to the surrounding electrodes). The first conductive protrusion supports the flexible conductive layer, dispersing the compressive stress acting on the chip assembly. The flexible conductive layer achieves a smaller compressive stress on the bonding surface of the chip assembly, avoiding large pressure acting directly on the surface of the chip assembly, reducing triaxial stress damage under high pressure stress conditions during chip assembly temperature cycling, improving connection reliability, achieving decoupling of pressure from conductivity and heat conduction, and ultimately improving the reliability of the power semiconductor device packaging structure.

[0005] The power semiconductor device packaging architecture disclosed in document CN114551378A belongs to the technical field of semiconductor power device mounting structures. It at least solves the technical problem of low heat dissipation efficiency in existing leadless designs. The packaging includes a package container and a heat sink partially embedded in the top of the package container. The package container contains a heat dissipation component that can clamp or wrap the power device, is electrically connected to the power device, and is in contact with the heat sink. The heat generated by the power device during operation is transferred to the heat sink via thermal conduction through the heat dissipation component to cool or dissipate heat from the power device. Summary of the Invention

[0006] The technical problem to be solved by this utility model is to provide a power semiconductor packaging structure with stable performance and good heat dissipation.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: a power semiconductor packaging structure, including a substrate, a power semiconductor chip, and an interconnect printed circuit board (PCB) connecting the power semiconductor chip and corresponding parts on the substrate; the substrate is provided with a packaging sealing layer that encapsulates the power semiconductor chip and the interconnect printed circuit board (PCB).

[0008] The substrate includes an intermediate insulating layer, an upper conductive metal layer, and a lower conductive metal layer. The lower conductive metal layer is used to connect a heat sink. The upper conductive metal layer includes a left metal layer and a right metal layer that are physically separated and electrically insulated by a partition groove. A recessed left mounting platform is provided on the left metal layer near the partition groove, and a recessed right mounting platform is provided in the middle part of the right metal layer. The right mounting platform is used to set up power semiconductor chips, and the interconnect printed circuit board (PCB) is mounted on the left and right mounting platforms.

[0009] The drain of the power semiconductor chip is located at the bottom, and the source and gate of the power semiconductor chip are located at the top. The drain of the power semiconductor chip is interconnected with the right mounting platform. The left metal layer is connected to the source of the power semiconductor chip through an interconnect printed circuit board (PCB). The interconnect PCB has an extension on the edge near the right metal layer for connecting to the external driving circuit of the power semiconductor package structure. The extension connects the source and gate of the power semiconductor chip to the driving circuit of the external circuit.

[0010] The interconnect printed circuit board (PCB) includes an insulating substrate. The reverse side of the interconnect printed circuit board (PCB) has a substrate connection part, which is electrically connected to the left mounting platform on the substrate. The higher surface of the copper layer on the left side serves as the interface of the entire power semiconductor package structure to the outside. The reverse side of the interconnect printed circuit board (PCB) also has a power semiconductor chip connection part that interconnects with the source of the power semiconductor chip.

[0011] The substrate corresponding part on the front side of the interconnect printed circuit board (PCB) and the substrate connection part on the back side are electrically interconnected through a number of first conductive vias; the back side of the interconnect printed circuit board (PCB) is provided with a gate connection part connected to the gate, and the chip corresponding part on the front side of the interconnect printed circuit board (PCB) and the power semiconductor chip connection part on the back side are electrically interconnected through a number of second conductive vias.

[0012] The extension of the interconnect printed circuit board (PCB) and the top surfaces of the left and right metal layers at the two far ends of the substrate expose the encapsulation sealing layer for interconnection with the external main circuit.

[0013] As a preferred embodiment, the interconnect printed circuit board (PCB) is provided with a plurality of through holes for the sealing material of the encapsulation sealing layer to penetrate into the free space below the interconnect printed circuit board (PCB) during encapsulation.

[0014] As a preferred embodiment, the extension portion is provided with a reverse conductive portion that is connected to the gate connection portion and a front conductive portion that is connected to the power semiconductor chip connection portion.

[0015] The beneficial effects of this utility model are:

[0016] This packaging structure achieves parasitic inductance cancellation, reducing it to a very low level; it reduces parasitic parameters in power semiconductor packages, improving the high-frequency performance of the circuit; and the negative coupling design between the chip and the DC bus further reduces parasitic inductance; injection molding or silicone encapsulation is used to achieve sealed protection of the chip, preventing the intrusion of moisture and other environmental factors.

[0017] Because the flexible PCB design has several through holes that run vertically through the packaging process, the sealing material of the packaging layer can penetrate into the free space under the interconnect printed circuit board PCB. This facilitates better penetration of the packaging material, making the packaged structure more robust, further ensuring reliability, and improving sealing performance and electrical isolation.

[0018] This structure can directly form chip mounting recesses and electrical connection areas through a stepped etching process, reducing the complexity of multi-step processing in traditional packaging; and it uses connection processes such as silver sintering or soldering to provide a reliable and efficient assembly method.

[0019] This flexible PCB structure provides stress relief, effectively reducing the impact of thermal expansion or mechanical vibration on chip connections; it can also use high thermal conductivity isolation substrates such as DBC or AMB, effectively reducing thermal resistance during device operation; the stepped etching design ensures close contact between the chip and the substrate, thereby optimizing the heat conduction path. Attached Figure Description

[0020] Figure 1This is a schematic diagram of the internal structure of a power semiconductor package.

[0021] Figure 2 This is a schematic diagram of the structure of a power semiconductor chip.

[0022] Figure 3(a) is a schematic diagram of the front structure of the interconnect printed circuit board (PCB); Figure 3(b) is a schematic diagram of the back structure of the interconnect printed circuit board (PCB).

[0023] Figure 4 This is a schematic diagram of a power semiconductor package structure connected to the main circuit board.

[0024] Figure 5 This is a schematic diagram of the overall packaged power semiconductor structure.

[0025] In the figure: power semiconductor package structure 100, substrate 200, power semiconductor chip 300, interconnect printed circuit board 400, and encapsulation sealing layer 600;

[0026] The substrate includes an upper conductive metal layer 201, a middle insulating layer 202, a lower conductive metal layer 203, a right mounting platform 204, a partition groove 205, a right metal layer 206, a left metal layer 207, and a left mounting platform 208.

[0027] Source 301, gate 302, drain 303; extension portion 401, insulating substrate 402;

[0028] Substrate corresponding part 410, potting hole 411, front conductive part 412, potting hole 413;

[0029] The substrate connection portion 420, the first conductive via 421, the power semiconductor chip connection portion 422, the gate connection portion 423, and the reverse conductive portion 424. Detailed Implementation

[0030] The specific implementation scheme of this utility model will now be described in detail with reference to the accompanying drawings.

[0031] like Figure 1-5 As shown, the power semiconductor package structure 100 includes a substrate 200, a power semiconductor chip 300, and an interconnect printed circuit board 400 connecting the power semiconductor chip 300 and corresponding parts on the substrate 200; the substrate is provided with a packaging sealing layer 600 that encapsulates the power semiconductor chip 300 and the interconnect printed circuit board 400.

[0032] like Figure 1As shown, the substrate 200 includes an intermediate insulating layer 202, an upper conductive metal layer 201, and a lower conductive metal layer 203. The lower conductive metal layer 203 is used to connect a heat sink. A power semiconductor chip 300 is disposed on the upper conductive metal layer 201, and the upper conductive metal layer 201 serves as part of an electrical connection to connect the power semiconductor chip 300 to other circuit boards or conductors.

[0033] The conductive metal layer 201 on the upper part of the substrate includes a left metal layer 207 and a right metal layer 206 that are physically separated and electrically insulated by a partition groove 205; a recessed left mounting platform 208 is provided on the left metal layer 207 near the partition groove 205, and a recessed right mounting platform 204 is provided in the middle part of the right metal layer 206. The right mounting platform 204 is used to mount the power semiconductor chip 300, and the interconnect printed circuit board 400 is mounted on the left mounting platform 208 and the right mounting platform 204; the drain 303 of the power semiconductor chip is interconnected with the right mounting platform 204.

[0034] like Figure 2 As shown, the drain 303 of the power semiconductor chip 300 is located at the bottom, and the source 301 and gate 302 of the power semiconductor chip 300 are located at the top.

[0035] The left metal layer 207 is connected to the source 301 of the power semiconductor chip 300 via the interconnect printed circuit board 400. The interconnect printed circuit board 400 has an extension 401 on the edge near the right metal 206 for connecting to the external driving circuit of the power semiconductor package structure. The extension 401 connects the gate 302 and the source 301 of the power semiconductor chip to the driving circuit of the external circuit.

[0036] As shown in Figures 3(a) and 3(b), the interconnect printed circuit board 400 includes an insulating substrate 402. The reverse side of the interconnect printed circuit board 400 is provided with a substrate connection portion 420, which is electrically connected to the left mounting platform 208 on the substrate 200. The higher surface of the copper layer of the left metal layer 207 serves as the external interface of the entire power semiconductor package structure 100. The reverse side of the interconnect printed circuit board 400 is provided with a power semiconductor chip connection portion 422 that is interconnected with the source 301 of the power semiconductor chip.

[0037] The substrate corresponding portion 410 on the front side of the interconnect printed circuit board PCB 400 and the substrate connection portion 420 on the back side are electrically interconnected through a plurality of first conductive vias 421. The back side of the interconnect printed circuit board PCB 400 is provided with a gate connection portion 423 connected to the gate 302, and the extension portion 401 is provided with a reverse conductive portion 424 connected to the gate connection portion 423 and a front conductive portion 412 connected to the power semiconductor chip connection portion 422. The chip corresponding portion on the front side of the interconnect printed circuit board PCB 400 and the power semiconductor chip connection portion 422 on the back side are electrically interconnected through a plurality of second conductive vias.

[0038] The interconnect printed circuit board PCB400 is provided with a plurality of vertically penetrating potting holes 413 for allowing the sealing material of the encapsulation sealing layer 600 to penetrate into the free space below the interconnect printed circuit board PCB400 during encapsulation.

[0039] The extension 401 of the interconnect printed circuit board PCB 400, used for connecting external drive circuits, and the top surfaces of the left and right metal layers 207 and 206 on the substrate, expose the encapsulation sealing layer 600 for interconnection with the external main circuit. It can be directly connected to the main circuit board 500, such as... Figure 4 As shown.

[0040] This structure is applicable to power semiconductors with vertical structures (such as SiC MOSFETs) and can also be extended to other types of power devices, such as devices with lateral structures.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some examples of its application, and are not intended to limit the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements are all within the protection scope of the present invention.

Claims

1. A power semiconductor package structure (100) comprising a substrate (200), a power semiconductor chip (300), an interconnection printed circuit board (PCB) (400) connecting the power semiconductor chip (300) and a corresponding part of the substrate (200); characterized in that: The substrate is provided with a packaging sealing layer (600) wrapping a power semiconductor chip (300) and an interconnection printed circuit board (PCB) (400); The substrate (200) comprises an intermediate insulating layer (202), an upper conductive metal layer (201) of the substrate, and a lower conductive metal layer (203) of the substrate, the lower conductive metal layer (203) of the substrate is used to connect a heat sink; the upper conductive metal layer (201) of the substrate comprises a left metal layer (207) and a right metal layer (206) which are physically separated and electrically insulated by a separation groove (205); a sunken left mounting platform (208) is arranged on one side of the left metal layer (207) close to the separation groove (205), and a sunken right mounting platform (204) is arranged on the middle part of the right metal layer (206), the right mounting platform (204) is used to arrange the power semiconductor chip (300), and the interconnection printed circuit board (PCB) (400) is arranged on the left mounting platform (208) and the right mounting platform (204); The drain (303) of the power semiconductor chip (300) is located at the bottom, and the source (301) and the gate (302) of the power semiconductor chip (300) are located at the top; the drain (303) of the power semiconductor chip is interconnected with the right mounting platform (204); the left metal layer (207) is connected to the source (301) of the power semiconductor chip (300) through the interconnection printed circuit board (PCB) (400), and the interconnection printed circuit board (PCB) (400) is provided with an extension part (401) on the edge close to the right metal layer (206) for connecting with an external driving circuit of the power semiconductor packaging structure, the extension part (401) connects the source (301) and the gate (302) of the power semiconductor chip (300) with the driving circuit of the external circuit; The interconnection printed circuit board (PCB) (400) comprises an insulating substrate (402), and the back of the interconnection printed circuit board (PCB) is provided with a substrate connecting part (420) which is electrically connected with the left mounting platform (208) on the substrate (200), and the higher surface of the copper layer of the left metal layer (207) serves as an external interface of the entire power semiconductor packaging structure (100); the back of the interconnection printed circuit board (PCB) (400) is provided with a power semiconductor chip connecting part (422) which is interconnected with the source (301) of the power semiconductor chip; The substrate corresponding part (410) on the front of the interconnection printed circuit board (PCB) (400) and the substrate connecting part (420) on the back are electrically interconnected through a plurality of first conductive vias; the back of the interconnection printed circuit board (PCB) (400) is provided with a gate connecting part (423) which is connected with the gate (302), and the chip corresponding part on the front of the interconnection printed circuit board (PCB) (400) and the power semiconductor chip connecting part (422) on the back are electrically interconnected through a plurality of second conductive vias; The extension part (401) of the interconnection printed circuit board (PCB) (400) and the top surfaces of the two distal left metal layers (207) and right metal layers (206) on the substrate are exposed from the packaging sealing layer (600) and used for interconnection with an external main circuit.

2. A power semiconductor package structure as claimed in claim 1, characterized in that: The interconnection printed circuit board (PCB) (400) is provided with a plurality of upper and lower through holes (411) for filling the encapsulating material of the encapsulating layer (600) into the free space below the interconnection printed circuit board (PCB) (400) during encapsulation.

3. A power semiconductor package structure as claimed in claim 1, characterized in that: The extension part (401) is provided with a reverse surface conductive part (424) in conduction with the gate connecting part (423) and a front surface conductive part (412) in conduction with the power semiconductor chip connecting part (422).

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