Multi-channel high-speed fiber bragg grating demodulation device

Abstract

The utility model relates to the technical field of fiber bragg grating demodulation, in particular to a multichannel high-speed fiber bragg grating demodulation device, which comprises an optical path module and an electric signal module, the optical path module comprises a tunable laser unit, a PLC (programmable logic controller) unit and a plurality of FBG (fiber bragg grating) sensors, the PLC unit comprises an optical splitter and a plurality of couplers, the electric signal module comprises a main control unit, a photoelectric conversion unit, a DC / DC unit, a 485 communication unit and an Ethernet communication unit, optical signals emitted by the tunable laser unit pass through an optical splitter and a multi-path coupler and then enter an FBG sensor, light is reflected by a grating and then is connected to a photodiode through the coupler, and the photoelectric conversion unit is connected to the Ethernet communication unit. And after photoelectric conversion, AD conversion and peak searching algorithm processing, the optical wavelength is demodulated. According to the utility model, a chip-level data acquisition design is adopted, the scanning speed of the demodulator is improved, fusion with a field system is facilitated through the 485 communication unit, and a heterogeneous system of the master control unit and the FPGA unit is adopted, so that the edge computing capability is enhanced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of fiber grating demodulation, in particular to a kind of multi-channel high-speed fiber grating demodulation device. BACKGROUND

[0002] Fiber grating demodulator is a kind of core equipment for detecting fiber grating sensor signal, and its main function is to convert wavelength shift caused by the change of external physical quantity (such as strain, temperature, pressure, etc.) of fiber grating into readable electrical signal or digital data.

[0003] There are many problems in the existing fiber grating demodulator, first, there is a lack of interface with industrial field control system; second, the anti-interference ability is weak, the analog signal processing circuit is easy to be disturbed by noise, which affects the demodulation accuracy; in addition, the edge computing ability is insufficient. UTILITY MODEL CONTENT

[0004] The utility model aims at providing a kind of multi-channel high-speed fiber grating demodulation device to solve the problems raised in the above background.

[0005] To achieve the above object, the utility model provides the following technical scheme:

[0006] A kind of multi-channel high-speed fiber grating demodulation device, including optical path module and electrical signal module, the optical path module includes tunable laser unit, PLC unit and several FBG sensors, the PLC unit includes beam splitter and several couplers, the electrical signal module includes main control unit, photoelectric conversion unit, DC / DC unit, 485 communication unit and Ethernet communication unit, the photoelectric conversion unit, the DC / DC unit, the 485 communication unit and the Ethernet communication unit are electrically connected with the main control unit, the photoelectric conversion unit includes several photodiodes, several logarithmic amplification circuits, several Butterworth filters, several differential operational amplifier circuits, several AD conversion circuits and FPGA unit, the photodiode, the logarithmic amplification circuit, the Butterworth filter, the differential operational amplifier circuit, the AD conversion circuit and the FPGA unit are electrically connected in sequence, the light signal emitted by the tunable laser unit passes through the beam splitter and multiple couplers, and the light signal enters the FBG sensor, after light is reflected by grating, it is accessed to the photodiode by the coupler, and after photoelectric conversion, AD conversion, peak searching algorithm processing, the light wavelength is demodulated.

[0007] As preferred, the DC / DC unit is used to power the tunable laser unit and the main control unit, the tunable laser unit and the main control unit are connected through serial port, and the tunable laser unit also sends trigger signal to the main control unit.

[0008] As preferred, the logarithmic amplification circuit comprises a potentiometer chip U1, a capacitor C1 and an operational amplifier U2, the model of the potentiometer chip U1 is AD5160, and the model of the operational amplifier U2 is ADA4817-1;

[0009] The first end of the capacitor C1 is connected to the W port of the potentiometer chip U1, the second end of the capacitor C1 is connected to the A port of the potentiometer chip U1, the output of the photodiode is connected to the second end of the capacitor C1, the FB port of the operational amplifier U2 is connected to the first end of the capacitor C1, and the -IN port of the operational amplifier U2 is connected to the second end of the capacitor C1.

[0010] As preferred, the Butterworth filter comprises a filter chip U3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, and the model of the filter chip U3 is LTC1563-2;

[0011] The first end of the resistor R1 is connected to the OUT port of the operational amplifier U2, the second end of the resistor R1 is connected to the SA port of the filter chip U3, the first end of the resistor R2 is connected to the second end of the resistor R1, the second end of the resistor R2 is connected to the INVA port of the filter chip U3, the first end of the resistor R3 is connected to the second end of the resistor R1, the second end of the resistor R3 is connected to the LPA port of the filter chip U3, the first end of the resistor R4 is connected to the LPB port of the filter chip U3, the second end of the resistor R4 is connected to the first end of the resistor R6, the first end of the resistor R5 is connected to the INVB port of the filter chip U3, the second end of the resistor R5 is connected to the first end of the resistor R6, and the second end of the resistor R6 is connected to the LPA port of the filter chip U3.

[0012] As preferred, the differential operational amplifier circuit comprises an operational amplifier U4, a resistor R7, a resistor R8, a resistor R9, a capacitor C7, a resistor R10, a resistor R11, a resistor R12 and a capacitor C10, and the model of the operational amplifier U4 is THS4531A;

[0013] The first end of the resistor R7 is connected to the LPB port of the filter chip U3, the second end of the resistor R7 is connected to the VIN+ port of the operational amplifier U4, the first end of the resistor R8 is connected to the VIN+ port of the operational amplifier U4, the second end of the resistor R8 is connected to the VOUT- port of the operational amplifier U4, the first end of the resistor R9 is connected to the VOUT- port of the operational amplifier U4, the second end of the resistor R9 is connected to the first end of the capacitor C7, and the second end of the capacitor C7 is connected to the ground;

[0014] The first end of the resistor R10 is connected to the VIN port of the operational amplifier U4, the second end of the resistor R10 is connected to the ground, the first end of the resistor R11 is connected to the VIN port of the operational amplifier U4, the second end of the resistor R11 is connected to the VOUT+ port of the operational amplifier U4, the first end of the resistor R12 is connected to the VOUT+ port of the operational amplifier U4, the second end of the resistor R12 is connected to the first end of the capacitor C10, and the second end of the capacitor C10 is connected to the ground.

[0015] Preferably, the AD conversion circuit comprises an AD chip U5 and a capacitor C11, the model of the AD chip U5 is LTC2246, the AIN- port of the AD chip U5 is connected to the second end of the resistor R12, the AIN+ port of the AD chip U5 is connected to the second end of the resistor R9, the first end of the capacitor C11 is connected to the second end of the resistor R12, and the second end of the capacitor C11 is connected to the second end of the resistor R9.

[0016] Preferably, the 485 communication unit comprises a 485 port, an EMC protection circuit, a 485 isolation transceiver and an STM32 single-chip microcomputer connected in sequence, the STM32 single-chip microcomputer analyzes the instructions on the 485 bus and controls the working of the demodulation device, the STM32 single-chip microcomputer also interacts with the main control unit, the 485 port comprises a port J1, a port J2, a resistor R13, a port J3 and a resistor R16, the A1 port of the port J2 is connected to the A1 port of the port J1, the first end of the resistor R13 is connected to the B1 port of the port J2, the second end of the resistor R13 is connected to the B1 port of the port J1, the A1 port of the port J3 is connected to the A2 port of the port J1, the first end of the resistor R16 is connected to the B1 port of the port J3, and the second end of the resistor R16 is connected to the B2 port of the port J1.

[0017] Preferably, the EMC protection circuit comprises a resistor R14, a resistor R15, a gas discharge tube GDT1, a diode D1, a diode D2, a diode TVS1, an inductor L1, a resistor R17, a resistor R18, a gas discharge tube GDT2, a diode D3, a diode D4, a diode TVS2 and an inductor L2.

[0018] The first end of the resistor R14 is connected to the A1 port of the port J1, the second end of the resistor R14 is connected to the first input end of the inductor L1, the first end of the resistor R15 is connected to the B1 port of the port J1, the second end of the resistor R15 is connected to the second input end of the inductor L1, the first end of the gas discharge tube GDT1 is connected to the first end of the resistor R14, the second end of the gas discharge tube GDT1 is connected to the first end of the resistor R15, the second end of the diode TVS1 is connected to the second end of the resistor R15, the positive electrode of the diode D1 is connected to the first end of the diode TVS1, the negative electrode of the diode D1 is connected to the second end of the resistor R14, the positive electrode of the diode D2 is connected to the second end of the resistor R14, and the negative electrode of the diode D2 is connected to the first end of the diode TVS1.

[0019] The first terminal of resistor R17 is connected to port A2 of port J1, and the second terminal of resistor R17 is connected to the first input terminal of inductor L2. The first terminal of resistor R18 is connected to port B2 of port J1, and the second terminal of resistor R18 is connected to the second input terminal of inductor L2. The first terminal of gas discharge tube GDT2 is connected to the first terminal of resistor R17, and the second terminal of gas discharge tube GDT2 is connected to the first terminal of resistor R18. The first terminal of diode TVS2 is connected to the second terminal of resistor R17. The anode of diode D3 is connected to the second terminal of diode TVS2, and the cathode of diode D3 is connected to the second terminal of resistor R18. The anode of diode D4 is connected to the second terminal of resistor R18, and the cathode of diode D4 is connected to the second terminal of diode TVS2.

[0020] Preferably, the 485 isolated transceiver includes transceiver chip U6 and transceiver chip U7, both of which are model TD301M485.

[0021] The B port of transceiver chip U6 is connected to the first output terminal of inductor L1, the A port of transceiver chip U6 is connected to the second output terminal of inductor L1, the B port of transceiver chip U7 is connected to the first output terminal of inductor L2, and the A port of transceiver chip U7 is connected to the second output terminal of inductor L2.

[0022] Compared with the prior art, the beneficial effects of this utility model are:

[0023] This utility model adopts a chip-level data acquisition design to improve the scanning speed of the demodulator. Through the 485 communication unit, it is easy to integrate with the field system. It adopts a heterogeneous system of main control unit and FPGA unit to enhance edge computing capabilities. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall structure of the utility model;

[0025] Figure 2 This is a structural schematic diagram of the optical path module in the utility model.

[0026] Figure 3 This is a schematic diagram of the electrical signal module in the utility model.

[0027] Figure 4 This is a schematic diagram of the PLC unit in the utility model;

[0028] Figure 5 This is a schematic diagram of the photoelectric conversion unit in the utility model;

[0029] Figure 6 This is a schematic diagram of the structure of the 485 communication unit in the utility model;

[0030] Figure 7 This is a circuit diagram of the logarithmic amplifier circuit in the utility model.

[0031] Figure 8 The circuit diagram of the Butterworth filter in the utility model is shown.

[0032] Figure 9 The circuit diagram is for a differential operational amplifier circuit of a utility model.

[0033] Figure 10 This is a circuit diagram of the AD conversion circuit in the utility model;

[0034] Figure 11 This is a circuit diagram of the 485 port and EMC protection circuit in the utility model.

[0035] Figure 12 This is a circuit diagram of the 485 isolated transceiver in the utility model.

[0036] In the picture:

[0037] 1. Optical path module; 10. Tunable laser unit; 11. PLC unit; 110. Beam splitter; 111. Coupler; 12. FBG sensor;

[0038] 2. Electrical signal module; 20. Main control unit; 21. Optoelectronic conversion unit; 210. Photodiode; 211. Logarithmic amplifier circuit; 212. Butterworth filter; 213. Differential operational amplifier circuit; 214. AD conversion circuit; 215. FPGA unit; 22. DC / DC unit; 23. 485 communication unit; 230. 485 port; 231. EMC protection circuit; 232. 485 isolation transceiver; 233. STM32 microcontroller; 24. Ethernet communication unit. Detailed Implementation

[0039] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0040] Please see Figures 1-12 The present invention provides the following technical solution:

[0041] A multi-channel high-speed fiber Bragg grating demodulation device includes an optical path module 1 and an electrical signal module 2. The optical path module 1 includes a tunable laser unit 10, a PLC unit 11, and several FBG sensors 12. It prioritizes the use of domestically produced laser light sources to reduce supply risks and costs. The PLC unit 11 includes a beam splitter 110 and several couplers 111. The electrical signal module 2 includes a main control unit 20, a photoelectric conversion unit 21, a DC / DC unit 22, a 485 communication unit 23, and an Ethernet communication unit 24. The photoelectric conversion unit 21, DC / DC unit 22, 485 communication unit 23, and Ethernet communication unit 24 are all electrically connected to the main control unit 20. The photoelectric conversion unit 21 includes several photodiodes 210, several logarithmic amplifier circuits 211, several Butterworth filters 212, several differential operational amplifier circuits 213, several AD conversion circuits 214, and an FPGA unit 215. The photodiodes 210 and logarithmic amplifier circuits 211... The Butterworth filter 212, differential operational amplifier circuit 213, AD conversion circuit 214, and FPGA unit 215 are electrically connected in sequence. The optical signal emitted by the tunable laser unit 10 passes through the beam splitter 110 and the multiplexer 111, and then enters the FBG sensor 12. After being reflected by the grating, the light passes through the coupler 111 and is connected to the photodiode 210. After photoelectric conversion, AD conversion, and peak finding algorithm processing, the light wavelength is demodulated. The beam splitter 110 is commonly a 1×16 beam splitter, the coupler 111 is commonly a 2×1 coupler, and the photodiode 210 is commonly an InGaAs photodiode. The photodiode 210 converts the optical signal into an electrical signal. The coupler 111, FBG sensor 12, photodiode 210, logarithmic amplifier circuit 211, Butterworth filter 212, differential operational amplifier circuit 213, and AD conversion circuit 214 correspond one-to-one. The FPGA unit 215 and the main control unit 20 can be Xilinx SOC. The Zynq-7020 features a dual-core CoreTX-A9 processor with a clock speed of 766MHz and 85K logic resources. The FPGA unit 215 is mainly responsible for laser diode data acquisition and wavelength demodulation algorithm implementation. The main control unit 20 is mainly responsible for wavelength data storage, MQTT data transmission, and 485 field control system interface.

[0042] In this embodiment, the DC / DC unit 22 is used to power the tunable laser unit 10 and the main control unit 20. The tunable laser unit 10 and the main control unit 20 are connected via a serial port. The data transmitted via the serial port includes the starting wavelength, trigger interval and number of sampling points. The tunable laser unit 10 also sends a trigger signal to the main control unit 20.

[0043] Specifically, the logarithmic amplifier circuit 211 includes a potentiometer chip U1, a capacitor C1, and an operational amplifier U2. The potentiometer chip U1 is model AD5160, and the operational amplifier U2 is model ADA4817-1.

[0044] The first terminal of capacitor C1 is connected to the W port of potentiometer chip U1, and the second terminal of capacitor C1 is connected to the A port of potentiometer chip U1. The output terminal of photodiode 210 is connected to the second terminal of capacitor C1. The FB port of operational amplifier U2 is connected to the first terminal of capacitor C1, and the -IN port of operational amplifier U2 is connected to the second terminal of capacitor C1. Photodiode 210 is connected to the negative input terminal of operational amplifier U2, and negative feedback is introduced through potentiometer chip U1 to convert the current signal output by photodiode 210 into a voltage signal. Potentiometer chip U1 plays the role of dynamically adjusting the gain.

[0045] Specifically, the Butterworth filter 212 includes filter chip U3, resistors R1, R2, R3, R4, R5 and R6, and the filter chip U3 is model LTC1563-2.

[0046] The first terminal of resistor R1 is connected to the OUT port of operational amplifier U2, and the second terminal of resistor R1 is connected to the SA port of filter chip U3. The first terminal of resistor R2 is connected to the second terminal of resistor R1, and the second terminal of resistor R2 is connected to the INVA port of filter chip U3. The first terminal of resistor R3 is connected to the second terminal of resistor R1, and the second terminal of resistor R3 is connected to the LPA port of filter chip U3. The first terminal of resistor R4 is connected to the LPB port of filter chip U3, and the second terminal of resistor R4 is connected to the first terminal of resistor R6. The first terminal of resistor R5 is connected to the INVB port of filter chip U3, and the second terminal of resistor R5 is connected to the first terminal of resistor R6, and the second terminal of resistor R6 is connected to the LPA port of filter chip U3. The voltage signal after passing through operational amplifier U2 is fed into a fourth-order Butterworth filter composed of filter chip U3 to filter out high-frequency signals above 85kHz.

[0047] Furthermore, the differential operational amplifier circuit 213 includes operational amplifier U4, resistors R7, R8, R9, capacitor C7, R10, R11, R12 and capacitor C10, and the operational amplifier U4 is model THS4531A.

[0048] The first end of resistor R7 is connected to the LPB port of filter chip U3, the second end of resistor R7 is connected to the VIN+ port of operational amplifier U4, the first end of resistor R8 is connected to the VIN+ port of operational amplifier U4, the second end of resistor R8 is connected to the VOUT- port of operational amplifier U4, the first end of resistor R9 is connected to the VOUT- port of operational amplifier U4, the second end of resistor R9 is connected to the first end of capacitor C7, and the second end of capacitor C7 is grounded.

[0049] The first terminal of resistor R10 is connected to the VIN- port of operational amplifier U4, and the second terminal of resistor R10 is grounded. The first terminal of resistor R11 is connected to the VIN- port of operational amplifier U4, and the second terminal of resistor R11 is connected to the VOUT+ port of operational amplifier U4. The first terminal of resistor R12 is connected to the VOUT+ port of operational amplifier U4, and the second terminal of resistor R12 is connected to the first terminal of capacitor C10, and the second terminal of capacitor C10 is grounded. The single-ended signal from filter chip U3 is converted into a differential signal by operational amplifier U4.

[0050] In addition, the AD conversion circuit 214 includes an AD chip U5 and a capacitor C11. The AD chip U5 is an LTC2246. The AIN- port of the AD chip U5 is connected to the second end of the resistor R12, and the AIN+ port of the AD chip U5 is connected to the second end of the resistor R9. The first end of the capacitor C11 is connected to the second end of the resistor R12, and the second end of the capacitor C11 is connected to the second end of the resistor R9. The differential signal is input into the AD chip U5 with a 25MHz high-speed parallel port, and the converted digital signal is sent to the FPGA unit 215 through the 14-bit parallel port.

[0051] It is worth noting that the 485 communication unit 23 includes a 485 port 230, an EMC protection circuit 231, a 485 isolation transceiver 232, and an STM32 microcontroller 233, which are electrically connected in sequence. The STM32 microcontroller 233 parses instructions on the 485 bus, controls the demodulation device, and also interacts with the main control unit 20. The 485 port 230 includes port J1, port J2, resistor R13, port J3, and resistor R14. R16, port A1 of port J2 is connected to port A1 of port J1, the first end of resistor R13 is connected to port B1 of port J2, the second end of resistor R13 is connected to port B1 of port J1, port A1 of port J3 is connected to port A2 of port J1, the first end of resistor R16 is connected to port B1 of port J3, and the second end of resistor R16 is connected to port B2 of port J1. Port J1 is used to connect to an external 485 bus, and ports J2 and J3 are used for redundancy backup or expansion of multi-channel communication.

[0052] It is worth noting that the EMC protection circuit 231 includes resistors R14 and R15, gas discharge tube GDT1, diodes D1, D2, TVS1, inductor L1, resistors R17 and R18, gas discharge tube GDT2, diodes D3 and D4, TVS2, and inductor L2. Gas discharge tubes GDT1 and GDT2 conduct and discharge under high voltage to protect the downstream circuit. Diodes TVS1 and TVS2 provide overvoltage protection. Inductors L1 and L2 filter out high-frequency noise and improve signal quality. Diodes D1, D2, D3, and D4 prevent reverse voltage from damaging the circuit.

[0053] The first terminal of resistor R14 is connected to port A1 of port J1, and the second terminal of resistor R14 is connected to the first input terminal of inductor L1. The first terminal of resistor R15 is connected to port B1 of port J1, and the second terminal of resistor R15 is connected to the second input terminal of inductor L1. The first terminal of gas discharge tube GDT1 is connected to the first terminal of resistor R14, and the second terminal of gas discharge tube GDT1 is connected to the first terminal of resistor R15. The second terminal of diode TVS1 is connected to the second terminal of resistor R15. The anode of diode D1 is connected to the first terminal of diode TVS1, and the cathode of diode D1 is connected to the second terminal of resistor R14. The anode of diode D2 is connected to the second terminal of resistor R14, and the cathode of diode D2 is connected to the first terminal of diode TVS1.

[0054] The first terminal of resistor R17 is connected to port A2 of port J1, and the second terminal of resistor R17 is connected to the first input terminal of inductor L2. The first terminal of resistor R18 is connected to port B2 of port J1, and the second terminal of resistor R18 is connected to the second input terminal of inductor L2. The first terminal of gas discharge tube GDT2 is connected to the first terminal of resistor R17, and the second terminal of gas discharge tube GDT2 is connected to the first terminal of resistor R18. The first terminal of diode TVS2 is connected to the second terminal of resistor R17. The anode of diode D3 is connected to the second terminal of diode TVS2, and the cathode of diode D3 is connected to the second terminal of resistor R18. The anode of diode D4 is connected to the second terminal of resistor R18, and the cathode of diode D4 is connected to the second terminal of diode TVS2.

[0055] In addition, the 485 isolation transceiver 232 includes transceiver chip U6 and transceiver chip U7. Both transceiver chip U6 and transceiver chip U7 are model TD301M485, which serve as electrical isolation and level conversion.

[0056] The B port of transceiver chip U6 is connected to the first output terminal of inductor L1, the A port of transceiver chip U6 is connected to the second output terminal of inductor L1, the B port of transceiver chip U7 is connected to the first output terminal of inductor L2, and the A port of transceiver chip U7 is connected to the second output terminal of inductor L2.

[0057] In use, the optical signal emitted by the tunable laser unit 10 passes through the beam splitter 110 and the multiplexer 111, and then enters the FBG sensor 12. After being reflected by the grating, the light passes through the coupler 111 and enters the photodiode 210. After photoelectric conversion by the photodiode 210, the logarithmic amplifier circuit 211, the Butterworth filter 212 and the differential operational amplifier circuit 213, the AD conversion by the AD conversion circuit 214, and the peak finding algorithm processing by the FPGA unit 215, the optical wavelength is demodulated.

[0058] The main control unit 20 mainly realizes wavelength data storage, MQTT data transmission, and 485 field control system docking. The main control unit 20 controls the scanning parameters of the tunable laser unit 10 through the serial port and receives the trigger signal sent by the tunable laser unit 10 to ensure that data acquisition and laser scanning are synchronized. The main control unit 20 receives wavelength data from the FPGA unit 215, performs edge computing, docks with the industrial field system through the 485 communication unit 23, supports the MODBUS protocol, realizes command parsing and data uploading, and also transmits data to the cloud or host computer through the Ethernet communication unit 24 to support remote monitoring.

[0059] The EMC protection circuit 231 in the 485 communication unit 23 provides lightning protection, surge protection, overvoltage protection, filtering, and polarity protection. The 485 isolation transceiver 232 provides electrical isolation and level conversion. The STM32 microcontroller 233 is used for communication coordination and data interaction.

[0060] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A multi-channel high-speed fiber Bragg grating demodulation device, characterized in that: Including optical path module (1) and electrical signal module (2), the optical path module (1) includes tunable laser unit (10), PLC unit (11) and several FBG sensors (12), the PLC unit (11) includes optical splitter (110) and several couplers (111), the electrical signal module (2) includes master unit (20), photoelectric conversion unit (21), DC / DC unit (22), 485 communication unit (23) and Ethernet communication unit (24), the photoelectric conversion unit (21), the DC / DC unit (22), the 485 communication unit (23) and the Ethernet communication unit (24) are electrically connected with the master unit (20), the photoelectric conversion unit (21) includes several photodiodes (210), several logarithmic amplification circuits (211), several Butterworth filters (212), several differential operational amplifier circuits (213), several AD conversion circuits (214) and FPGA units (215), the photodiodes (210), the logarithmic amplification circuits (211), the Butterworth filters (212), the differential operational amplifier circuits (213), the AD conversion circuits (214) and the FPGA units (215) are electrically connected in sequence, the tunable laser unit (10) emits optical signals, which pass through the optical splitter (110) and multiple couplers (111), then the optical signals enter the FBG sensor (12), after the light is reflected by the grating, the light is accessed to the photodiode (210) through the coupler (111), and after photoelectric conversion, AD conversion and peak searching algorithm processing, the optical wavelength is demodulated.

2. The multi-channel high-speed fiber grating demodulation device according to claim 1, characterized in that: The DC / DC unit (22) is used for powering the tunable laser unit (10) and the master unit (20), and the tunable laser unit (10) and the master unit (20) are connected through a serial port, and the tunable laser unit (10) also sends a trigger signal to the master unit (20).

3. The multi-channel high-speed fiber grating demodulation device according to claim 1, characterized in that: The logarithmic amplification circuit (211) includes a potentiometer chip U1, a capacitor C1 and an operational amplifier U2, the model of the potentiometer chip U1 is AD5160, and the model of the operational amplifier U2 is ADA4817-1; The first end of the capacitor C1 is connected to the W port of the potentiometer chip U1, the second end of the capacitor C1 is connected to the A port of the potentiometer chip U1, the output end of the photodiode (210) is connected to the second end of the capacitor C1, the FB port of the operational amplifier U2 is connected to the first end of the capacitor C1, and the-IN port of the operational amplifier U2 is connected to the second end of the capacitor C1.

4. The multi-channel high-speed fiber grating demodulation device according to claim 3, characterized in that: The Butterworth filter (212) includes a filter chip U3, resistors R1, R2, R3, R4, R5 and R6, and the model of the filter chip U3 is LTC1563-2; The first end of the resistor R1 is connected to the OUT port of the operational amplifier U2, the second end of the resistor R1 is connected to the SA port of the filter chip U3, the first end of the resistor R2 is connected to the second end of the resistor R1, the second end of the resistor R2 is connected to the INVA port of the filter chip U3, the first end of the resistor R3 is connected to the second end of the resistor R1, the second end of the resistor R3 is connected to the LPA port of the filter chip U3, the first end of the resistor R4 is connected to the LPB port of the filter chip U3, the second end of the resistor R4 is connected to the first end of the resistor R6, the first end of the resistor R5 is connected to the INVB port of the filter chip U3, the second end of the resistor R5 is connected to the first end of the resistor R6, and the second end of the resistor R6 is connected to the LPA port of the filter chip U3.

5. The multi-channel high-speed fiber grating demodulation device according to claim 4, characterized in that: The differential operational amplifier circuit (213) comprises an operational amplifier U4, a resistor R7, a resistor R8, a resistor R9, a capacitor C7, a resistor R10, a resistor R11, a resistor R12 and a capacitor C10, and the model of the operational amplifier U4 is THS4531A. The first end of the resistor R7 is connected to the LPB port of the filter chip U3, the second end of the resistor R7 is connected to the VIN+ port of the operational amplifier U4, the first end of the resistor R8 is connected to the VIN+ port of the operational amplifier U4, the second end of the resistor R8 is connected to the VOUT- port of the operational amplifier U4, the first end of the resistor R9 is connected to the VOUT- port of the operational amplifier U4, the second end of the resistor R9 is connected to the first end of the capacitor C7, and the second end of the capacitor C7 is connected to the ground. The first end of the resistor R10 is connected to the VIN- port of the operational amplifier U4, the second end of the resistor R10 is connected to the ground, the first end of the resistor R11 is connected to the VIN- port of the operational amplifier U4, the second end of the resistor R11 is connected to the VOUT+ port of the operational amplifier U4, the first end of the resistor R12 is connected to the VOUT+ port of the operational amplifier U4, the second end of the resistor R12 is connected to the first end of the capacitor C10, and the second end of the capacitor C10 is connected to the ground.

6. The multi-channel high-speed fiber grating demodulation device according to claim 1, characterized in that: The AD conversion circuit (214) comprises an AD chip U5 and a capacitor C11, the model of the AD chip U5 is LTC2246, the AIN- port of the AD chip U5 is connected to the second end of the resistor R12, the AIN+ port of the AD chip U5 is connected to the second end of the resistor R9, the first end of the capacitor C11 is connected to the second end of the resistor R12, and the second end of the capacitor C11 is connected to the second end of the resistor R9.

7. The multi-channel high-speed fiber grating demodulation device according to claim 1, characterized in that: The 485 communication unit (23) comprises a 485 port (230), an EMC protection circuit (231), a 485 isolation transceiver (232) and an STM32 single-chip microcomputer (233) connected in sequence, the STM32 single-chip microcomputer (233) analyzes instructions on the 485 bus, controls the work of the demodulation device, and also interacts with the main control unit (20), the 485 port (230) comprises a port J1, a port J2, a resistor R13, a port J3 and a resistor R16, the A1 port of the port J2 is connected to the A1 port of the port J1, the first end of the resistor R13 is connected to the B1 port of the port J2, the second end of the resistor R13 is connected to the B1 port of the port J1, the A1 port of the port J3 is connected to the A2 port of the port J1, the first end of the resistor R16 is connected to the B1 port of the port J3, and the second end of the resistor R16 is connected to the B2 port of the port J1.

8. The multi-channel high-speed fiber grating demodulation device according to claim 7, characterized in that: The EMC protection circuit (231) comprises a resistor R14, a resistor R15, a gas discharge tube GDT1, a diode D1, a diode D2, a diode TVS1, an inductor L1, a resistor R17, a resistor R18, a gas discharge tube GDT2, a diode D3, a diode D4, a diode TVS2 and an inductor L2; the first end of the resistor R14 is connected to the A1 port of the port J1, the second end of the resistor R14 is connected to the first input end of the inductor L1, the first end of the resistor R15 is connected to the B1 port of the port J1, the second end of the resistor R15 is connected to the second input end of the inductor L1, the first end of the gas discharge tube GDT1 is connected to the first end of the resistor R14, the second end of the gas discharge tube GDT1 is connected to the first end of the resistor R15, the second end of the diode TVS1 is connected to the second end of the resistor R15, the positive electrode of the diode D1 is connected to the first end of the diode TVS1, the negative electrode of the diode D1 is connected to the second end of the resistor R14, the positive electrode of the diode D2 is connected to the second end of the resistor R14, and the negative electrode of the diode D2 is connected to the first end of the diode TVS1; the first end of the resistor R17 is connected to the A2 port of the port J1, the second end of the resistor R17 is connected to the first input end of the inductor L2, the first end of the resistor R18 is connected to the B2 port of the port J1, the second end of the resistor R18 is connected to the second input end of the inductor L2, the first end of the gas discharge tube GDT2 is connected to the first end of the resistor R17, the second end of the gas discharge tube GDT2 is connected to the first end of the resistor R18, the first end of the diode TVS2 is connected to the second end of the resistor R17, the positive electrode of the diode D3 is connected to the second end of the diode TVS2, the negative electrode of the diode D3 is connected to the second end of the resistor R18, the positive electrode of the diode D4 is connected to the second end of the resistor R18, and the negative electrode of the diode D4 is connected to the second end of the diode TVS2.

9. The multi-channel high-speed fiber grating demodulation apparatus according to claim 8, characterized in that: The 485 isolation transceiver (232) comprises a transceiver chip U6 and a transceiver chip U7, and the models of the transceiver chip U6 and the transceiver chip U7 are both TD301M485; the B port of the transceiver chip U6 is connected to the first output end of the inductor L1, the A port of the transceiver chip U6 is connected to the second output end of the inductor L1, the B port of the transceiver chip U7 is connected to the first output end of the inductor L2, and the A port of the transceiver chip U7 is connected to the second output end of the inductor L2.

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