Pulse width adjusting circuit
By combining RC delay circuits and OR logic circuits, the problem of high cost of existing pulse width adjustment circuits is solved, achieving the effects of simplified circuit structure and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2026-03-10
AI Technical Summary
Existing pulse width modulation circuits require complex logic circuits or MCUs, resulting in excessive costs.
By using a combination of RC delay circuits and OR logic circuits, pulse width adjustment is achieved through resistors, capacitors, and OR logic gates, simplifying the circuit structure and avoiding the use of complex logic circuits and MCUs.
It reduces circuit costs, simplifies circuit structure, and allows for effective adjustment of pulse width.
Smart Images
Figure CN223987085U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a pulse width adjustment circuit. Background Technology
[0002] Pulse width modulation (PWM) circuits are circuits that can change the duration of the high-level signal of a pulse signal. They are currently widely used in various fields such as motor control, power equipment control, lighting control, power management, and audio processing. However, the inventors have found that existing PWM circuits require complex logic circuits, or even MCUs (Microcontroller Units), which results in excessively high costs. Utility Model Content
[0003] The purpose of this application is to address at least one of the aforementioned technical defects, particularly the technical defect of excessively high costs in the prior art.
[0004] In some embodiments, this application provides a pulse width adjustment circuit, including:
[0005] An RC delay circuit includes a capacitor module and a resistor module; the first terminal of the resistor module is used as the signal input terminal of the pulse width adjustment circuit, the second terminal of the resistor module is connected to the first terminal of the capacitor module, the third terminal of the resistor module is connected to the second terminal of the capacitor module, and the second terminal of the capacitor module is used for grounding.
[0006] The OR logic circuit has a first input terminal connected to the first terminal of the resistor module, a second input terminal connected to the first terminal of the capacitor module, and a signal output terminal used as the signal output terminal of the pulse width adjustment circuit.
[0007] In one embodiment, the resistor module includes:
[0008] A first resistor unit, the first end of which is used as the signal input terminal of the pulse width adjustment circuit, and the second end of which is connected to the second end of the capacitor module.
[0009] The second resistor unit has its first end connected to the first end of the first resistor unit, and its second end connected to the first end of the capacitor module and the second input terminal of the OR logic circuit.
[0010] In one embodiment, the first resistor unit includes a first resistor, and the second resistor unit includes a second resistor and a diode;
[0011] The first end of the first resistor is used as the signal input terminal of the pulse width adjustment circuit, and the second end of the first resistor is connected to the second end of the capacitor module.
[0012] The first end of the second resistor is connected to the first end of the first resistor and the positive terminal of the diode, and the second end of the second resistor is connected to the negative terminal of the diode, the first end of the capacitor module and the second input terminal of the OR logic circuit.
[0013] In one embodiment, the first resistor is an adjustable resistor, and / or the second resistor is an adjustable resistor.
[0014] In one embodiment, the capacitor module includes a first capacitor;
[0015] The first terminal of the first capacitor is connected to the second terminal of the resistor module and the second input terminal of the OR logic circuit, respectively; the second terminal of the first capacitor is connected to the third terminal of the resistor module and is used for grounding.
[0016] In one embodiment, the first capacitor is an adjustable capacitor.
[0017] In one embodiment, the pulse width adjustment circuit further includes a voltage regulation and filtering circuit;
[0018] The first terminal of the voltage regulator and filter circuit is connected to the power supply terminal of the OR logic circuit, and the second terminal of the voltage regulator and filter circuit is used for grounding.
[0019] In one embodiment, the voltage regulator filter circuit includes a second capacitor;
[0020] The first terminal of the second capacitor is connected to the power supply terminal of the OR logic circuit, and the second terminal of the second capacitor is used for grounding.
[0021] In one embodiment, the OR logic circuit includes an OR logic gate;
[0022] The first input terminal of the OR logic gate is connected to the first terminal of the resistor module, the second input terminal of the OR logic gate is connected to the first terminal of the capacitor module, the signal output terminal of the OR logic gate is used as the signal output terminal of the pulse width adjustment circuit, the power supply terminal of the OR logic gate is used to connect to the power supply, and the ground terminal of the OR logic gate is used to ground.
[0023] In one embodiment, the OR logic gate is a device of model SN74LVC1G32.
[0024] In the pulse width adjustment circuit provided in some embodiments of this application, when the input pulse signal is a high-level signal, the pulse signal is input to the OR logic gate through the first input terminal of the OR logic circuit, causing the OR logic gate to output a high-level signal. Furthermore, the high-level signal can also charge the capacitor module in the RC delay circuit. When the input pulse signal is a low-level signal, the charged capacitor module can output a high-level signal to the OR logic circuit for a period of time, allowing the OR logic circuit to continuously output a high-level signal for a period of time, thereby increasing the pulse width of the pulse signal. Thus, the pulse width can be adjusted using an RC delay circuit and an OR logic circuit, eliminating the need for complex logic circuits and an MCU, thereby simplifying the circuit structure of the pulse width adjustment circuit and reducing circuit costs. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic block diagram of the pulse width adjustment circuit in some embodiments;
[0027] Figure 2 This is a circuit diagram of the pulse width adjustment circuit in some embodiments;
[0028] Figure 3 This is a schematic diagram comparing the pulse width before and after adjustment in some embodiments. Detailed Implementation
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0031] In some embodiments, this application provides a pulse width adjustment circuit capable of adjusting the pulse width of a pulse signal. For example... Figure 1As shown, the pulse width adjustment circuit provided in this application includes an RC delay circuit 10 and an OR logic circuit 20. The RC delay circuit 10 may include a resistor module 110 and a capacitor module 120. The RC delay circuit 10 refers to a circuit that utilizes resistors and capacitors and has a delay function, while the OR logic circuit 20 refers to a circuit capable of performing OR logic operations.
[0032] It should be noted that the RC delay circuit 10 may include more components besides resistors and capacitors. Furthermore, the number of resistors, capacitors, and the connections between the various electronic components in the RC delay circuit 10 can be adjusted based on practical factors such as charging time requirements, discharging time requirements, voltage regulation requirements, and the application scenario of the pulse width adjustment circuit. In other words, the specific circuit structure of the RC delay circuit 10 can be determined according to the actual situation.
[0033] The OR logic circuit 20 can be implemented in any way, and this application does not impose any specific restrictions on it. For example, the OR logic circuit 20 can be implemented using an OR gate. Or, the OR logic circuit 20 can be implemented using electronic components such as transistors and resistors.
[0034] Please see Figure 1 The first terminal of resistor module 110 is connected to the first input terminal of OR logic circuit 20 and serves as the signal input terminal of pulse width adjustment circuit, capable of receiving pulse signals whose pulse width is to be adjusted. The second terminal of resistor module 110 is connected to the second input terminal of OR logic circuit 20 and the first terminal of capacitor module 120. The second terminal of capacitor module 120 and the third terminal of resistor module 110 are both grounded, and the signal output terminal of OR logic circuit 20 serves as the signal output terminal of pulse width adjustment circuit.
[0035] When a high-level signal is received at the first input terminal of the OR logic circuit 20, the signal output terminal of the OR logic circuit 20 outputs a high-level signal. When a high-level signal is received at the second input terminal of the OR logic circuit 20, the signal output terminal of the OR logic circuit 20 outputs a high-level signal. When a low-level signal is received at both the first and second input terminals of the OR logic circuit 20, the signal output terminal of the OR logic circuit 20 outputs a low-level signal.
[0036] Assume the pulse signal input to the pulse width adjustment circuit is a first pulse signal, and the pulse signal output by the pulse width adjustment circuit is a second pulse signal. If the first pulse signal is at a high level, either the first input terminal of the logic circuit 20 can receive a high-level signal, or the signal output terminal of the logic circuit 20 outputs a high-level second pulse signal. Furthermore, when the first pulse signal is at a high level, it can charge the capacitor module 120 via the resistor module 110, thereby raising the first terminal voltage of the capacitor module 120.
[0037] After the first pulse signal transitions from high to low, the first input terminal of the OR logic circuit 20 receives a low-level signal, and the capacitor module 120 discharges. Since the second input terminal of the OR logic circuit 20 is connected to the first terminal of the capacitor module 120, during the discharge process of the capacitor module 120, if the voltage at the first terminal of the capacitor module 120 is greater than or equal to the high-level judgment threshold (e.g., 0.6VCC), it can be determined that the second input terminal of the OR logic circuit 20 receives a high-level signal. Therefore, the OR logic circuit 20 can still output a high-level second pulse signal for a period of time.
[0038] When the first pulse signal is low, if the voltage at the first terminal of the capacitor module 120 is lower than the high-level judgment threshold, then the first input terminal of the OR logic circuit 20 receives a low-level signal, or the second input terminal of the OR logic circuit 20 receives a low-level signal, and therefore the OR logic circuit 20 outputs a low-level second pulse signal.
[0039] Therefore, the pulse width of the second pulse signal is (t1 + t2), where t1 is the pulse width of the first pulse signal, and t2 is the time required for the voltage at the first terminal of capacitor module 120 to drop to the high-level judgment threshold. It can be understood that the specific duration of t2 is related to the time constant of the RC delay circuit 10. Adjusting the time constant of the RC delay circuit 10 can change the duration of t2, thereby adjusting the pulse width of the second pulse signal.
[0040] This application utilizes an RC delay circuit 10 and an OR logic circuit 20 to adjust the pulse width without the need for complex logic circuits or an MCU, thereby simplifying the circuit structure of the pulse width adjustment circuit and reducing circuit costs.
[0041] In some embodiments, the resistor module 110 may include a first resistor unit and a second resistor unit. It is understood that the first resistor unit may include one or more resistors. When the first resistor unit includes multiple resistors, the specific connection relationship of each resistor can be determined according to the actual situation, and this application does not impose any limitations on this. Similarly, the second resistor unit may include one or more resistors, and the number of resistors in the first resistor unit and the number of resistors in the second resistor unit may be the same or different.
[0042] The first end of the first resistor unit is the first end of the resistor module 110, used as the signal input terminal of the pulse width adjustment circuit to receive the first pulse signal. The second end of the first resistor unit is connected to the second end of the capacitor module 120 and is used for grounding. The first end of the second resistor unit is connected to the first end of the first resistor unit, and the second end of the second resistor unit is connected to the first end of the capacitor module 120 and the second input terminal of the logic circuit 20.
[0043] When the first pulse signal is high, the second resistor unit and the capacitor unit are connected in series to form a capacitor charging circuit, and the first resistor unit is connected in parallel with the capacitor charging circuit. When the first pulse signal is low, the capacitor module, the first resistor unit, and the second resistor unit form a discharge circuit, allowing the capacitor module to discharge through the first resistor unit and the second resistor unit.
[0044] Therefore, in this embodiment, the charging and discharging circuits of the capacitor module are different, allowing for differences in the charging and discharging time constants of the circuit. This improves the practicality of the pulse adjustment circuit.
[0045] In some embodiments, such as Figure 2 As shown, the first resistor unit includes a first resistor R1, and the second resistor unit includes a second resistor R2 and a diode D1. The first terminal of the first resistor R1 serves as the signal input terminal of the pulse width adjustment circuit, and the second terminal of the first resistor R1 is connected to the second terminal of the capacitor module 120. The first terminal of the second resistor R2 is connected to both the first terminal of the first resistor R1 and the anode of the diode D1, and the second terminal of the second resistor R2 is connected to the cathode of the diode D1, the first terminal of the capacitor module 120, and / or the second input terminal of the logic circuit 20.
[0046] When the first pulse signal is high, diode D1 is turned on, and the first pulse signal can charge capacitor module 120 through the path of diode D1. When the first pulse signal is low, diode D1 is turned off, and capacitor module 120 discharges sequentially through second resistor R2 and first capacitor C1. In this way, the charging time of capacitor module 120 can be shortened, allowing capacitor module 120 to charge quickly when the pulse width of the first pulse signal is short, ensuring that the pulse adjustment circuit can perform pulse adjustment function when faced with first pulse signals with different pulse widths.
[0047] It is understood that the resistance values of the first resistor R1 and the second resistor R2 can be determined according to the actual situation, and the diode D1 can be selected according to the actual situation. This application does not impose specific restrictions on this. In some examples, the resistance value of the first resistor R1 can be 47 kΩ, the resistance value of the second resistor R2 can be 100 Ω, and the diode D1 is a Schottky diode D1.
[0048] Furthermore, in some embodiments, the first resistor R1 is an adjustable resistor, and / or the second resistor R2 is an adjustable resistor. Thus, by adjusting the resistance value of the first resistor R1 and / or the resistance value of the second resistor R2, the charging time constant and discharging time constant of the RC delay circuit 10 can be adjusted, thereby making the pulse width of the second pulse signal adjustable. This allows for more convenient pulse width adjustment and improves the practicality of the circuit.
[0049] In some embodiments, the capacitor module 120 includes a first capacitor C1. A first terminal of the first capacitor C1 is connected to a second terminal of the resistor module 110 and a second input terminal of the logic circuit 20. A second terminal of the first capacitor C1 is connected to a third terminal of the resistor module 110 and is grounded. This further simplifies the circuit structure of the pulse width adjustment circuit and reduces cost.
[0050] It is understood that the capacitance value of the first capacitor C1 can be determined according to the actual situation, for example, it can be 1 nanofarad, and this application does not impose a specific limitation on it. In one example, the first capacitor C1 is an adjustable capacitor. In this way, by adjusting the capacitance value of the first capacitor C1, the time constant of the RC delay circuit 10 is adjusted, and the pulse width of the second pulse signal can be adjusted, thereby making it easier to adjust the pulse width and improving the practicality of the circuit.
[0051] In some embodiments, the pulse width adjustment circuit may further include a voltage regulator and filter circuit. The first terminal of the voltage regulator and filter circuit is connected to the power supply terminal of the OR logic circuit 20, and the second terminal of the voltage regulator and filter circuit is grounded. The voltage regulator and filter circuit refers to a circuit capable of stabilizing the power supply voltage and reducing power supply voltage fluctuations and ripple. By providing a voltage regulator and filter circuit at the power supply terminal of the OR logic circuit 20, it can be ensured that the power supply terminal of the OR logic circuit 20 receives a more stable power supply, thereby improving the stability of the OR logic circuit 20.
[0052] It is understood that the voltage regulator and filter circuit can be implemented in any way. In some examples, the voltage regulator and filter circuit may include a second capacitor C2, with the first terminal of the second capacitor C2 connected to the power supply terminal of the OR logic circuit 20, and the second terminal of the second capacitor C2 used for grounding. In this way, the filtering characteristics of the capacitor can be used to achieve DC voltage regulation, thereby simplifying the circuit structure of the pulse width adjustment circuit, and further reducing the size and cost of the pulse width adjustment circuit.
[0053] Similar to the first capacitor C1, the capacitance value of the second capacitor C2 can also be determined according to the actual situation, for example, it can be 100 nanofarads. This application does not impose specific restrictions on this.
[0054] In some embodiments, such as Figure 2As shown, the OR logic circuit 20 may include an OR logic gate U1. The OR logic gate U1 has a first input terminal A, a second input terminal B, a signal output terminal Y, a power supply terminal VCC, and a ground terminal AGND. The first input terminal A is connected to the first terminal of the resistor module 110, the second input terminal B is connected to the first terminal of the capacitor module 120, the signal output terminal Y serves as the signal output terminal of the pulse width adjustment circuit, the power supply terminal VCC is connected to the power supply VS1, and the ground terminal AGND is used for grounding. This embodiment implements the OR logic circuit 20 using the OR logic gate U1, which further simplifies the circuit structure of the pulse width adjustment circuit and reduces the circuit size.
[0055] It is understood that the OR logic gate U1 can be implemented using any type of OR gate device. In some examples, the OR logic gate U1 can be a device of type SN74LVC1G32, so that the OR logic circuit 20 can maintain low static power consumption over a wide VCC operating range.
[0056] In some embodiments, such as Figure 2 and Figure 3 As shown, when the circuit structure of the pulse width adjustment circuit is as follows: Figure 2 As shown, with the first resistor R1 having a resistance of 47 kΩ, the second resistor R2 having a resistance of 100 Ω, the first capacitor C1 having a capacitance of 1 nanofarad, and the second capacitor C2 having a capacitance of 100 nanofarad, if the pulse width of the first pulse signal is 10 nanoseconds, then after adjustment by the pulse width adjustment circuit, the second pulse signal output by the circuit can have a pulse width of 65 nanoseconds. Therefore, this application demonstrates that the pulse signal width can be adjusted without using complex logic gates and an MCU.
[0057] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0058] The terms “comprising,” “including,” or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0059] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0060] In this text, “a,” “one,” “the,” “the,” and “its” may also include plural forms unless the context clearly indicates otherwise. Multiple refers to at least two, such as 2, 3, 5, or 8, etc. “And / or” includes any and all combinations of the related listed items.
[0061] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.
[0062] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A pulse width adjustment circuit, characterized by, The pulse width adjusting circuit comprises: an RC delay circuit comprising a resistance module and a capacitance module; a first end of the resistance module is used as a signal input end of the pulse width adjusting circuit; a second end of the resistance module is connected to a first end of the capacitance module; a third end of the resistance module is connected to a second end of the capacitance module; and the second end of the capacitance module is used for grounding; or a logic circuit, a first input end of the or logic circuit is connected to the first end of the resistance module, a second input end of the or logic circuit is connected to the first end of the capacitance module, and a signal output end of the or logic circuit is used as a signal output end of the pulse width adjusting circuit.
2. The pulse width adjustment circuit according to claim 1, characterized by, The resistance module comprises: a first resistance unit, a first end of the first resistance unit is used as a signal input end of the pulse width adjusting circuit, and a second end of the first resistance unit is connected to a second end of the capacitance module; a second resistance unit, a first end of the second resistance unit is connected to a first end of the first resistance unit, and a second end of the second resistance unit is connected to the first end of the capacitance module and a second input end of the or logic circuit respectively.
3. The pulse width adjustment circuit according to claim 2, wherein The first resistance unit comprises a first resistance, and the second resistance unit comprises a second resistance and a diode; a first end of the first resistance is used as a signal input end of the pulse width adjusting circuit, and a second end of the first resistance is connected to a second end of the capacitance module; a first end of the second resistance is connected to the first end of the first resistance and a positive electrode of the diode respectively, and a second end of the second resistance is connected to a negative electrode of the diode, the first end of the capacitance module and the second input end of the or logic circuit respectively.
4. The pulse width adjustment circuit according to claim 3, wherein The first resistance is an adjustable resistance, and / or the second resistance is an adjustable resistance.
5. The pulse width adjusting circuit according to claim 1, wherein The capacitance module comprises a first capacitance; a first end of the first capacitance is connected to the second end of the resistance module and the second input end of the or logic circuit respectively, and a second end of the first capacitance is connected to a third end of the resistance module and used for grounding.
6. The pulse width adjustment circuit of claim 5, wherein The first capacitance is an adjustable capacitance.
7. The pulse width adjusting circuit according to any one of claims 1 to 6, characterized by, The pulse width adjusting circuit further comprises a voltage stabilizing filter circuit; a first end of the voltage stabilizing filter circuit is connected to a power supply end of the or logic circuit, and a second end of the voltage stabilizing filter circuit is used for grounding.
8. The pulse width adjustment circuit of claim 7, wherein, The voltage stabilizing filter circuit comprises a second capacitance; a first end of the second capacitance is connected to the power supply end of the or logic circuit, and a second end of the second capacitance is used for grounding.
9. The pulse width adjusting circuit according to any one of claims 1 to 6, characterized by, The or logic circuit comprises an or logic gate; a first input end of the or logic gate is connected to the first end of the resistance module, a second input end of the or logic gate is connected to the first end of the capacitance module, a signal output end of the or logic gate is used as a signal output end of the pulse width adjusting circuit, a power supply end of the or logic gate is used for connecting a power supply, and a grounding end of the or logic gate is used for grounding.
10. The pulse width adjustment circuit of claim 9, wherein, The or logic gate is a device of SN74LVC1G32 model.