Display panel

Abstract

The utility model discloses a display panel. The display panel comprises pixels, signal lines electrically connected with the pixels and signal bonding pads connected to the signal lines, and each signal bonding pad comprises a first conductive pattern connected to the tail end of the corresponding signal line and a second conductive pattern connected to the tail end of the corresponding signal line. A second conductive pattern including a first layer disposed on the first conductive pattern, a second layer disposed on the first layer, and a third layer disposed on the second layer; and an insulating pattern disposed between the first conductive pattern and the second conductive pattern and defining a groove pattern on an upper surface of the second conductive pattern.

Description

TECHNICAL FIELD

[0001] The utility model relates to a display panel, more particularly to a display panel including a pad area. BACKGROUND

[0002] A display device includes a display area activated according to an electric signal. The display device can sense an input applied from the outside through the display area while displaying various images to provide information to a user.

[0003] A display device includes a display panel and a circuit substrate. The display panel can be connected to a main board through the circuit substrate. A driving chip can be mounted in the display panel. SUMMARY

[0004] The utility model aims at providing a display panel with improved bonding reliability.

[0005] The display panel according to an embodiment of the utility model includes a pixel, a signal line electrically connected to the pixel, and a signal pad connected to the signal line. The signal pad includes a first conductive pattern connected to a terminal portion of the signal line, a second conductive pattern including a first layer disposed on the first conductive pattern, a second layer disposed on the first layer, and a third layer disposed on the second layer, and an insulating pattern disposed between the first conductive pattern and the second conductive pattern and defining a groove pattern on the second conductive pattern.

[0006] The insulating pattern can be disposed inside each of the first conductive pattern and the second conductive pattern in a plan view.

[0007] The insulating pattern can include a lower surface adjacent to the first conductive pattern, an upper surface opposite to the lower surface and spaced apart from the first conductive pattern, and a side surface connecting the upper surface and the lower surface. The second conductive pattern can cover a portion of the first conductive pattern where the insulating pattern is not disposed, the upper surface of the insulating pattern, and the side surface of the insulating pattern.

[0008] The groove pattern can overlap the upper surface of the insulating pattern in a plan view.

[0009] The groove pattern can be defined to expose the second layer through the third layer.

[0010] The second conductive pattern can further include an oxide film disposed on the third layer. The groove pattern can be defined to pass through the oxide film.

[0011] The groove pattern can include at least one trench or at least one crack.

[0012] The second layer can have a thickness that is thicker than each of a thickness of the first layer and a thickness of the third layer.

[0013] The second layer can have a conductivity that is greater than each of a conductivity of the first layer and a conductivity of the third layer.

[0014] The insulating pattern can be formed of a polymer.

[0015] A display device according to an embodiment of the present disclosure includes a display panel including a signal pad, an electronic component electrically connected to the display panel, and an adhesive layer adhering the display panel and the electronic component, the signal pad including a first conductive pattern, a second conductive pattern defining a groove pattern thereon and disposed on the first conductive pattern, and an insulating pattern disposed between the first conductive pattern and the second conductive pattern.

[0016] The second conductive pattern can include a first layer disposed on the first conductive pattern, a second layer disposed on the first layer, and a third layer disposed on the second layer, the groove pattern penetrating the third layer and exposing the second layer.

[0017] The electronic component can include a substrate and a bump electrode disposed on the substrate and protruding in a direction toward the display panel, the bump electrode being in contact with the second layer while filling the groove pattern.

[0018] The second layer exposed through the groove pattern can be covered by the bump electrode and not in contact with the adhesive layer.

[0019] In a plan view, the insulating pattern can be disposed inside each of the first conductive pattern and the second conductive pattern.

[0020] The insulating pattern can include an upper surface spaced apart from the first conductive pattern, and in a plan view, the groove pattern can overlap the upper surface of the insulating pattern.

[0021] The insulating pattern can be formed of a polymer.

[0022] A method of manufacturing a display device according to an embodiment of the present disclosure includes providing a preliminary signal pad including a first conductive pattern connected to a signal line, a second conductive pattern disposed on the first conductive pattern, and an insulating pattern disposed between the first conductive pattern and the second conductive pattern, and forming a groove pattern on the second conductive pattern to provide a signal pad.

[0023] The second conductive pattern can include a first layer disposed on the first conductive pattern, a second layer disposed on the first layer, and a third layer disposed on the second layer, and the groove pattern can be formed by penetrating the third layer with a laser or a piercing needle to expose the second layer.

[0024] The signal pad can be bonded to an electronic component including a bump electrode immediately after the step of providing the signal pad, and the bump electrode can be bonded to be in contact with the second layer exposed through the groove pattern.

[0025] According to the foregoing, the display device according to the present disclosure can increase the contact area of the bump electrode and the pad electrode, thereby improving the initial resistance and the reliability resistance.

[0026] In addition, the manufacturing method of the display device according to the present disclosure can manufacture a display device with improved bonding reliability, and a low-pressure process can reduce physical damage to the display panel or the electronic component that can occur in the bonding process. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0028] Figure 2a and Figure 2b are exploded perspective views of a display device according to an embodiment of the present disclosure, respectively.

[0029] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0030] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 5 is a cross-sectional view of a display panel showing a pixel according to an embodiment of the present disclosure.

[0032] Figure 6 is an enlarged exploded perspective view of a pad area of a display device according to an embodiment of the present disclosure.

[0033] Figure 7a is a simple plan view of a pad area according to an embodiment of the present disclosure.

[0034] Figure 7b and Figure 7c are cross-sectional views of pad areas PA1 and PA2 according to an embodiment of the present disclosure, respectively.

[0035] Figure 8is a cross-sectional view showing a bonding structure of a display device according to an embodiment of the present application.

[0036] Figures 9 to 1 Id are cross-sectional views each briefly showing a step of a manufacturing method of a display device according to an embodiment of the present application.

[0037] Figures 12a to 12d are each a brief plan view of a pad area according to still another embodiment of the present application.

[0038] (Explanation of Reference Numerals)

[0039] DD: display device

[0040] DP: display panel

[0041] CL1: first conductive pattern

[0042] CL2: second conductive pattern

[0043] SP: insulating pattern

[0044] GVP: groove pattern

[0045] DC-BP, PB-BP: bump electrode

[0046] DP-PD: signal pad DETAILED DESCRIPTION

[0047] In the present specification, in the case where a certain constitutional element (or area, layer, part, etc.) is mentioned to be "on", "connected to", or "combined with" another constitutional element, it means that it can be directly disposed / connected / combined on the other constitutional element or a third constitutional element can be disposed therebetween.

[0048] The same reference numerals refer to the same constitutional elements. In addition, in the drawings, the thickness, proportions, and sizes of the constitutional elements are exaggerated for effective explanation of technical contents. "And / or" includes all of one or more combinations of the associated constitutional elements.

[0049] The terms of first, second, etc. can be used to explain various constitutional elements, but the above constitutional elements cannot be limited by the above terms. The above terms are used only for the purpose of distinguishing one constitutional element from the other constitutional elements. For example, a first constitutional element can be named a second constitutional element, and similarly a second constitutional element can also be named a first constitutional element, without departing from the scope of the present application. The singular expression includes the plural expression unless it is clearly different in context.

[0050] Further, the terms "below", "lower", "above", "upper" and the like are used for the purpose of explanation regarding the relative relationship of the constituent elements illustrated in the drawings. The above terms are relative concepts, and are explained based on the directions indicated in the drawings.

[0051] The terms "comprise" or "have" and the like are to be construed as specifying the presence of stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0052] Unless defined differently, all terms used in the present specification (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. Also, the terms defined in a generally used dictionary are to be interpreted as having the same meaning as those in the context of the relevant technology, and are not to be interpreted as having an ideal or excessively formal meaning unless clearly defined herein.

[0053] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a display device DD according to an embodiment of the present application. Figure 2a and Figure 2b are exploded perspective views of a display device DD according to an embodiment of the present application, respectively. Figure 2b is exemplarily illustrated Figure 2a a display device DD in a state in which a bending area BA is bent.

[0055] Referring to Figure 1 , the display device DD is exemplarily illustrated as a mobile phone terminal. The display device DD according to the present application can be applied to large electronic devices such as televisions and monitors, medium and small electronic devices such as tablet computers, car navigation systems, game consoles, smart watches, and the like.

[0056] The display device DD can have a rectangular shape in a planar surface, the rectangular shape having a long side extending in a first direction DR1 and having a short side extending in a second direction DR2 crossing the first direction DR1. However, the display device DD is not limited thereto, and can have various shapes such as a circular shape, a polygonal shape, and the like in a planar surface.

[0057] Hereinafter, a direction substantially perpendicularly crossing the planar surface defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the present specification, "when viewed in a planar surface" can mean a state of being observed in the third direction DR3.

[0058] The display device DD can be rigid or flexible. "Flexible" can mean a characteristic that can be bent, including everything from a completely folded structure to a structure that can be bent at a level of several nanometers. For example, the flexible display device DD can include a curved display device, a rollable display device, and a foldable display device.

[0059] The display device DD can display an image IM through a display surface DD-IS. An icon image is illustrated as an example of the image IM. The display surface DD-IS can be parallel to a surface defined by the first direction DR1 and the second direction DR2.

[0060] The display surface DD-IS can include a display area DD-DA displaying the image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA can be an area in which the image is not displayed. However, it is not limited thereto, and the non-display area DD-NDA can be adjacent to any one side of the display area DD-DA or omitted.

[0061] Referring to Figure 2a and Figure 2b , the display device DD can include a window body WM, a display module DM, and a housing member BC.

[0062] The window body WM can be disposed above the display module DM to transmit the image provided from the display module DM to the outside. Although not illustrated, the window body WM can include a base layer and a functional layer disposed on the base layer. The functional layer can include a protective layer, a fingerprint prevention layer, etc. The base layer of the window body WM can be composed of glass, sapphire, or plastic, etc. The base layer of the window body WM can contain an optically transparent insulating substance. For example, the base layer of the window body WM can include a glass or plastic film, or include a glass substrate and a plastic film combined by an adhesive.

[0063] The window body WM can include a transmission area TA and a non-transmission area NTA. The transmission area TA can overlap the display area DD-DA illustrated in Figure 1 , and have a shape corresponding to the display area DD-DA. The non-transmission area NTA can overlap the non-display area DD-NDA illustrated in Figure 1 , and have a shape corresponding to the non-display area DD-NDA. The non-transmission area NTA can be an area in which the light transmittance is relatively low compared to the transmission area TA. The non-transmission area NTA can be defined by a bezel pattern in a partial area of the base layer of the window body WM, and an area in which the bezel pattern is not disposed can be defined as the transmission area TA. However, it is not limited thereto, and the non-transmission area NTA can also be omitted.

[0064] Although not illustrated, a reflection-prevention layer may be configured between the window WM and the display module DM. The reflection-prevention layer reduces the reflectivity of external light incident from outside the display device DD. The reflection-prevention layer may include color filters. The color filters may have a predetermined arrangement. For example, the color filters may be arranged taking into account the emission colors of pixels included in the display panel DP, as described later. Additionally, the reflection-prevention layer may also include a black matrix adjacent to the color filters.

[0065] According to one embodiment of the present invention, the display module DM may include a display panel DP and an input sensor ISU.

[0066] The display panel (DP) can be any of the following: liquid crystal display panel, electrophoretic display panel, microelectromechanical system display panel, electrowetting display panel, organic light emitting display panel, inorganic light emitting display panel, and quantum dot light emitting display panel. However, it is not specifically limited to these. Hereinafter, the display panel (DP) will be defined as an organic light emitting display panel.

[0067] The input sensor ISU can include any one of capacitive sensors, optical sensors, ultrasonic sensors, and electromagnetic induction sensors. The input sensor ISU can be formed on the display panel DP through a continuous process, or it can be attached to the top of the display panel DP by an adhesive layer after separate manufacturing, and is not limited to any particular embodiment.

[0068] The display device DD may further include a driver chip DC disposed on the display panel DP. The display device DD may also include a circuit board PB disposed on the display panel DP. In this embodiment, the circuit board PB may be a flexible circuit board, but is not limited thereto. For example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and the main circuit board.

[0069] The driver chip DC may include driving elements for driving the pixels of the display panel DP, such as data driving circuitry. Figure 2aThe diagram illustrates a structure where the driver chip DC is mounted on the display panel DP, but the present invention is not limited thereto. For example, the driver chip DC can also be mounted on the circuit board PB. In this embodiment, the driver chip DC directly mounted on the display panel DP and the circuit board PB can be collectively referred to as electronic components.

[0070] The display panel DP may include a curved area BA and a first non-curved area NBA1 and a second non-curved area NBA2 arranged in a first direction DR1, separated from the curved area BA.

[0071] The bending region BA can be defined as the area where the display panel DP bends along a virtual bending axis BX extending in the second direction DR2. Alternatively, a first non-bending region NBA1 can be defined as the area overlapping with the transmissive region TA, and a second non-bending region NBA2 can be defined as the area connecting the circuit board PB. When the bending region BA bends with respect to the bending axis BX, the circuit board PB and the driving chip DC can be bent in a direction toward the back of the display panel DP and positioned below the back of the display panel DP. Although not shown, additional structures can be configured to compensate for the step between the circuit board PB and the back of the display panel DP created by the bending region BA.

[0072] According to one embodiment, the width of the first non-curved region NBA1 in the second direction DR2 may be greater than the widths of the curved region BA and the second non-curved region NBA2. However, it is not limited to this, and the width of the curved region BA in the second direction DR2 may be provided as a shape that narrows from the first non-curved region NBA1 to the second non-curved region NBA2, not limited to any one embodiment.

[0073] like Figure 2a as well as Figure 2b As shown, as a portion of the display panel DP bends, the circuit board PB, which is electrically bonded to the display panel DP, can be disposed on the back side of the display panel DP.

[0074] The housing component BC can accommodate the display module DM and integrate it with the window WM. The circuit board PB can be positioned at one end of the display panel DP and electrically connected to the... Figure 3 The circuit element layer DP-CL is described in the diagram. Although not shown, the display device DD may also include a motherboard, an electronic module mounted on the motherboard, a camera module, a power supply module, etc.

[0075] The above description of a mobile phone terminal as an example of a display device DD is provided. However, in this specification, a display device DD may include two or more bonded electronic components. Each of the display panel DP and the driver chip DC mounted on the display panel DP is a different electronic component, and the display device DD can be constituted by these alone. Each of the display panel DP and the circuit board PB connected to the display panel DP is also a different electronic component, and the display device DD can be constituted by these alone. In addition, a display device DD can be constituted by the motherboard and the electronic module mounted on the motherboard alone. Hereinafter, the display device DD according to this utility model will be described with a focus on the bonding structure of the display panel DP and the driver chip DC mounted on the display panel DP.

[0076] Figure 3 This is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0077] Reference Figure 3 The display panel (DP) may include a substrate layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and an upper insulating layer (TFL). The input sensor (ISU) may be configured on the upper insulating layer (TFL).

[0078] The display panel (DP) can include the display area DP-DA and the non-display area DP-NDA. Specifically, the display area DP-DA of the display panel (DP) and... Figure 1 The display area shown is DD-DA or Figure 2a The transmission area TA shown corresponds to the non-display area DP-NDA. Figure 1 The non-display area DD-NDA shown is... Figure 2a The non-transmissive region NTA is shown.

[0079] The substrate layer BL may include at least one plastic film. The substrate layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate as a flexible substrate.

[0080] The circuit element layer DP-CL may include at least one intermediate insulating layer and circuit elements. The intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements may include signal lines, pixel driving circuits, etc. The insulating layer, semiconductor layer, and conductive layer are formed by processes such as coating and evaporation. Subsequently, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns, and signal lines are formed by such processes. Patterns disposed on the same layer are formed by the same process. Hereinafter, "patterns formed by the same process" means that they contain the same materials, including the same layered structure.

[0081] The display element layer of a DP-OLED can include multiple light-emitting elements. The DP-OLED display element layer may also include organic layers such as pixel-defining films.

[0082] The upper insulating layer (TFL) can seal the display element layer (DP-OLED). The upper insulating layer (TFL) can be disposed on the display element layer (DP-OLED). The upper insulating layer (TFL) can overlap with the display area (DP-DA) and the non-display area (DP-NDA). The upper insulating layer (TFL) can overlap with at least a portion of the non-display area (DP-NDA). As an example, the upper insulating layer (TFL) can include a thin-film encapsulation layer. The thin-film encapsulation layer can include a stacked structure of inorganic layers, organic layers, and inorganic layers. The upper insulating layer (TFL) can protect the display element layer (DP-OLED) from foreign matter such as moisture, oxygen, and dust particles. However, it is not limited to this; the upper insulating layer (TFL) can also include additional insulating layers besides the thin-film encapsulation layer. For example, it can also include an optical insulating layer for controlling the refractive index.

[0083] In one embodiment of this invention, a packaging substrate can be provided instead of the upper insulating layer TFL. In this case, the packaging substrate can be opposite the base layer BL, and a circuit element layer DP-CL and a display element layer DP-OLED can be disposed between the packaging substrate and the base layer BL.

[0084] The input sensor ISU can be directly mounted on the display panel DP. In this specification, "structure A is directly mounted on structure B" means that there is no separate layer between structure A and structure B. In this embodiment, the input sensor ISU can be manufactured together with the display panel DP using a continuous process. However, the inventive concept is not limited to this; the input sensor ISU can be provided as a separate panel, thus bonded to the display panel DP via an adhesive layer. Alternatively, the input sensor ISU can be omitted.

[0085] Figure 4 This is a plan view of a display panel DP according to an embodiment of the present invention.

[0086] Reference Figure 4 The display panel DP may include multiple pixels PX, gate drive circuit GDC, multiple signal lines SGL and multiple signal pads DP-PD.

[0087] Pixels (PX) can be configured in the display area DP-DA. Each pixel (PX) includes a light-emitting element and a pixel driving circuit connected thereto. In one embodiment, the light-emitting element may be an organic light-emitting element. The gate driving circuit (GDC) sequentially outputs gate signals to a plurality of gate lines (GL) described later. The transistors of the gate driving circuit (GDC) can be formed using the same process as the transistors of the pixel (PX), such as LTPS (Low Temperature Polycrystalline Silicon) or LTPO (Low Temperature Polycrystalline Oxide) processes. The display panel DP may also include another driving circuit that provides light emission control signals to the pixels (PX).

[0088] The signal line SGL may include gate line GL, data line DL, power line PL, and control signal line CSL. Specifically, the gate line GL may be connected to a corresponding pixel PX within a pixel PX, and the data line DL may be connected to a corresponding pixel PX within a pixel PX. The power line PL may be connected to a pixel PX. The control signal line CSL provides control signals to the scan drive circuit.

[0089] Signal lines SGL may overlap with the display area DP-DA and the non-display area DP-NDA. Each signal line SGL may include a routing portion LP. Although not shown, the signal line SGL may also include a pad portion. The routing portion LP may overlap with the display area DP-DA and the non-display area DP-NDA. The pad portion may be connected to the end of the routing portion LP.

[0090] Multiple signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. Alternatively, the area configuring the first and second pads PD1 and PD2 can be defined as the first pad area PA1, and the area configuring the third pad PD3 can be defined as the second pad area PA2.

[0091] It is possible that the first pad area PA1 is with Figure 2a The first pad region PA1 may include a first region B1 for configuring the first pad PD1 and a second region B2 for configuring the second pad PD2. The first pad region PA1 and the second pad region PA2 may be configured within the non-display area DP-NDA. The first pad region PA1 and the second pad region PA2 may be spaced apart from each other in the first direction DR1. An exemplary illustration shows a single pad row configured in the first pad region PA1, but this is not limited to this; multiple pad rows may also be configured in the first pad region PA1.

[0092] Each of the first pads PD1 can be connected to the corresponding data line DL in the data line DL. Although not shown, the first pads PD1 and the second pads PD2 can be electrically connected to each other. The second pad PD2 can be connected to the third pad PD3 via the connection signal line SCLn.

[0093] The circuit board PB may include multiple substrate bump electrodes PB-BP. The substrate bump electrodes PB-BP may be arranged in the second direction DR2. The substrate bump electrodes PB-BP of the circuit board PB may be contacted and connected to the third pad PD3 of the second pad region PA2.

[0094] Figure 5 This is a cross-sectional view of a display panel DP with pixel PX according to an embodiment of the present invention.

[0095] Reference Figure 5 The display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA. Each pixel may include a light-emitting element OLED and pixel driving circuitry connected thereto. Specifically, a pixel PX may include a transistor TR and a light-emitting element OLED.

[0096] For example, in Figure 5 The image shows a transistor TR, but is not limited thereto. A pixel PX according to one embodiment may include seven transistors TR and at least one capacitor, the seven transistors TR and the capacitor being electrically connected to each other. However, the number of transistors TR and capacitors constituting the pixel PX is not limited to any one embodiment.

[0097] The display panel (DP) can include multiple insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating, semiconductor, and conductive layers can be formed through methods such as coating and vapor deposition. Subsequently, photolithography can be used to selectively pattern the insulating, semiconductor, and conductive layers. This method can form semiconductor patterns, conductive patterns, signal lines, etc., within both the circuit element layer (DP-CL) and the display element layer (DP-OLED).

[0098] The substrate layer BL may include a synthetic resin film. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may also have a three-layer structure consisting of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide resin layer, and the material is not particularly limited. In addition, the substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0099] In one embodiment, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, first to sixth insulating layers 10 to 60, a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1, and a second connection electrode CNE2.

[0100] At least one inorganic layer is disposed on top of the substrate layer BL. The inorganic layer can be formed in multiple layers. A barrier layer BRL can be disposed on the substrate layer BL. A buffer layer BFL can be disposed on the barrier layer BRL. Both the barrier layer BRL and the buffer layer BFL can be inorganic layers.

[0101] Semiconductor patterns are configured on the buffer layer BFL. The semiconductor patterns may contain polycrystalline silicon. However, they are not limited to this; the semiconductor patterns may also contain amorphous silicon or metal oxide.

[0102] Figure 5 Only a portion of the semiconductor pattern is shown; other semiconductor patterns may be configured on the plane in other areas of pixel PX. The semiconductor patterns may be arranged across pixel PX according to a specific rule. The electrical properties of the semiconductor patterns differ depending on whether they are doped or not. The semiconductor pattern may include a first region and a second region. The first region may be doped with either N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant.

[0103] The first region has higher conductivity than the second region and can essentially function as an electrode or signal line. The second region can be a region with low or no doping concentration and can essentially be equivalent to the active electrode A (or channel) of a transistor TR. In other words, part of the semiconductor pattern can be the active electrode A of a transistor TR, another part can be the source electrode S or drain electrode D of a transistor TR, and yet another part can be the connecting electrodes CNE1, CNE2, or the connecting signal line SCLd.

[0104] like Figure 5 As shown, the source S, active A, and drain D of transistor TR can be formed from a semiconductor pattern.

[0105] exist Figure 5 A portion of the connection signal line SCLd formed from a semiconductor pattern is shown. In one embodiment, the connection signal line SCLd may be electrically connected to the drain D of any of the transistors TR within the pixel PX.

[0106] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 may cover a semiconductor pattern. The first insulating layer 10 may overlap with multiple pixels PX. A gate G may be disposed on the first insulating layer 10. The gate G may be part of a metal pattern. The gate G may overlap with an active electrode A. In the process of doping the semiconductor pattern, the gate G may function as a mask.

[0107] A second insulating layer 20 covering the gate G can be disposed on the first insulating layer 10. The second insulating layer 20 can overlap with the pixel PX. An upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G of the transistor TR. The upper electrode UE can be part of a metal pattern. A portion of the gate G and the upper electrode UE overlapping therewith can define a capacitor.

[0108] A third insulating layer 30 covering the upper electrode UE can be disposed on the second insulating layer 20. The first connection electrode CNE1 disposed on the third insulating layer 30 can be connected to the connection signal line SCLd through the contact hole CNT-1 penetrating the first to third insulating layers 10 to 30.

[0109] A fourth insulating layer 40 covering the first connecting electrode CNE1 can be disposed on the third insulating layer 30. The first to fourth insulating layers 10 to 40 can be inorganic layers and / or organic layers, and can have a single-layer or multi-layer structure.

[0110] The first connecting electrode CNE1 can also be disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50. Alternatively, in one embodiment, both the first connecting electrode CNE1 disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 and the first connecting electrode CNE1 disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50 can be included.

[0111] A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 that penetrates the fourth insulating layer 40 and the fifth insulating layer 50.

[0112] A sixth insulating layer 60, covering the second connecting electrode CNE2, can be disposed on the fifth insulating layer 50. The sixth insulating layer 60 can be an organic layer. A first electrode AE ​​can be disposed on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.

[0113] On the other hand, the circuit element layer DP-CL may include multiple connection electrodes connected to the transistor TR, some of which may be configured on different layers. Although not shown, the first connection electrode CNE1 may also extend and connect to the transistor TR. The location of the multiple connection electrodes is not limited to any one embodiment.

[0114] The display element layer DP-OLED may include a pixel defining film PDL and a light-emitting element OLED. The pixel defining film PDL may define a pixel aperture OPN. The pixel aperture OPN of the pixel defining film PDL may expose at least a portion of the first electrode AE. In this embodiment, the light-emitting region PXA may be defined correspondingly to a portion of the first electrode AE ​​exposed through the pixel aperture OPN.

[0115] A hole control layer (HCL) can be commonly configured in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer HCL may include a hole transport layer and / or a hole injection layer. A light-emitting layer (EML) can be configured on the hole control layer HCL. The EML can be configured in the region corresponding to the pixel aperture (OPN). That is, the EML can be formed separately in each pixel PX. However, this is not a limitation; the EML can also be commonly formed in multiple pixels PX using an open mask.

[0116] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and / or an electron injection layer. A hole control layer (HCL) and the ECL may be jointly formed on the pixel (PX) using an open mask. A second electrode (CE) may be disposed on the ECL. The second electrode (CE) may have an integral shape and be jointly disposed on the pixel (PX). An upper insulating layer (TFL) may be disposed on the second electrode (CE). The upper insulating layer (TFL) may include multiple thin films.

[0117] Figure 6 This is an exploded perspective view of the pad areas PA1 and PA2 of a display device DD according to an embodiment of the present invention. Exemplarily, in Figure 6 The DC drive chip and the circuit board PB are shown in a disassembled view from the display panel DP. Figure 6 The first pad PD1, the second pad PD2, the connection signal line SCLn, and the third pad PD3 are connected to... Figure 4 The first pad PD1, the second pad PD2, the connecting signal line SCLn, and the third pad PD3 are the same, so the description will be omitted or simplified.

[0118] Reference Figure 4 as well as Figure 6The driver chip DC can be bonded to the first pad region PA1 via the first adhesive layer CF1. The circuit board PB can be bonded to the second pad region PA2 via the second adhesive layer CF2. The first and second adhesive layers CF1 and CF2 may contain an adhesive synthetic resin. Each of the first and second adhesive layers CF1 and CF2 may be a non-conductive film. That is, the first and second adhesive layers CF1 and CF2 may not contain conductive balls, but only an adhesive synthetic resin.

[0119] The driver chip DC may include a driving integrated circuit (D-IC) and a chip bump electrode DC-BP mounted within the driver chip DC. The driving integrated circuit D-IC may include an upper DC-US and a lower DC-DS, where the lower DC-DS may be the surface facing the first and second pads PD1 and PD2. The chip bump electrode DC-BP may be disposed on the lower DC-DS of the driving integrated circuit D-IC.

[0120] The chip bump electrode DC-BP may include a first bump BP1 electrically connected to a first pad PD1 and a second bump BP2 electrically connected to a second pad PD2. The first bump BP1 may be arranged along a second direction DR2, and the second bump BP2 may be spaced apart from the first bump BP1 in the first direction DR1 and arranged along the second direction DR2.

[0121] The driver chip DC can receive a first signal from the outside via the second pad PD2 and the second bump BP2. The driver chip DC can provide a second signal generated based on the first signal to the first pad PD1 via the first bump BP1. For example, the driver chip DC may include a data driving circuit. The first signal may be an image signal applied externally as a digital signal, and the second signal may be a data signal as an analog signal. The driver chip DC can generate an analog voltage corresponding to the grayscale value of the image signal. The data signal can be... Figure 4 The data line DL shown is provided to pixel PX.

[0122] Although not shown, the first bump BP1 and the second bump BP2 may be in a shape that protrudes from the underside DC-DS of the driver integrated circuit D-IC and is exposed to the outside. Alternatively, if the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed in a contact state, and the second pad PD2 and the second bump BP2 may be fixed in a contact state.

[0123] The circuit board PB may include a base layer P-BS and substrate bump electrodes PB-BP mounted within the circuit board PB. The circuit board PB may include a top PB-US and a bottom PB-DS, with the bottom PB-DS being the surface facing the third pad PD3. The substrate bump electrodes PB-BP may be disposed on the bottom PB-DS of the base layer P-BS. The substrate bump electrodes PB-BP may be electrically connected to the third pad PD3. The substrate bump electrodes PB-BP may be arranged along a second direction DR2. The circuit board PB can provide image signals, driving voltages, and other control signals to the driver chip DC.

[0124] Although not illustrated, the substrate bump electrode PB-BP may be in a shape that protrudes from below the substrate layer P-BS and is exposed to the outside. If the second adhesive layer CF2 is cured, the third pad PD3 and the substrate bump electrode PB-BP may be fixed in contact.

[0125] The electronic component may include a substrate and bump electrodes DC-BP and PB-BP disposed on the underside of the substrate. Alternatively, when the electronic component corresponds to the driver chip DC, the substrate corresponds to the driver integrated circuit D-IC of the driver chip DC, and the bump electrode corresponds to the chip bump electrode DC-BP. Or, when the electronic component corresponds to the circuit substrate PB, the substrate corresponds to the base layer P-BS of the circuit substrate PB, and the bump electrode corresponds to the substrate bump electrode PB-BP.

[0126] Figure 7a This is a simplified plan view of the pad areas PA1 and PA2 according to an embodiment of the present invention. Figure 7b as well as Figure 7c These are cross-sectional views of pad areas PA1 and PA2 according to an embodiment of the present invention. Figure 7b Is with Figure 7a The cross-sectional view of the pad areas PA1 and PA2 corresponding to the A-A' line. Figure 7c Is with Figure 7a The cross-sectional view of the pad areas PA1 and PA2 corresponding to B-B'. Figure 8 This is a cross-sectional view showing the bonding structure of a display device DD according to an embodiment of the present invention.

[0127] Figures 7a to 8 The signal pad DP-PD (or signal pad structure) shown can be a reference. Figure 4 as well as Figure 6 The description refers to any one of the first to third pads, PD1 to PD3. Figure 7aThe text describes a data line DL, including a terminal section DL-E and a line section DL-S with different widths, as an example of a signal line, but it is not limited to this. Here, "width" can refer to the length or width of the terminal section DL-E or the line section DL-S in a second direction. The signal line can be any signal line other than the data line DL, or it can have a uniform width without distinguishing between the terminal section DL-E and the line section DL-S. The terminal section DL-E can be... Figure 4 This corresponds to the pad section mentioned above.

[0128] The following description focuses on pad areas PA1 and PA2, centered on the first pad area PA1 used for configuring the data line DL. The second pad area PA2, in addition to replacing the data line DL, is configured to connect the signal line SCLn (see [reference]). Figure 4 The same description applies to the first pad area PA1, except for ).

[0129] Reference Figure 7a The signal pad DP-PD may include a first conductive pattern CL1, a second conductive pattern CL2, and at least one insulating pattern SP. The first conductive pattern CL1 can be connected to the end of the data line DL-E through at least one contact hole OP-C. Figure 7a The example shows a signal pad DP-PD comprising seven contact holes OP-C and six insulating patterns SP, but the number of contact holes OP-C and insulating patterns SP is not limited thereto.

[0130] The end portion DL-E in the plane may have a shape that extends in the first direction DR1. That is, the length or width of the end portion DL-E in the first direction DR1 may be greater than the length or width in the second direction DR2.

[0131] On the plane, contact holes OP-C may overlap with the end portion DL-E. Contact holes OP-C may be arranged along the first direction DR1. Contact holes OP-C may be spaced apart within the first direction DR1. A portion of the first conductive pattern CL1 on the plane may overlap with contact holes OP-C.

[0132] The insulating pattern SP can overlap with the second conductive pattern CL2 on the plane. The insulating pattern SP can be spaced apart from the contact hole OP-C on the plane. In this embodiment, the insulating pattern SP can be arranged along the first direction DR1. The insulating patterns SP can be spaced apart from each other within the first direction DR1.

[0133] In this embodiment, the insulating pattern SP can be configured between adjacent contact holes OP-C. Figure 7a The example shows six insulating patterns SP of each of the six planes disposed between the seven contact holes OP-C, but the configuration is not limited thereto.

[0134] exist Figure 7a The example shown illustrates an insulating pattern SP that is a square on a plane, but it is not limited to this. The shape of the insulating pattern SP on the plane can be changed to a polygon, a circle, an ellipse, etc., other than a square. In addition, the shapes of the insulating patterns SP are not limited to being the same as each other.

[0135] Reference Figure 7b as well as Figure 7c The end portion DL-E can be disposed on the first insulating layer 10. The end portion DL-E can be disposed with... Figure 5 The terminal portion DL-E is formed on the same layer as the gate G. The terminal portion DL-E can be formed using the same process as the gate G. The terminal portion DL-E can contain the same material as the gate G.

[0136] However, the location of the distal DL-E is not limited to this. The distal DL-E can also be... Figure 5 The upper electrode UE shown is configured on the same layer, contains the same material, and has the same stacked structure. Alternatively, a portion of the multiple signal lines may pass through the gate G (see reference). Figure 5 The other part is formed using the same process as the upper electrode UE (refer to...). Figure 5 Formed using the same process.

[0137] On the other hand, a data cable DL can be configured on a single layer and have a unified shape, but is not limited to this. A data cable DL can include multiple parts configured on different layers. For example, the line section DL-S (see reference). Figure 7a () can include more than two parts.

[0138] The first conductive pattern CL1 can be disposed on the fourth insulating layer 40. The first conductive pattern CL1 can be connected to the end portion DL-E through the contact hole OP-C penetrating the second to fourth insulating layers 20, 30, and 40. That is, the first conductive pattern CL1 can contact the end portion DL-E through the contact hole OP-C. The second to fourth insulating layers 20, 30, and 40 can be connected to the end portion DL-E through the contact hole OP-C. Figure 5 The second to fourth insulating layers 20, 30, and 40 of the display area DP-DA shown are formed using the same process. In this specification, the insulating layer disposed between the end portion DL-E and the first conductive pattern CL1 can be defined as the pad insulating layer IL-P. In this embodiment, the second to fourth insulating layers 20, 30, and 40 can be defined as the pad insulating layer IL-P. Alternatively, the stack-up structure of the pad insulating layer IL-P can be based on the circuit element layer DP-CL (refer to...). Figure 5 The layered structure can be modified. In one embodiment, the contact hole OP-C can be defined by a greater number of insulating layers than the second to fourth insulating layers 20, 30, 40, or by a smaller number of insulating layers.

[0139] The first conductive pattern CL1 and the end portion DL-E can be distinguished by the pad insulating layer IL-P (e.g., the second to fourth insulating layers 20, 30, 40) disposed between them.

[0140] The second conductive pattern CL2 can be disposed on the first conductive pattern CL1. The second conductive pattern CL2 is related to the insulating pattern SP (see reference). Figure 7a Non-overlapping areas can contact the first conductive pattern CL1.

[0141] In one embodiment, the first conductive pattern CL1 may be connected to the first conductive pattern CL1 via a conductor in the first conductive pattern CL1. Figure 5 The first connecting electrode CNE1 described above is formed using the same process, and the second conductive pattern CL2 is formed using the same process as in... Figure 5 The second connecting electrode CNE2 described above is formed using the same process. Alternatively, the first conductive pattern CL1 may contain elements identical to the first connecting electrode CNE1 (see reference 1). Figure 5 The second conductive pattern CL2 contains the same material as the second connecting electrode CNE2 (see reference). Figure 5 The same substance. Figure 7b as well as Figure 7c An exemplary embodiment is shown in which the first conductive pattern CL1 is disposed on the fourth insulating layer 40. According to the embodiment, the first conductive pattern CL1 may be disposed on the third insulating layer 30, in which case the fourth insulating layer 40 may not be disposed in the pad regions PA1, PA2. However, this is not a limitation; if the combination of connection electrodes formed by the same process as the first and second conductive patterns CL1, CL2 can provide first and second conductive patterns CL1, CL2 on different layers, then it can be based on the circuit element layer DP-CL (refer to...). Figure 5 Various choices can be made based on the layered structure of the structure.

[0142] On a plane, an exemplary illustration shows a second conductive pattern CL2 having an area larger than that of a first conductive pattern CL1, with the edges of the second conductive pattern CL2 positioned outwards and covering the edges of the first conductive pattern CL1, but this is not a limitation. Alternatively, the second conductive pattern CL2 may have substantially the same area as the first conductive pattern CL1, with the edges of the second conductive pattern CL2 substantially aligned with the edges of the first conductive pattern CL1.

[0143] A portion of the second conductive pattern CL2 may include a portion that overlaps with the insulating pattern SP on a plane. The insulating pattern SP may be disposed in cross-section between the first conductive pattern CL1 and the second conductive pattern CL2. The insulating pattern SP may be disposed on the first conductive pattern CL1 and covered by the second conductive pattern CL2. The second conductive pattern CL2 may cover the top U-SP and the side S-SP of the insulating pattern SP.

[0144] In this specification, the lower surface D-SP of the insulating pattern SP can be defined as the surface of the insulating pattern SP that contacts the first conductive pattern CL1. The upper surface U-SP of the insulating pattern SP can be defined as the surface opposite to the lower surface D-SP in the surface of the insulating pattern SP that contacts the second conductive pattern CL2. The side surface S-SP of the insulating pattern SP can be defined as any surface other than the upper surface U-SP in the surface of the insulating pattern SP that contacts the second conductive pattern CL2.

[0145] The insulating pattern SP can have a trapezoidal shape in cross-section. The insulating pattern SP can have an inclined side S-SP, and the inclination of the side S-SP relative to the lower D-SP can be an acute angle. However, it is not limited to this; the insulating pattern SP can also have a rectangular shape in cross-section, or it can have an inverted trapezoidal shape.

[0146] The insulating pattern SP may contain polymers. The insulating pattern SP may contain thermosetting polymers. However, it is not limited to this; the insulating pattern SP may also contain thermoplastic polymers.

[0147] In one embodiment, the insulating pattern SP can be connected to the fifth insulating layer 50 (see reference). Figure 5 The same process is used to form the insulating pattern SP. Therefore, the additional process for forming the insulating pattern SP is not required. However, this is not the only limitation; combinations of connecting electrodes formed using the same process as the first and second conductive patterns CL1 and CL2 can be based on the circuit element layer DP-CL (refer to...). Figure 5 Various options can be made for the layered structure of the insulating layer, which can be formed by the same process as the insulating pattern SP.

[0148] The portion of the second conductive pattern CL2 that covers the insulating pattern SP may protrude from the first conductive pattern CL1 in a third direction DR3, compared to other portions of the second conductive pattern CL2. This protruding portion of the second conductive pattern CL2 may be referred to as the protruding portion CL2-T. The second conductive pattern CL2 may contact the top of the first conductive pattern CL1, the side surface S-SP of the insulating pattern SP, and the top surface U-SP of the insulating pattern SP, which do not overlap with the insulating pattern SP. The protruding portion CL2-T of the conductive pattern CL2 may correspond to the portions that contact the side surface S-SP and the top surface U-SP of the insulating pattern SP.

[0149] The second conductive pattern CL2 may include a first layer CL2-1, a second layer CL2-2, and a third layer CL2-3 stacked sequentially. The first layer CL2-1 may be disposed on the first conductive pattern CL1. The first layer CL2-1 may contact the top of the first conductive pattern CL1 (which does not overlap with the insulating pattern SP), the side surface S-SP of the insulating pattern SP, and the top surface U-SP of the insulating pattern SP. The second layer CL2-2 may be disposed on the first layer CL2-1. The first layer CL2-1 may cover the bottom of the second layer CL2-2. The third layer CL2-3 may be disposed on the second layer CL2-2. The third layer CL2-3 may cover the top of the second layer CL2-2.

[0150] The thickness of the second CL2-2 layer can be greater than the thickness of the first CL2-1 layer. The thickness of the third CL2-3 layer can be thinner than the thickness of the second CL2-2 layer. The second CL2-2 layer can have higher conductivity than both the first CL2-1 layer and the third CL2-3 layer. The second CL2-2 layer can contain a material with higher conductivity than the materials contained in the first CL2-1 layer and the third CL2-3 layer. The first CL2-1 layer and the third CL2-3 layer can contain the same material. The second CL2-2 layer can contain a different material than the materials contained in the first CL2-1 layer and the third CL2-3 layer. For example, the first CL2-1 layer and the third CL2-3 layer can contain titanium (Ti), and the second CL2-2 layer can contain aluminum (Al).

[0151] The second conductive pattern CL2 may also include an oxide film (not shown) formed on top of and covering the third layer CL2-3. For example, the oxide film formed on top of the third layer CL2-3 may contain titanium oxide (TiO2). x ).

[0152] The second layer CL2-2 can be covered by the third layer CL2-3, when the second layer CL2-2 is bonded to the first adhesive layer CF1 (see reference). Figure 6 When in contact, it prevents surface oxidation of the second layer CL2-2. Specifically, it prevents oxidation of the second layer CL2-2 due to oxygen atoms (O) contained in the first adhesive layer CF1.

[0153] The groove pattern GVP is defined in the second conductive pattern CL2.

[0154] Reference Figure 7a The groove pattern GVP can be configured in the area of ​​the second conductive pattern CL2 that overlaps with the insulating pattern SP. Figure 7aThe planar shape of the groove pattern GVP shown is a rectangle elongated in the first direction DR1, but this is exemplary, and the planar shape can be a polygon, circle, ellipse, etc., other than a rectangle. Additionally, the groove pattern GVP, including one groove, is shown overlapping an insulating pattern SP, but this is exemplary; a groove pattern GVP including two or more grooves can also overlap an insulating pattern SP.

[0155] The groove pattern GVP can be a single or multiple grooves on the cross-section, or a single or multiple cracks, as long as it is disposed on the U-SP of the insulating pattern SP (refer to...). Figure 7c The shape of the second layer CL2-2 that is exposed is unrestricted.

[0156] Reference Figure 7c The groove pattern GVP can penetrate the third layer CL2-3 and expose the second layer CL2-2. The groove pattern GVP can be defined as the protruding portion CL2-T of the second conductive pattern CL2 disposed on the insulating pattern SP and protruding therein.

[0157] Specifically, such as Figure 7c As shown, the groove pattern GVP can be defined as the third layer CL2-3 of the second conductive pattern CL2 disposed on the upper U-SP of the insulating pattern SP. In this case, the groove pattern GVP can be an opening pattern that penetrates the third layer CL2-3. The opening pattern can penetrate the third layer CL2-3 and expose the upper surface of the second layer CL2-2.

[0158] Alternatively, although not illustrated, the groove pattern GVP may be defined on a portion of the second layer CL2-2 and the third layer CL2-3 of the second conductive pattern CL2 disposed on the upper U-SP of the insulating pattern SP. In this case, the groove pattern GVP may include an opening pattern penetrating the third layer CL2-3 and a groove pattern extending from the opening pattern and defined on the upper surface of the second layer CL2-2.

[0159] Figure 8 An example is shown of a driver chip DC as an electronic accessory. Figure 8 The chip bump electrode DC-BP of the driver chip DC is shown (reference). Figure 6 The first bump BP1 and the first pad PD1 in the ) (refer to Figure 6 The contact state. First pad PD1 (refer to...) Figure 6 )exist Figure 8 The image shows the signal pads DP-PD.

[0160] Through the bonding process, the first bump BP1 of the driver chip DC can penetrate the first adhesive layer CF1 and make contact with the second conductive pattern CL2 of the signal pad DP-PD.

[0161] In the case of the display device DD of this utility model, the shape of the interface where the first bump BP1 and the second layer CL2-2 contact can be a single trench shape, or multiple trench shapes or multiple crack shapes spaced at certain intervals. Alternatively, in the case of multiple trench shapes or multiple crack shapes, the depths of the trench shapes and crack shapes can be substantially the same. That is, unlike this utility model, the signal pads without defined groove patterns GVP do not have various spacings and / or depths of crack shapes generated by pressure tearing the second layer during bonding.

[0162] The display device DD of this invention can be energized through direct contact between the first bump BP1 and the second conductive pattern CL2, specifically, by achieving physicochemical bonding between the material constituting the first bump BP1 and the material constituting the second conductive pattern CL2, thereby further improving the reliability of the electrical connection.

[0163] That is, the display device DD of this invention, by not containing conductive balls, can prevent short-circuit defects through conductive balls, and / or current-carrying defects when the conductive balls are not positioned between the signal pads DP-PD and the bump electrodes, even when the signal pads DP-PD are densely packed. This facilitates the realization of high-resolution panels.

[0164] The display device DD of this invention can enhance the signal pads DP-PD and the driver chip DC (see reference) by defining a groove pattern GVP on the upper surface of the second conductive pattern CL2. Figure 6 ) or circuit board PB (refer to Figure 6 The bonding reliability of electronic components such as [missing information].

[0165] Specifically, compared to the case where the second conductive pattern CL2 does not have the groove pattern GVP, bump electrodes DC-BP and PB-BP of the electronic components can be added (see reference). Figure 6 The area of ​​direct contact between the second layer CL2-2 exposed by the groove pattern GVP and the bump electrodes DC-BP and PB-BP (refer to...). Figure 6 The area in direct contact with the second layer CL2-2 can improve the initial resistance and reliability resistance.

[0166] Furthermore, a groove pattern GVP is pre-formed in the second conductive pattern CL2 before bonding, thus allowing for a lower-voltage bonding process compared to the case without the groove pattern GVP. When the second conductive pattern CL2 lacks the groove pattern GVP, it is necessary to expose the second layer CL2-2 by applying pressure to the third layer CL2-3 during bonding, thereby exposing the second layer CL2-2 to contact the bump electrode. That is, a high-voltage process is required. This invention is possible with a low-voltage process, which also prevents bonding issues during the display panel DP (Display Panel Display).Figure 6 Defects caused by the lifting of the film (e.g., an organic film) in the membrane. Additionally, the bonding process is performed immediately after the formation of the groove pattern GVP, thus also preventing oxidation of the exposed second layer CL2-2.

[0167] The following description describes a method for manufacturing a display device according to an embodiment, with reference to the accompanying drawings. In this description of the method for manufacturing a display device according to an embodiment, details that are repeated in the description of the display device according to the above embodiment are omitted.

[0168] Figures 9 to 1 Id These are cross-sectional views that briefly illustrate one step of a method for manufacturing a display device according to an embodiment of the present invention.

[0169] For ease of explanation, Figures 9 to 1 Id They respectively showed the same as Figure 7a The cross-section corresponding to the B-B' line. Figures 9 to 1 Id In the same context, the aforementioned principles can be applied to the same structure. Figures 4 to 7c The description in the text is omitted, with detailed explanations omitted.

[0170] One embodiment of the display device manufacturing method may include the steps of providing a pre-signal pad P-PD and forming a groove pattern GVP to manufacture the signal pad DP-PD.

[0171] Figure 9 This is a cross-sectional view that briefly illustrates the steps involved in providing the pre-signal pads P-PD. (Refer to...) Figure 9 The pre-signal pad P-PD may include a first conductive pattern CL1, a second conductive pattern CL2, and an insulating pattern SP.

[0172] The first conductive pattern CL1 can be disposed on the substrate layer BL. The first conductive pattern CL1 can be connected to a signal line (e.g., a data line DL, see reference). Figure 4 The second conductive pattern CL2 can be disposed on the first conductive pattern CL1. The insulating pattern SP can be disposed between the first conductive pattern CL1 and the second conductive pattern CL2.

[0173] The second conductive pattern CL2 may include a first layer CL2-1, a second layer CL2-2, and a third layer CL2-3 stacked sequentially. The first layer CL2-1 may cover the portion of the first conductive pattern CL1 without an insulating pattern SP and the insulating pattern SP, and is configured thereon. The second layer CL2-2 may cover the first layer CL2-1 and is configured thereon. The third layer CL2-3 may cover the second layer CL2-2 and is configured thereon.

[0174] The thickness of the first layer CL2-1 and the thickness of the third layer CL2-3 can each be thinner than the thickness of the second layer CL2-2.

[0175] The first CL2-1 and the third CL2-3 layers can contain materials different from the second CL2-2 layer. The material contained in the second CL2-2 layer can have higher conductivity compared to the material contained in the first CL2-1 and the third CL2-3 layers. For example, the first CL2-1 and the third CL2-3 layers can contain titanium (Ti), and the second CL2-2 layer can contain aluminum (Al). An oxide film (not shown) can also be added above the third CL2-3 layer. For example, the oxide film can contain titanium oxide (TiO2). x The second CL2-2 layer can be covered by the third CL2-3 layer to prevent oxidation.

[0176] The first and second conductive patterns CL1 and CL2 can be formed by processes such as coating and vapor deposition. The first and second conductive patterns CL1 and CL2 can be selectively patterned by photolithography and etching processes.

[0177] The insulating pattern SP can have a trapezoidal shape in the cross section. However, it is not limited to this; the insulating pattern SP can also have a rectangular shape in the cross section, or it can also have an inverted trapezoidal shape.

[0178] The insulating pattern SP may contain polymers. The insulating pattern SP may contain thermosetting polymers. However, it is not limited to this; the insulating pattern SP may also contain thermoplastic polymers.

[0179] Regarding the planar arrangement of the first and second conductive patterns CL1, CL2 and the insulating pattern SP, it can be applied to... Figure 7a The aforementioned content.

[0180] Between the base layer BL and the pre-signal pads P-PD, a barrier layer BRL, a buffer layer BFL, and signal lines (e.g., data lines DL, see reference) can also be configured. Figure 4 The end portion DL-E and the pad insulation layer IL-P.

[0181] Figure 10a as well as Figure 11a The following is a brief illustration of the GVP pattern forming the groove (see reference). Figure 8 A cross-sectional view of the steps involved in manufacturing the DP-PD signal pads. Figure 10b as well as Figure 11b Prior to the bonding process described later, a groove pattern GVP can be formed on the second conductive pattern CL2. Forming the groove pattern GVP before the bonding process prevents oxidation of the exposed second layer CL2-2 when stored separately for intermediate processes.

[0182] Figure 10a as well as Figure 11aThe processes for forming the groove pattern GVP are illustrated by way of example.

[0183] Reference Figure 10a The process of forming the groove pattern GVP in the second conductive pattern CL2 can be a laser LS process. A brief illustration shows the process of etching the upper part of the second conductive pattern CL2 using laser LS.

[0184] The second conductive pattern CL2 can be exposed by laser LS etching of the third layer CL2-3 in the second conductive pattern CL2. Alternatively, the second conductive pattern CL2 can be exposed by etching of the third layer CL2-3 and a portion of the second layer CL2-2.

[0185] The groove pattern GVP can be formed in the area on the plane that overlaps with the upper U-SP of the insulating pattern SP, so that the second layer CL2-2 exposed through the groove pattern GVP in subsequent bonding processes can be bonded to the first bump BP1 (see reference). Figure 8 Contact. That is, a groove pattern GVP can be defined on the portion of the second conductive pattern CL2 above the insulating pattern SP U-SP. The groove pattern GVP may include multiple grooves.

[0186] exist Figure 10a Examples are shown in the foregoing. Figure 7a Similar to the method described above, laser LS patterning is performed on the first direction DR1 to pattern a groove on an insulating pattern SP. However, it is not limited to this method. Laser LS patterning can also be performed on the second direction DR2, and the number of grooves on an insulating pattern SP can be two or more. Alternatively, patterning can be performed in directions other than the first and second directions DR1 and DR2, and the pattern can be a point shape that is not a line shape or other polygonal or circular shapes.

[0187] Reference Figure 11a A groove pattern GVP is formed in the second conductive pattern CL2 (refer to...) Figure 8 The process can be a needle-ND process. A simplified illustration shows a process for forming a crack above the second conductive pattern CL2 using a needle-ND. The needle-ND can be positioned below the stage STG. In this specification, the groove pattern GVP can be defined as including the crack shape.

[0188] Microneedle NDs can be used as long as they are made of a material with a hardness greater than that of the etched layer of the desired second conductive pattern CL2. For example, when the third layer CL2-3 of the second conductive pattern CL2 is titanium (Ti), the microneedle ND can contain a material with a hardness greater than titanium. When etching to a portion of the second layer CL2-2, for example, if the second layer CL2-2 is aluminum (Al), the microneedle ND can contain a material with a hardness greater than both titanium and aluminum. For example, the microneedle ND can contain quartz or SUS (stainless steel).

[0189] The second conductive pattern CL2 can be exposed by ND etching of the third layer CL2-3 in the second conductive pattern CL2. Alternatively, the second conductive pattern CL2 can be exposed by etching of the third layer CL2-3 and a portion of the second layer CL2-2.

[0190] The groove pattern GVP can be formed in the area on the plane that overlaps with the upper U-SP of the insulating pattern SP, so that the second layer CL2-2 exposed through the groove pattern GVP in subsequent bonding processes can be bonded to the first bump BP1 (see reference). Figure 8 Contact. That is, a groove pattern GVP can be defined on the portion of the second conductive pattern CL2 above the insulating pattern SP U-SP. The groove pattern GVP can include multiple cracks. The multiple cracks can be formed in a shape corresponding to the microneedle ND.

[0191] exist Figure 11a The illustration shows patterning by moving the microneedle ND in the aforementioned first direction DR1, but it is not limited to this. Patterning can also be achieved by moving the microneedle ND in the second direction DR2, or in directions other than those described above. Alternatively, it can be patterned into a dot shape that is not a line shape, or other polygonal or circular shapes. Furthermore, the number of puncture needles included in the microneedle ND can be one or more.

[0192] One embodiment of the display device manufacturing method may further include bonding signal pads DP-PD and electronic components (e.g., driver chip DC, see reference). Figure 8 The bonding steps.

[0193] Figure 10b as well as Figure 11b These are cross-sectional views that briefly illustrate the steps of signal pad DP-PD, including the groove pattern GVP, and DC bonding of the driver chip. Figure 10b as well as Figure 11b The DC driver chip is exemplary and can also be applied to the circuit board PB (see reference). Figure 6 Other electronic accessories.

[0194] The steps for signal pad DP-PD and driver chip DC bonding can be performed in Figure 10a as well as Figure 11a The GVP (Groove Vessel Plasma) process is performed immediately after the groove pattern is formed. Therefore, oxidation of the second CL2-2 layer exposed through the groove pattern GVP can be prevented.

[0195] Figure 10b Exemplary illustration via Figure 10a The bonding process following the formation of the groove pattern GVP by the laser LS process. Figure 11b Exemplary illustration via Figure 11a The bonding process following the formation of the groove pattern GVP using the microneedle ND process.

[0196] Before bonding, a groove pattern GVP is pre-formed in the second conductive pattern CL2, allowing for a lower bonding pressure compared to the case without a groove pattern GVP. Without a groove pattern GVP in the second conductive pattern CL2, a crack needs to be formed in the third layer CL2-3 during bonding to expose the second layer CL2-2, allowing it to contact the bump electrode. This requires high pressure.

[0197] The bonding process of this invention can be applied to low-voltage processes and can also prevent bonding from occurring during the display panel DP (refer to...) Figure 6 Defects that occur when the membrane (e.g., an organic membrane) in a film (e.g.) warps up.

[0198] Figure 10c as well as Figure 11c A display device DD that briefly shows the bonding status of the pad areas. Figure 10c Exemplary Figure 10b The display device DD after the bonding process, Figure 11c Exemplary Figure 11b The display device DD after the bonding process.

[0199] Figure 11d Enlarged display Figure 11c The first bump BP1 is a portion XX' of the contact area between the first bump BP1 and the second conductive pattern CL2. The first bump BP1 can directly contact the second layer CL2-2 through the groove pattern GVP, which penetrates the third layer CL2-3. Electricity can be passed between the materials constituting the first bump BP1 and the materials constituting the second layer CL2-2 through physicochemical bonding. Figure 10c The contact portion between the first bump BP1 and the second conductive pattern CL2 also differs only in the shape of the groove pattern GVP. The first bump BP1 penetrates the third layer CL2-3 through the groove pattern GVP and directly contacts the second layer CL2-2. Figure 11d The same as shown.

[0200] The display device DD for the bonding status of the pad area can be similarly applied to... Figure 8 The content mentioned above is omitted here for brevity.

[0201] The display device DD manufactured according to the manufacturing method of this utility model can be energized through direct contact between the first bump BP1 and the second conductive pattern CL2, specifically, by achieving physicochemical bonding between the material constituting the first bump BP1 and the material constituting the second conductive pattern CL2, thereby further improving the reliability of the electrical connection.

[0202] That is, the display device DD manufactured according to the manufacturing method of this utility model, by not containing conductive balls, can prevent short-circuit defects through conductive balls and / or poor power conduction when the conductive balls are not positioned between the signal pads DP-PD and the bump electrodes, even when the signal pads DP-PD are densely packed. This facilitates the realization of high-resolution panels.

[0203] Furthermore, the manufacturing method of this invention can enhance the signal pad DP-PD and the driver chip DC or circuit board PB (see reference) by including the step of forming a groove pattern GVP above the second conductive pattern CL2. Figure 6 The bonding reliability of electronic components such as [missing information].

[0204] Specifically, compared to the case where the second conductive pattern CL2 does not form a groove pattern GVP and a bonding process is performed, bump electrodes DC-BP and PB-BP of the electronic components can be added (refer to...). Figure 6 The area of ​​direct contact between the second layer CL2-2 exposed by the groove pattern GVP and the bump electrodes DC-BP and PB-BP (refer to...). Figure 6 The area in direct contact with the second layer CL2-2 can improve the initial resistance and reliability resistance.

[0205] Figures 12a to 12d These are simplified plan views of the pad areas according to yet another embodiment of the present invention.

[0206] To explain Figures 12a to 12d The length of the first direction DR1, the length of the second direction DR2, and / or the area of ​​the groove included in the groove pattern GVP are briefly shown and are exemplary, and are not limited to the lengths and / or areas shown in the figures.

[0207] Figure 12a The pad areas PA1 and PA2 are illustrated exemplarily as shown in... Figure 7a The same as the groove pattern GVP extending in the first direction DR1, or the groove pattern GVP in the shape of a rectangle, but defined on an insulating pattern SP, includes two grooves.

[0208] Figure 12b The pad areas PA1 and PA2 are illustrated exemplarily as shown in... Figure 7a The groove pattern GVP includes a groove on an insulating pattern SP, but it is a line or rectangular groove pattern GVP extending in the second direction DR2.

[0209] Figure 12c An exemplary illustration shows pad areas PA1, PA2 comprising a groove pattern GVP consisting of nine dots or square-shaped grooves on an insulating pattern SP. The number, size / area / position of the dots or square-shaped grooves are not limited thereto and various other applicable methods may be used.

[0210] Figure 12d An exemplary illustration shows pad areas PA1, PA2 comprising a groove pattern GVP consisting of two square-shaped grooves on an insulating pattern SP. The number, size / area / position of the square-shaped grooves are not limited thereto and various other applicable methods may be used.

[0211] Figures 12a to 12d The groove pattern GVP can also be achieved using the aforementioned laser LS ( Figure 10a Patterning, or using microneedles (ND) Figure 11a (to be patterned)

[0212] The present invention has been described above with reference to preferred embodiments. However, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and scope of the invention as set forth in the appended claims. Therefore, the technical scope of the present invention is not limited by the content set forth in the detailed description, but should be determined solely by the claims.

Claims

1. A display panel, characterized by, The display panel includes a pixel, a signal line electrically connected to the pixel, and a signal pad connected to the signal line, The signal pad includes: a first conductive pattern connected to a terminal portion of the signal line; a second conductive pattern including a first layer disposed on the first conductive pattern, a second layer disposed on the first layer, and a third layer disposed on the second layer; and an insulating pattern disposed between the first conductive pattern and the second conductive pattern, a recess pattern is defined on the second conductive pattern.

2. The display panel according to claim 1, wherein in a planar view, the insulating pattern is disposed inside each of the first conductive pattern and the second conductive pattern.

3. The display panel according to claim 1, wherein the insulating pattern includes a lower face adjacent to the first conductive pattern, an upper face opposite to the lower face and spaced apart from the first conductive pattern, and a side face connecting the upper face and the lower face, the second conductive pattern covers a portion of the first conductive pattern where the insulating pattern is not disposed, the upper face of the insulating pattern, and the side face of the insulating pattern.

4. The display panel according to claim 3, wherein in a planar view, the recess pattern overlaps the upper face of the insulating pattern.

5. The display panel according to claim 1, wherein the recess pattern is defined to penetrate the third layer and expose the second layer.

6. The display panel according to claim 1, wherein the second conductive pattern further includes an oxide film disposed on the third layer, the recess pattern is defined to penetrate the oxide film.

7. The display panel according to claim 1, wherein the recess pattern includes at least one groove or at least one crack.

8. The display panel according to claim 1, wherein a thickness of the second layer is thicker than each of a thickness of the first layer and a thickness of the third layer.

9. The display panel according to claim 1, wherein an electrical conductivity of the second layer is greater than each of an electrical conductivity of the first layer and an electrical conductivity of the third layer.

10. The display panel according to claim 1, wherein the insulating pattern is formed of a polymer.

Images