Chip package

Abstract

The utility model discloses a chip packaging body, which comprises a substrate, a first chip, a second chip and a switching layer, the first chip is fixed on one side of the substrate in an attached manner and is connected with the substrate, the second chip is fixed on one side, far away from the substrate, of the first chip in an attached manner and is connected with the substrate, and the switching layer is connected with the first chip in an attached manner. The switching layer is fixed and attached to one side, far away from the first chip, of the second chip; wherein the switching layer is connected with the substrate through a first connecting line, the switching layer is further connected with the second chip through a second connecting line, and a conductive circuit is arranged in the switching layer to communicate the first connecting line with the second connecting line. Through the above structure, the conditions of uncontrollable wire throwing, wire collapse or short circuit of each connecting wire can be reduced, and the electrical property and the stability of the chip packaging body can be maintained and stabilized.

Description

Technical Field

[0001] This invention applies to the technical field of chip packaging. Background Technology

[0002] Packaging technology refers to the process of placing an integrated circuit die on a substrate that serves as a support, bringing out the pins, and then fixing and packaging it into a whole.

[0003] Currently, in the dual-layer wBGA (Window Ball Grid Array) packaging structure, long wires are typically used to connect the upper die to the substrate.

[0004] However, long wires can have a certain impact on electrical properties, and long wire arcs are prone to uncontrollable wire slippage, wire collapse, and even wire-to-wire contact, which can lead to short circuits. Utility Model Content

[0005] This invention provides a chip package to solve various problems caused by long-line connections in chip packages.

[0006] To solve the above-mentioned technical problems, this utility model provides a chip package, including: a substrate, a first chip, a second chip, and an adapter layer. The first chip is attached and fixed to one side of the substrate and connected to the substrate. The second chip is attached and fixed to the side of the first chip away from the substrate. The adapter layer is fixed and attached to the side of the second chip away from the first chip. The adapter layer is connected to the substrate via a first connecting line and to the second chip via a second connecting line. Conductive lines are provided in the adapter layer to connect the first connecting line and the second connecting line.

[0007] The system comprises two transition layers; the two transition layers are spaced apart and symmetrically disposed at opposite ends on the side of the first chip away from the substrate; the transition layers, the corresponding first connection line, and the corresponding second connection line form a connection mechanism; the substrate is connected to the second chip through the two connection mechanisms respectively.

[0008] The middle region of the second chip on the side away from the substrate is exposed, and multiple first pads are provided on the middle region to connect the second connection lines.

[0009] One end of the adapter layer is located at the edge of the second chip, and the other end of the adapter layer extends toward the middle region of the second chip. In the extension direction, the length of the adapter layer is half of the difference between the length of the second chip and the length of the middle region of the second chip, and the length of the middle region ranges from 0.65 to 0.75 mm.

[0010] The number of the adapter layer is 1; in the extension direction of the adapter layer, the two ends of the adapter layer are flush with the two ends of the second chip, and the position corresponding to the middle area of ​​the adapter layer and the second chip is cut out to expose the middle area of ​​the second chip.

[0011] The chip package also includes a third connecting line, and the position on the substrate corresponding to the middle area of ​​the first chip is a cutout area; one end of the third connecting line is connected to the substrate, and the other end of the third connecting line passes through the cutout area and connects to the first chip.

[0012] The first chip has multiple second pads in the middle area to connect one end of a third connection line, and the other end of the third connection line is connected to the side of the substrate away from the first chip.

[0013] The chip package also includes a molding layer, which molds the substrate close to the first chip to mold the first chip, the second chip, the adapter layer, the first connecting line, and the second connecting line; and the molding layer also molds the middle area of ​​the side of the first chip away from the second chip to mold the third connecting line.

[0014] The transition layer includes printed circuit boards and / or wafers.

[0015] The substrate is bonded and fixed to the first chip, the first chip is bonded and fixed to the second chip through a first die bond film, and the second chip is bonded and fixed to the transition layer through a second die bond film.

[0016] The beneficial effects of this utility model are as follows: Unlike the prior art, the chip package of this utility model includes a substrate, a first chip, a second chip, and an adapter layer. The first chip is attached and fixed to one side of the substrate and connected to the substrate. The second chip is attached and fixed to the side of the first chip away from the substrate. The adapter layer is fixed and attached to the side of the second chip away from the first chip. The adapter layer is connected to the substrate via a first connecting line and to the second chip via a second connecting line. Conductive lines are provided in the adapter layer to connect the first connecting line and the second connecting line. Thus, the length of the connecting line between the substrate and the second chip can be shortened by the adapter layer, dividing it into two short lines in the middle. This significantly reduces the length of a single connecting line and reduces the occurrence of uncontrollable wire slippage, wire collapse, or short circuits in the connecting lines, which is beneficial for maintaining the electrical properties and stability of the chip package. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the chip package provided by this utility model;

[0018] Figure 2 yes Figure 1A top view of one embodiment of the chip package in the examples;

[0019] Figure 3 yes Figure 1 A bottom view of one embodiment of the chip package in the example;

[0020] Figure 4 yes Figure 1 A top view of another embodiment of the chip package in the example. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0022] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of a chip package embodiment provided by this utility model.

[0025] The chip package 100 of this embodiment includes: a substrate 130, a first chip 110, a second chip 120, and an adapter layer 160. The chip package 100 of this embodiment can be used to manufacture electronic devices with storage functions such as motherboards, flash memory, and random access memory.

[0026] The substrate 130 includes a printed circuit board, which may include a single-layer board or a multi-layer board, depending on actual needs. The substrate 130 has conductive structures to achieve connection and conduction, so as to meet relevant electrical requirements.

[0027] The first chip 110 is attached and fixed to one side of the substrate 130, and the first chip 110 is connected to the substrate 130; the second chip 120 is attached and fixed to the side of the first chip 110 away from the substrate 130.

[0028] The first chip 110 and the second chip 120 are the same type of chip, including but not limited to DDR die (Double Data Rate memory chip), LPDDR die (Low Power Double Data Rate), GDDR die (Graphics Double Data Rate), and HBM die (High Bandwidth Memory), etc. The signal lead-out contacts of the first chip 110 and the second chip 120 are both located in their middle area.

[0029] The first chip 110 and the second chip 120 are vertically stacked. The first chip 110 and the second chip 120 may or may not have a direct connection through their bonding surfaces, depending on the requirements of the chip package 100.

[0030] The adapter layer 160 is fixed and attached to the side of the second chip 120 away from the first chip 110; wherein, the adapter layer 160 is connected to the substrate 130 via a first connecting line 140, and the adapter layer 160 is also connected to the second chip 120 via a second connecting line 150. Conductive lines (not shown) are provided in the adapter layer 160 to connect the first connecting line 140 and the second connecting line 150.

[0031] The substrate 130 is connected to the second chip 120 sequentially via a first connecting line 140, an adapter layer 160, and a second connecting line 150. In this embodiment, the adapter layer 160 shortens the length of the connecting line between the substrate 130 and the second chip 120, dividing it into two short lines in the middle. This significantly reduces the length of a single connecting line, minimizing the occurrence of uncontrollable wire slippage, wire collapse, or short circuits, and helps maintain the stable electrical properties of the chip package 100.

[0032] Through the above steps, the chip package of this embodiment includes a substrate, a first chip, a second chip, and an adapter layer. The first chip is bonded and fixed to one side of the substrate and connected to the substrate. The second chip is bonded and fixed to the side of the first chip away from the substrate. The adapter layer is fixed and bonded to the side of the second chip away from the first chip. The adapter layer is connected to the substrate via a first connecting line and to the second chip via a second connecting line. Conductive lines are provided in the adapter layer to connect the first connecting line and the second connecting line. By setting the adapter layer, the length of the connecting line between the substrate and the second chip can be shortened and divided into two short lines in the middle, thereby significantly reducing the length of a single connecting line, improving the stability of a single connecting line, reducing the occurrence of uncontrollable wire slippage, wire collapse, or short circuits, which is beneficial to maintaining the electrical properties and stability of the chip package and extending the service life of the chip package.

[0033] Please see Figure 2 , Figure 2 yes Figure 1 This is a top view of one embodiment of the chip package. The molding compound is hidden in this diagram for easier viewing.

[0034] In some embodiments, the number of transition layers 160 is two. The two transition layers 160 are spaced apart and symmetrically disposed at opposite ends on the side of the first chip 110 away from the substrate.

[0035] The adapter layer 160, the corresponding first connection line 140, and the corresponding second connection line 150 form a connection mechanism 166; the substrate 130 is connected to the second chip 120 through the two connection mechanisms 166 respectively.

[0036] Specifically, the opposite ends of the substrate 130 near the second chip 120 can be connected to corresponding connection mechanisms 166, and then the second chip 120 is connected through the connection mechanisms 166. This double-sided connection increases the connection space between the substrate 130 and the second chip 120, so as to meet the multiple connection requirements between the substrate 130 and the second chip 120. This ensures that each connection requirement has sufficient operating space during connection and sufficient floor space after connection, thus guaranteeing the stability of the connection.

[0037] In this embodiment, the first connecting line 140 and the second connecting line 150 are collective terms for multiple connecting lines. In practice, the first connecting line 140 and the second connecting line 150 may each include multiple connecting lines. The transition layer 160 is provided with multiple conductive lines 161, the opposite ends of which are connected to the corresponding connecting lines in the first connecting line 140 and the second connecting line 150, respectively, to achieve connectivity between the first connecting line 140 and the second connecting line 150. In a specific application scenario, the conductive structure in the connecting mechanism 166, composed of the first connecting line 140, conductive lines 161, and second connecting lines 150, consists of multiple independent lines, including but not limited to 10, 25, 40, 50, 88, or 100 lines, etc., specifically set according to actual needs.

[0038] In some embodiments, the middle region 122 of the second chip 120 on the side away from the substrate 130 is exposed, that is, the transition layer 160 does not cover the middle region 122, so as to expose the middle region 122. And a plurality of first pads 121 are provided on the middle region 122 to connect the second connection line 150.

[0039] In a specific application scenario, 100 first pads 121 can be provided on the middle area 122 of the second chip 120, of which 50 first pads 121 are connected to a corresponding connection mechanism 166, and the other 50 first pads 121 are connected to another corresponding connection mechanism 166.

[0040] In a specific application scenario, on the side of the transition layer 160 away from the second chip 120, a plurality of third pads 163 are provided at the end near the middle region 122, and a plurality of fourth pads 164 are provided at the end away from the middle region 122. A plurality of fifth pads 131 are provided on one side of the substrate 130, and the plurality of fifth pads 131 are respectively located at opposite ends of the second chip 120.

[0041] Specifically, the substrate 130 is sequentially connected to the first pad 121 of the middle region 122 of the second chip 120 via a plurality of fifth pads 131, a plurality of first connection lines 140, a plurality of fourth pads 164, an adapter layer 160, a plurality of third pads 163, and a second connection line 150.

[0042] The above-mentioned pad routing settings are simple to operate and do not require any changes to the original manufacturing process of the chip package 100, so as to ensure the manufacturing efficiency of the chip package 100 when the adapter layer 160 replaces the connecting lines.

[0043] Two transition layers 160 are symmetrically arranged at opposite ends of the second chip 120. The two transition layers 160 can have identical structures, including two sets of conductive lines 161, thus enabling corresponding connections regardless of whether the transition layer 160 is located on the left or right side. In this configuration, during the routing of the second chip 120, the connecting lines on the two transition layers 160 can be routed simultaneously without adjusting the routing equipment. One setup completes the routing of both connection mechanisms 166, improving routing efficiency and the fabrication efficiency of the chip package 100.

[0044] In some embodiments, one end of the adapter layer 160 is located at the edge of the second chip 120, and the other end of the adapter layer 160 extends towards the middle region 122 of the second chip 120. In the extension direction x, the length S of the adapter layer 160 is half the difference between the length H of the second chip 120 and the length L of the middle region 122 of the second chip 120, i.e., S = (HL) / 2. The length L of the middle region 122 ranges from 0.65 to 0.75 mm. This length L of the middle region 122 is the space required for the routing of the first pad 121. However, the length H of the second chip 120 is not fixed; different models of the second chip 120 have different lengths. Therefore, in embodiments with two adapter layers 160, the length S of the adapter layer 160 can be set accordingly based on the length H of the second chip 120, only needing to retain the length L of the middle region 122.

[0045] With the length setting of this adapter layer 160, the length of the connecting lines can be shortened to the maximum extent, further reducing the occurrence of uncontrollable wire slippage, wire collapse or short circuits in each connecting line, which is conducive to maintaining the electrical properties and stability of the stable chip package.

[0046] Please read back Figure 1 The chip package 100 also includes a third connecting line 170, and the position on the substrate 130 corresponding to the middle area of ​​the first chip 110 is a cutout area 133.

[0047] One end of the third connecting line 170 is connected to the substrate 130, and the other end of the third connecting line 170 passes through the cutout area 133 and is connected to the first chip 110.

[0048] Please see Figure 3 , Figure 3 yes Figure 1 This is a bottom view of one embodiment of the chip package. The molding compound is hidden in this diagram for easier viewing.

[0049] In some embodiments, a plurality of second pads 111 are provided on the middle region of the first chip 110 to connect to the third connection line 170, and one end of the third connection line 170 is connected to the side of the substrate 130 away from the first chip 110, specifically it can be connected to the sixth pad 136 provided on the substrate 130.

[0050] That is, the first chip 110 is connected to the substrate 130 through a connection structure consisting of the second pad 111, the third connection line 170, and the sixth pad 136. The number of the above connection structures is set based on actual connection requirements and is not limited here, for example: 10, 15, 20, 25, or 40, etc.

[0051] Please read back Figure 1 In some embodiments, the chip package 100 further includes a molding layer 190, which molds the substrate 130 on the side close to the first chip 110 to mold the first chip 110, the second chip 120, the adapter layer 160, the first connecting line 140, and the second connecting line 150; and the molding layer 190 also molds the middle area of ​​the side of the first chip 110 away from the second chip 120 to mold the third connecting line 170, that is, double-sided molding, molding all the chips and connecting lines.

[0052] In some embodiments, the interposer layer 160 includes a printed circuit board and / or a wafer type interposer. Both the printed circuit board with built-in conductive lines and the wafer type interposer can be pre-prepared. When fixing the interposer layer 160, the printed circuit board or wafer type interposer can be directly mounted, thereby effectively increasing the stability of the WB (bonding) operation on the wafer (i.e., chip) during the dual-layer wBGA packaging process, eliminating the need for other processing operations on the wafer surface and protecting the structural stability of the wafer surface.

[0053] Furthermore, the printed circuit board and wafer can serve as the substrate surface, directly contacting the WB stage (bonding platform), so that the chip package 100 can be flipped during the fabrication process.

[0054] In some embodiments, the substrate 130 is bonded to the first chip 110, the first chip 110 is bonded to the second chip 120 via a first die bond film 151 (DAF), and the second chip 120 is bonded to the transition layer 160 via a second die bond film 152. This bonding method is simple to operate, requires no additional processing steps, and does not damage the chip surface, thus improving the structural stability of the chip.

[0055] Please see Figure 4 , Figure 4 yes Figure 1This is a top view of another embodiment of the chip package in the examples. The molding compound is hidden in this diagram for easier viewing.

[0056] In this embodiment, there is one adapter layer 260. In the extension direction x of the adapter layer 260, the two ends of the adapter layer 260 are flush with the two ends of the second chip 220, and the position corresponding to the middle area of ​​the adapter layer 260 and the second chip 220 is hollowed out to expose the middle area of ​​the second chip 220.

[0057] That is, the entire adapter layer 260 covers the second chip 220, and the middle area of ​​the second chip 220 is exposed by hollowing out the entire adapter layer 260 for connection. In this embodiment, only one adapter layer 260 needs to be installed, which speeds up the installation process. The conductive lines inside the adapter layer 260 can be pre-prepared based on actual connection requirements.

[0058] In this embodiment, the positions and connections of the other structures are the same as in the previous embodiments. Please refer to the previous text for further details.

[0059] Through the above steps, this embodiment shortens the length of the connection line between the substrate and the second chip by setting an adapter layer, dividing it into two short lines in the middle. This significantly reduces the length of a single connection line, minimizing uncontrollable wire slippage, wire collapse, or short circuits, thus helping to maintain the electrical properties and stability of the chip package. Furthermore, this embodiment adds a substrate-type or wafer-type adapter layer on the second chip, which can act as a protective surface. It also enhances the first chip's wire bonding (WB) process, achieving effective output and ensuring operational stability. Moreover, it transforms the original long-line operation method into a risk-controlled general packaging WB mode. This improves wire bonding stability and reduces the impact on electrical properties.

[0060] The above are merely embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A chip package, characterized by The chip package comprises: a substrate; a first chip fixedly attached to one side of the substrate, the first chip being connected to the substrate; a second chip fixedly attached to a side of the first chip away from the substrate; an adapter layer fixedly and attachably arranged on a side of the second chip away from the first chip; wherein the adapter layer is connected to the substrate through a first connecting line, the adapter layer is also connected to the second chip through a second connecting line, and the adapter layer is provided with a conductive circuit to connect the first connecting line and the second connecting line.

2. The chip package of claim 1, wherein, The number of the adapter layers is two. The two adapter layers are symmetrically arranged at opposite ends of a side of the first chip away from the substrate. The adapter layer, the corresponding first connecting line and the corresponding second connecting line form a connecting mechanism, and the substrate is connected to the second chip through two connecting mechanisms respectively.

3. The chip package of claim 2, wherein, A middle region of a side of the second chip away from the substrate is exposed, and a plurality of first pads are arranged on the middle region to correspondingly connect the second connecting line.

4. The chip package of claim 2 or 3, wherein, One end of the adapter layer is located at an edge of the second chip, and the other end of the adapter layer extends to a middle region of the second chip; wherein, in the extending direction, the length of the adapter layer is half of the difference between the length of the second chip and the length of the middle region of the second chip, and the length of the middle region ranges from 0.65 to 0.75 mm.

5. The chip package of claim 1, wherein, The number of the adapter layers is one; in the extending direction of the adapter layer, the opposite ends of the adapter layer are flush with the corresponding opposite ends of the second chip, and the adapter layer is hollowed out at a position corresponding to the middle region of the second chip to expose the middle region of the second chip.

6. The chip package of claim 1, wherein, The chip package further comprises a third connecting line, and a position on the substrate corresponding to a middle region of the first chip is a hollow region. One end of the third connecting line is connected to the substrate, and the other end of the third connecting line is connected to the first chip through the hollow region.

7. The chip package of claim 6, wherein, A plurality of second pads are arranged on the middle region of the first chip to correspondingly connect one end of the third connecting line, and the other end of the third connecting line is connected to a side of the substrate away from the first chip.

8. The chip package of claim 6, wherein, The chip package further comprises a plastic encapsulation layer, which encapsulates a side of the substrate close to the first chip to encapsulate the first chip, the second chip, the adapter layer, the first connecting line and the second connecting line. The plastic encapsulation layer also encapsulates a middle region of a side of the first chip away from the second chip to encapsulate the third connecting line.

9. The chip package of claim 1, wherein, The adapter layer comprises a printed circuit board and / or a wafer board.

10. The chip package of claim 1, wherein, The substrate and the first chip are adhesively fixed, the first chip and the second chip are adhesively fixed through a first die-bonding film, and the second chip and the adapter layer are adhesively fixed through a second die-bonding film.

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