Microelectronic device

Abstract

The utility model relates to a microelectronic device. A first layer of a resin compatible with direct laser structuring (LDS) is formed on the substrate and encapsulates the first integrated circuit. The substrate includes a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal covered by the first layer. A first via is formed using LDS, the first via passing through the first layer and forming an electrical connection with the second connection terminal. A second integrated circuit is mounted over the first integrated circuit. A second layer of a resin compatible with the LDS is formed to encapsulate a second integrated circuit. A second via is formed using LDS, the second via passing through the second layer and forming an electrical connection with the first via.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority of French application No. 2400206, filed on January 10, 2024, the contents of which are incorporated herein in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates generally to an apparatus comprising a plurality of integrated circuits. BACKGROUND

[0004] In microelectronics, the trend is to move towards miniaturization to consume less raw material and reduce production costs, or to be able to add new functionalities to products without increasing their size. With this in mind, it is advantageous to stack integrated circuits on the same substrate, so that they occupy less space. Electrical connections between first integrated circuits mounted on a substrate can be formed by direct connections between metal pads, and wire bonding provides a solution for forming electrical connections between second integrated circuits mounted on the first integrated circuits. However, the use of wires requires a significant space to be left around the integrated circuits to be connected.

[0005] There is therefore a need for a method of assembling a plurality of circuits stacked on the same substrate one on top of the other, thereby making it possible to reduce the dimensions of the final apparatus. SUMMARY

[0006] One embodiment provides a microelectronic apparatus comprising: a substrate; a first integrated circuit mounted on the substrate; a first layer of resin compatible with direct laser structuring (LDS) deposited on the substrate and having the first integrated circuit incorporated therein (e.g., encapsulated); in the substrate, a first connection terminal coupled to the first integrated circuit and a second connection terminal coupled to the first connection terminal and covered by the first layer; a first via formed by the LDS, the first via passing through the first layer and making electrical contact with the second connection terminal; a second integrated circuit mounted on the first integrated circuit; a second layer of resin compatible with the LDS, the second integrated circuit incorporated (e.g., encapsulated) in the second layer; and a second via formed by the LDS, the second via passing through the second layer and making electrical contact with the first via.

[0007] In one embodiment, the microelectronic apparatus further comprises an LDS metal track electrically coupling the second LDS via to the second integrated circuit.

[0008] In one embodiment, the second LDS via is laterally offset from the first LDS via and connected thereto by the LDS metal track.

[0009] In one embodiment, the first integrated circuit and the second integrated circuit each have a first surface and a second surface opposite the first surface, the first surface comprising a metallization comprising one or more connection terminals, and wherein the first integrated circuit and the second integrated circuit are mounted with their second surfaces facing each other.

[0010] In one embodiment, the microelectronic device further comprises a device on the second layer, wherein the device is electrically coupled to the second via.

[0011] In one embodiment, the microelectronic device further comprises a third layer made of resin, the third layer being on the second layer and covering the second LDS via. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above features and advantages and other features and advantages will be described in detail in the rest of the disclosure of specific embodiments given as an illustration and not limitation, with reference to the drawings, in which:

[0013] Figure 1 is a cross-sectional view of a device comprising two integrated circuits connected to each other and to the same substrate according to an embodiment of the disclosure;

[0014] Figures 2A-2I is a cross-sectional view of a method of manufacturing Figure 1 a device according to an embodiment of the disclosure;

[0015] Figure 3A and Figure 3B is a cross-sectional view of successive steps of a method of manufacturing Figure 1 a device that can be applied to; and

[0016] Figure 4A and Figure 4B shows partial cross-sectional views of successive steps of a panel embedded package (PEP) method of integrated circuits. DETAILED DESCRIPTION

[0017] Like features are denoted with like reference signs in the various figures. In particular, structural and / or functional features common to the various embodiments can have the same reference signs and can deploy the same structural, dimensional and material properties.

[0018] For the sake of clarity, only the steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the steps of manufacturing the laminated substrate and the integrated circuits are common and are not described in detail.

[0019] When referring to two elements connected together, this means a direct connection, without any intermediate element other than a conductor, unless otherwise indicated, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements.

[0020] In the following description, when referring to absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right" or to relative position qualifiers such as "top", "bottom", "upper", "lower" or to orientation qualifiers such as "horizontal", "vertical", these refer to the orientation of the figures, unless otherwise indicated.

[0021] The expressions "about", "approximately", "substantially" and "… around" mean plus or minus 10%, preferably plus or minus 5%, unless otherwise indicated.

[0022] Figure 1 is a cross-sectional view of a device 100 according to an embodiment of the disclosure, the device 100 comprising two integrated circuits 101, 102 connected to each other and to a same substrate 104.

[0023] In the example of Figure 1 The two integrated circuits 101 and 102 are mounted one on top of the other by means of a bonding layer 126 and encapsulated in a resin 106. The integrated circuit 101 is mounted on the substrate 104, for example, by means of a dielectric layer 105. The integrated circuits 101 and 102 are electrically connected to each other and to the substrate 104 by means of a set of vias 112, 117, 118, 112', 117', 118' and a set of metal tracks 114, 119, 124, 114', 119', 124' formed in the resin 106, in the substrate 104 and / or in the dielectric layer 105.

[0024] The substrate 104 and the dielectric layer 105 are made of, for example, Ajinomoto Build-up Film (ABF) or of, for example, a polymer. The substrate 104 has a thickness equal to, for example, at least 50 μιη. The dielectric layer 105 has a thickness equal to, for example, at least 10 μιη.

[0025] The integrated circuits 101 and 102 each have a metallization comprising one or more connection terminals 123, 130, 123', 130' on a first surface of each of the integrated circuits 101, 102 and, on a second surface opposite the first surface, for example, no metallization or connection terminals. The second integrated circuit 102 is mounted on the first integrated circuit 101 so that the second surfaces of the integrated circuits 101 and 102 face each other and so that the connection terminals present on their first surfaces remain accessible.

[0026] The connection terminals 123 of the integrated circuit 101 are located, for example, on its lower surface and are connected, for example, by one or more metal tracks 124 to the connection terminals 125 on the upper surface of the substrate 104. The metal tracks 124 are made, for example, of copper, gold, tin, silver or an alloy of several of these materials.

[0027] In certain embodiments, the connection terminals 123 and 125 are also connected by the metal tracks 124 to connection terminals 128, thereby enabling coupling of the device 100 to an external electronic device (not shown). The connection terminals 128 are present, for example, on the lower surface of the substrate 104.

[0028] The connection terminals 130 of the integrated circuit 102 are located, for example, on its upper surface. The connection terminals 125 and 130 are connected to each other by the via 112 and the via 118. In the example shown in Figure 1 The via 112 has, for example, a height at least equal to the sum of the height of the first integrated circuit 101 and the height of the dielectric layer 105. In general, the via 112 has a height at least equal to the distance separating the connection terminals 125 from the upper surface of the integrated circuit 101. In the example shown in Figure 1 The via 118 has, for example, a height at least equal to the sum of the height of the second integrated circuit 102 and the height of the bonding layer 126. In general, the via 118 has a height at least equal to the distance separating the via 112 from the upper surface of the integrated circuit 102.

[0029] According to an embodiment, the vias 112 and 118 are laterally offset, i.e. offset from each other in a direction parallel to the plane of the substrate 104, by a distance δ. The vias 112 and 118 are connected to each other, for example, by a metal track 114.

[0030] The via 117 is connected, on the one hand, to the connection terminals 130 of the integrated circuit 102 and, on the other hand, to the via 118 by one or more metal tracks 119.

[0031] The resin 106 used to encapsulate the integrated circuit 101 is, for example, a specific resin compatible with direct laser structuring (LDS), this compatibility being reflected in the fact that the resin comprises additives or particles that can be activated by laser treatment at the location of the desired vias and tracks. The thickness of the resin layer 106 is, for example, at least equal to the sum of the heights of the vias 112 and 118. In the example shown in Figure 1 The thickness of the resin layer 106 is sufficient, for example, to cover the metal tracks 119.

[0032] In the example shown in Figure 1In the example, a second set of connection terminals 123', 125', 128', and 130' are shown, along with a second set of through holes 112', 117', and 118', and metal rails 114', 119', and 124', which are similar to those described above and will not be described in detail again. In other embodiments, one or more sets of connection terminals, through holes, and metal rails may be provided.

[0033] Figures 2A-2I Manufacturing according to embodiments of the present disclosure Figure 1 A cross-sectional view of the successive steps of the method of the apparatus 100.

[0034] Figures 2A-2I Some components and Figure 1 The components are the same, and these components are represented by the same reference numerals and will not be described in detail again.

[0035] Below is Figures 2A-2I The description only describes the formation of metal tracks 114 and 119 and through holes 112, 117 and 118. For example, the same steps are used to form metal tracks 114' and 119' and through holes 112', 117' and 118'.

[0036] Figure 2A An example of device 200 is shown for manufacturing Figure 1 The method of device 100 provides a starting point. (And...) Figure 1 Compared to device 100, device 200 does not include a second integrated circuit 102 or through holes 112, 118 for connecting circuits 101 and 102 to each other and to substrate 104.

[0037] Figure 2A The device 200 is, for example, based on Figure 4A and Figure 4B The manufacturing steps of the panel embedded packaging (PEP) method detailed in the article are obtained.

[0038] exist Figure 2A In one example, device 200 includes a first integrated circuit 101 encapsulated in a resin layer 106A, the first integrated circuit 101 being flip-chip oriented so that the front-side connection terminals 123, 123' face and are connected to a substrate 104. The height h1 of the resin layer 106A is, for example, sufficient to cover the integrated circuit 101 and the connection terminals 125.

[0039] Figure 2B This illustrates the optional step following the thinning of resin layer 106A. Figure 2A The apparatus. According to an embodiment, the thickness of the resin layer is reduced to expose the back side of the integrated circuit 101. This step is useful, for example, when it is intended to bond a second integrated circuit 102 to the first integrated circuit 101.

[0040] exist Figure 2B In the example, the final height h1' of the resin layer 106A' is at least equal to the sum of the height d1 of the first integrated circuit 101 and the height d5 of the dielectric layer 105. In general, the height h1' is, for example, at least equal to the distance separating the connection terminal 125 from the upper surface of the integrated circuit 101.

[0041] In the following Figures 2C-2I The description states that these steps are applicable to... Figure 2B The device obtained at the step. However, in the omitted Figure 2B In the case of the steps described, those skilled in the art will understand how to adjust Figures 2C-2I The steps in the process.

[0042] Figure 2C This shows the result after the laser ablation (or drilling) step. Figure 2B The device. The resin layer 106A' is perforated by a laser beam to partially expose the connection terminals 125 present on the surface of the substrate 104. The perforation 110 performed corresponds to the location of the future metal via.

[0043] During the laser ablation step, the laser beam used for perforating resin 106A' interacts with the LDS additive present in resin 106A' and locally activates the periphery of the perforation 110.

[0044] Additionally, during this step, for example, a laser beam is used to irradiate the upper surface of resin 106A', i.e., the surface furthest from substrate 104, at the location where the metal tracks 114 will be formed, in order to locally activate them.

[0045] Figure 2D The illustration shows, for example, after an autocatalytic growth or electroless plating step. Figure 2C The apparatus. During this method, metal is deposited on the surface of resin 106A', which has been previously activated by a laser beam, without the use of an electric current. The activation of the resin by the laser beam creates a seed at the location where the resin surface is irradiated. For example, through-hole 112 is... Figure 2C The perforation 110 is created from the exposed connection terminal 125 and the periphery of the previously activated perforation 110. The metal track 114 is created, for example, on the previously activated portion of the surface of the resin 106A'.

[0046] Although Figure 2D An example of electroless plating to form metal tracks 114 and through-holes 112 is shown, but electroplating methods can also be used. In this case, temporary metal tracks (not shown) are created, for example, on the surface of the resin layer 106A' to allow current to flow for such electroplating.

[0047] Through hole 112 is made of, for example, copper, gold, tin, silver or an alloy of these materials.

[0048] The above text combined Figure 2C and Figure 2D The described steps correspond to the implementation methods of the LDS method.

[0049] Figure 2E The diagram illustrates the process after the second integrated circuit 102 is bonded to the first integrated circuit 101. Figure 2D The device. For example, regarding... Figure 1 As described, integrated circuits 101 and 102 each include a first surface (or front side) and a second surface (or back side) opposite to the first surface. The first surface (or front side) includes a metallization containing one or more connection terminals, while the second surface (or back side), for example, does not include a metallization or connection terminals. A second integrated circuit 102 is, for example, joined such that the second surfaces of the two integrated circuits 101 and 102 are in contact, and the connection terminals of the second integrated circuit are located on its upper surface, such that the connection terminals remain accessible after joining. The two integrated circuits are joined, for example, using an epoxy-based adhesive polymerized during a heating step.

[0050] According to the embodiment, in omitting Figure 2B In the case of thinning steps or partial thinning, there is a resin layer between integrated circuits 101 and 102.

[0051] Figure 2F This shows the process after depositing a second layer of 106B resin compatible with LDS. Figure 2E The device.

[0052] The deposition of resin layer 106B is performed, for example, by compression molding, where the resin is deposited, for example, on... Figure 2E It is pressed into the mold on the surface of the device.

[0053] The thickness h2 of layer 106B is, for example, at least equal to the height of the future via 118, that is, at least sufficient to cover the integrated circuit 102.

[0054] Figure 2G This illustrates the optional step following the thinning of resin layer 106B. Figure 2F The device.

[0055] As for height h2, Figure 2G In the example shown, the final height h2' of the resin layer 106B' is at least equal to the sum of the height d2 of the second integrated circuit 102 and the height d26 of the bonding layer 126. In general, the height h2' is, for example, greater than the distance by which the via 112 is separated from the upper surface of the integrated circuit 102 to cover the integrated circuit 102.

[0056] In the followingFigures 2H-2I The description states that these steps are applicable to Figure 2G The device obtained at the step. However, in the omitted Figure 2G In the case of the steps described, those skilled in the art will understand how to adjust Figures 2H-2I The steps in the process.

[0057] Figure 2H The image shows the result after a laser ablation (or drilling) step. Figure 2G The apparatus. A resin layer 106B is perforated by a laser beam to form perforations 116 and, for example, 115, corresponding to the locations of future vias. Perforation 116 exposes at least a portion of a metal track 114 coupled to at least one connection terminal 123 of integrated circuit 101 and at least one connection terminal 128 of substrate 104. Perforation 115, for example, exposes a connection terminal 130 of integrated circuit 102.

[0058] After the laser ablation step, the periphery of the perforations 115 and 116 is activated.

[0059] Additionally, during this step, the locations on the upper surface of resin 106B' where the metal tracks 119 will be formed are illuminated, for example, by a laser beam to locally activate them.

[0060] Figure 2I This illustrates, for example, after the autocatalytic growth step. Figure 2H The device. During this method, in Figure 2H A through-hole 118 is created in the perforation 116, starting from the exposed portion of the metal track 114 and from the previously activated periphery of the perforation 116. For example, in Figure 2H Through-holes 117 are created in through-holes 115, starting from the exposed connection terminals of integrated circuit 102 and from the previously activated periphery of through-holes 115. For example, metal tracks 119 are created on the surface of resin 106B on the previously activated portion. For example, through-holes 118, 117 and tracks 119 are made of copper, gold, tin, silver or an alloy of various of these materials.

[0061] The above and Figure 2H and Figure 2I The relevant steps correspond to the implementation methods of the LDS method. The LDS method is only possible on compatible resin layers.

[0062] According to an embodiment, the through-holes formed by autocatalytic growth in steps 2C and 2H are created by forming a metal layer on the walls of the through-holes 110, 116, and 115. The through-holes 112, 118, and 117 thus created form cones, for example, partially filled at their centers. The through-holes 112 and 118 are offset from each other by a distance δ and connected by a metal track 114 to ensure good connection.

[0063] Although Figure 2I An example of electroless plating to form metal tracks 119 and through-holes 114 is shown, but electroplating methods can also be used. In this case, for example, temporary metal tracks (not shown) are created on the surface of the resin layer 106B' to allow current to flow for this electroplating.

[0064] exist Figure 2I After the step (not shown) of depositing a third resin layer on the surface of the device, a result is obtained. Figure 1 The device 100. An assembly formed of resin layers 106A', 106B' and a third resin layer and... Figure 1 The resin layer 106 corresponds to this.

[0065] Figure 3A and Figure 3B It can be applied to Figure 1 A cross-sectional view of the successive steps of the manufacturing method of the device.

[0066] Figure 3A and Figure 3B Some components and Figure 1 and / or Figures 2A-2I The components are the same, and these components are represented by the same reference numerals and will not be described in detail again.

[0067] Figure 3A The optional step of connecting the surface mount device (SMD) 120 to the metal tracks 119 and 119' is shown. Figure 2I The device. According to an embodiment, the surface mount component 120 is, for example, added to... Figure 1 The device 100 is integrated during the packaging process. Component 120 is, for example, soldered or bonded with conductive adhesive between tracks 119 and 119'.

[0068] Figure 3B This illustrates the optional step following the deposition of resin layer 106C to encapsulate component 120. Figure 3A The device. For example, a resin incompatible with LDS is used for this layer. The height of the resin layer 106C is, for example, at least as high as the component 120, and, for example, higher than the component 120 to cover the component 120 in order to protect the component 120 and insulate it.

[0069] according to Figure 3B In alternative embodiments of the shown embodiments, a series of layers, including nickel and / or gold layers, are deposited on the surface of the metal track 119 by electroplating to make it corrosion resistant, and the resin layer 106C is not deposited.

[0070] exist Figure 1 , Figures 2A-2I as well as Figure 3A andFigure 3B In the example, dielectric layer 105 is present between substrate 104 and chip 101. However, in other embodiments, layer 105 is omitted, and integrated circuit 101 is directly mounted on substrate 104. Those skilled in the art will understand how these processes can be adapted.

[0071] During the method described in this way, two series of through-holes 112 and 118 are created sequentially. The advantage of creating these two series of through-holes instead of a single through-hole is that the height of each through-hole is reduced, resulting in a more compact final device. In practice, the aspect ratio of through-holes is generally limited. For example, in the case of through-holes formed by LDS, the aspect ratio is limited to 1:1, meaning the height cannot exceed the diameter of the through-hole. Therefore, creating two successive through-holes occupies less surface area than creating a single, taller, and therefore wider through-hole. For example, when it is desired to form a 300 µm high through-hole, if the aspect ratio is limited to 1, it is possible to create two through-holes, each 150 µm high with a maximum diameter of 150 µm, one above the other, for a total height of 300 µm and a maximum diameter of 150 µm. In contrast, a single 300 µm high through-hole would require a maximum diameter of 300 µm. This effectively reduces the surface area required for the through-hole.

[0072] Figure 4A and Figure 4B A partial cross-sectional view of the successive steps of the panel embedded packaging (PEP) method for integrated circuit 101 is shown.

[0073] Figure 4A and Figure 4B Components and Figure 1 and / or Figures 2A-2I and / or Figures 3A-3B The components are the same, and are represented by the same reference numerals and will not be described in detail again.

[0074] PEP packaging technology is used, for example, to obtain Figure 2A Device 200.

[0075] In step A, a substrate (e.g., a wafer 301 of semiconductor material (e.g., silicon) including an integrated circuit (not shown at step A) is covered by a dielectric layer 105. The dielectric layer 105 is, for example, ABF or a polymer film.

[0076] In step B, after depositing the dielectric layer 105, the layer 105 is partially opened by, for example, laser and / or plasma etching to create a via, such as that present on wafer 301. Figure 1 , Figures 2A-2I and Figures 3A-3B The connection terminal 123 of the integrated circuit 101 is located there. A through-hole will be used to form a conductive via.

[0077] In step C, the wafer 301 from step B is then subjected to, for example, grinding to remove substrate thickness that is not useful for the operation of the integrated circuit, and dicing to separate the integrated circuit 101 into individual electronic chips.

[0078] In step D, following step C, the electronic chip is flipped and repositioned on a support plate made of, for example, stainless steel, such that the dielectric layer 105 is bonded to the plate through a temporary bonding film 302.

[0079] In step E, following step D, the chips are, for example, separated, with a spacing between them sufficient to create, for example, [the following is a separate process]. Figure 2D A future through-hole 112 is formed. The support plate is, for example, rectangular and larger than the silicon wafer, for example, 700 mm × 700 mm. A resin layer 106A is deposited to encapsulate the chip.

[0080] In step F, after depositing the resin layer 106A, it is thinned, for example, by abrasive polishing.

[0081] In step G, following step F, the chip encapsulated in resin 106A is separated from the support plate, flipped over to expose the dielectric layer 105, and its opposite surface is bonded to the support plate through a temporary bonding film 304. For example, automated optical inspection (AOI) is performed to detect defects on the chip.

[0082] In step H, following step G, metal particles 306, such as copper and titanium, are deposited on the surface of the packaged chip. These particles will serve as seeds for subsequent autocatalytic or electrocatalytic growth steps.

[0083] In step I, after depositing metal particles 306, a photoresist layer 308 is deposited, for example.

[0084] In step J, after depositing layer 308, it is exposed and developed using laser direct imaging (LDI) to create openings in the dielectric layer. Using a laser instead of a mask for this photolithography step allows for adjustment of the illumination pattern of the dielectric layer. The position of the electronic chip on the support plate can vary from plate to plate, and LDI imaging makes it possible to accommodate these variations.

[0085] In step K, after the opening is formed, a metal through-hole and track 124 are formed, for example, by electroplating.

[0086] In step L, after forming the metal track 124, for example, a photoresist layer 310 is deposited.

[0087] In step M, the LDI-exposed layer 310 is developed to create openings in the photoresist layer 310.

[0088] In step N, following step M, a metal track 128, for example made of copper, is created on the metal track deposited in step K, for example by electroplating according to the opening in layer 310. Track 128 forms, for example, a connection terminal.

[0089] Step O following step N, for example, involves etching away layers 308 and 310 and the precursor particles 306 remaining beneath layers 308 and 310.

[0090] In step P, after the etching step, a dielectric layer 104 is deposited to encapsulate the metal track and via.

[0091] In step Q, after depositing the dielectric layer 104, it is thinned, for example, to expose the metal track 328, and successive layers, including, for example, nickel and / or gold layers, are deposited on the surface of the metal track 328 by electroplating to make it corrosion resistant. The structure including the two integrated circuits 101 is separated from the support plate.

[0092] By combination Figure 4A and Figure 4B The detailed steps A to Q describe methods, for example, for packaging integrated circuit 101 and obtaining... Figure 2A The apparatus 200. Then, the resin used for coating the integrated circuit is, for example, a specific resin compatible with LDS. Figure 4A and Figure 4B In the example, a structure comprising two integrated circuits 101 is formed. In other embodiments, a structure comprising one or more integrated circuits 101 arranged side-by-side can be formed using the same method. Figures 2A-2I The described method is applied simultaneously to all integrated circuits 101, and multiple individual devices 100 are obtained by means of a separate structure, such as by laser cutting or mechanical sawing.

[0093] As a variant, after step Q, in step R, the electronic chip is separated into individual electronic chips, for example by laser cutting or mechanical sawing. In this case, regarding Figures 2A-2I The described method is applied individually to each electronic chip.

[0094] An embodiment provides a method comprising: forming a first layer of resin compatible with direct laser structuring (LDS) on a substrate, wherein a first integrated circuit mounted on the substrate is incorporated (e.g., encapsulated) in the first layer, the substrate including a first connection terminal coupled to the first integrated circuit and a second connection terminal coupled to the first connection terminal and covered by the first layer; forming a first via through LDS, the first via penetrating the first layer and forming an electrical contact with the second connection terminal; mounting a second integrated circuit on the first integrated circuit; forming a second layer of resin compatible with LDS on the substrate, wherein the second integrated circuit is incorporated (e.g., encapsulated) in the second layer; and forming a second via through LDS, the second via penetrating the second layer and forming an electrical contact with the first via.

[0095] According to an embodiment, forming the first layer includes depositing an initial resin layer and thinning the initial resin layer to obtain the first layer.

[0096] According to an embodiment, forming the second layer includes depositing an initial resin layer and thinning the initial resin layer to obtain the second layer.

[0097] According to an embodiment, the method further includes adding a device on a second layer that is coupled to a second via.

[0098] According to an embodiment, the method further includes depositing a third layer made of resin on the second layer.

[0099] According to an embodiment, the first integrated circuit and the second integrated circuit each have a first surface and a second surface opposite to the first surface. The first surface includes a metallization portion containing one or more connection terminals. The first integrated circuit and the second integrated circuit are mounted with their second surfaces facing each other.

[0100] According to the embodiments, the through holes are formed by autocatalytic growth or electroless plating.

[0101] According to an embodiment, the second through hole is laterally offset relative to the first through hole.

[0102] According to an embodiment, the height of the first layer is at least equal to the distance that separates the second connection terminal from the upper surface of the first integrated circuit.

[0103] According to an embodiment, the height of the second layer is at least equal to the distance that separates the first via from the upper surface of the second integrated circuit.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, Figures 2A-2IThe method described herein is illustrated for a single device 100, but the method can be performed simultaneously for multiple devices bonded to a common substrate and separated at the end of the method. The method is detailed for two integrated circuits 101 and 102, but can be extended to a stack of at least three integrated circuits, in which case, for example, a set of vias is formed for each integrated circuit. Additionally, although already bonded... Figure 4A and Figure 4B The method details the formation Figure 2A This is an example of device 200, but other methods can be used to obtain this device.

Claims

1. A microelectronic device, characterized by: Comprising: a substrate including a first connection terminal and a second connection terminal electrically coupled to the first connection terminal; a first integrated circuit mounted on the substrate and electrically coupled to the first connection terminal; a first layer of resin on the substrate compatible with direct laser structuring (LDS), wherein the first integrated circuit is incorporated into the first layer and the first layer covers the second connection terminal; a first LDS via through the first layer and electrically coupled to the second connection terminal; a second integrated circuit mounted above the first integrated circuit; a second layer of resin on the first layer compatible with LDS, wherein the second integrated circuit is incorporated into the second layer; and a second LDS via through the second layer and electrically coupled to the first LDS via.

2. The microelectronic device of claim 1, wherein, Further comprising an LDS metal track electrically coupling the second LDS via to the second integrated circuit.

3. The microelectronic device of claim 1, wherein: The second LDS via is laterally offset from the first LDS via and connected thereto by the LDS metal track.

4. The microelectronic device of claim 1, wherein, The first and second integrated circuits each have a first surface and a second surface opposite the first surface, the first surface including a metallization including one or more connection terminals, and wherein the first and second integrated circuits are mounted with their second surfaces facing each other.

5. The microelectronic device of claim 1, wherein Further comprising a device on the second layer, wherein the device is electrically coupled to the second via.

6. The microelectronic device of claim 1, wherein: Further comprising a third layer of resin made of resin on the second layer and covering the second LDS via.

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