Semiconductor device

Abstract

The semiconductor device provided by the embodiment of the utility model comprises a first integrated circuit, a second integrated circuit and a bonding layer, a bonding layer is between the first integrated circuit and the second integrated circuit, where the bonding layer includes a first layer and a second layer, the first layer being an aluminum nitride (AlN) layer, and the second layer being one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. A steady increase in demand has created pressure to reduce costs, prices, size, and weight, and to increase quality and reliability of ICs. This has created pressure to improve the fabrication process as well as to develop new technologies and techniques. SUMMARY

[0003] According to an embodiment of the present application, a semiconductor device includes a first integrated circuit, a second integrated circuit, and a bonding layer. The bonding layer is between the first integrated circuit and the second integrated circuit, wherein the bonding layer includes a first layer and a second layer, the first layer is an aluminum nitride (AlN) layer, and the second layer is one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer.

[0004] According to an embodiment of the present application, a semiconductor device includes an interconnect structure. The interconnect structure includes a plurality of dielectric layers, a plurality of conductive patterns, and at least one heat dissipation pattern. The at least one heat dissipation pattern includes a first layer and a second layer, the first layer is an aluminum nitride (AlN) layer, and the second layer is one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present disclosure can be better understood, and its numerous objects, advantages, and features can be appreciated, when the following detailed description of the application, taken in conjunction with the accompanying drawings, is read with reference made to such illustrations where:

[0006] Figures 1A-1G is a schematic cross-sectional view illustrating a method of forming a semiconductor device according to some embodiments of the present application.

[0007] Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0008] Figures 3A-3E is a schematic cross-sectional view illustrating a method of forming a semiconductor device according to some embodiments of the present application.

[0009] Figures 4A-4C is a schematic cross-sectional view illustrating a method of forming a semiconductor device according to some embodiments of the present application.

[0010] Figure 5 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0012] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0013] Figure 8 A flowchart of a method for forming a semiconductor device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of this utility model. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship between one component or feature and another, as illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0016] Other features and processes may also be included. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packaged or 3D integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in the routing or on a substrate to enable testing of the 3D package or 3DIC, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0017] This invention provides a heat dissipation material to better dissipate heat from semiconductor devices. In some embodiments, the heat dissipation material is a multilayer comprising an aluminum nitride layer and an aluminum oxide layer, or an aluminum nitride layer and an aluminum oxynitride layer. The heat dissipation material may serve as a bonding layer for bonding integrated circuits, or as a heat dissipation pattern and / or etched top layer to improve heat dissipation in integrated circuits. By using the heat dissipation material, semiconductor devices can have improved heat dissipation, thereby improving yield and performance.

[0018] Figures 1A-1G This is a schematic cross-sectional view illustrating a method for forming a semiconductor device according to some embodiments of the present invention.

[0019] Please refer to Figure 1A An integrated circuit 100A is provided. The integrated circuit 100A may be a wafer, die, package, die stack, or the like, and may also be referred to as a circuit component. In some embodiments, the integrated circuit 100A includes a semiconductor substrate 102, a plurality of components 112, and an interconnect structure 120. In some embodiments, the semiconductor substrate 102 is made of an elemental semiconductor material, such as crystalline silicon, diamond, or germanium; made of a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or made of an alloy semiconductor material, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. The semiconductor substrate 102 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0020] In some embodiments, component 112 is a transistor. For example, each component 112 includes a source / drain region 114 and a gate 116. Each component 112 may also include a channel region (not shown) below the gate 116. The channel region may also be located between the source / drain regions 114, serving as a path for electrons to travel when component 112 is energized.

[0021] In some embodiments, the semiconductor substrate 102 includes various doped regions depending on circuit requirements (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate). In some embodiments, the doped regions are doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. In some embodiments, these doped regions serve as source / drain regions 114 of component 112. Depending on the type of dopant in the doped regions, component 112 may be referred to as an n-type transistor or a p-type transistor.

[0022] In some embodiments, the gate 116 comprises copper, titanium, tantalum, tungsten, aluminum, zirconium, hafnium, cobalt, titanium aluminum, tantalum aluminum, tungsten aluminum, zirconium aluminum, hafnium aluminum, titanium nitride, any other suitable metallic material or combination thereof. In some embodiments, the gate 116 further comprises a material for fine-tuning the corresponding work function. For example, the gate 116 may also comprise a p-type work function material such as Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2 or combinations thereof, or an n-type work function material such as Ag, TaCN, Mn or combinations thereof.

[0023] In some embodiments, such as Figure 1A As shown, the source / drain region 114 is buried in the semiconductor substrate 102, and the gate 116 is located above the semiconductor substrate 102. However, the present invention is not limited thereto. In alternative embodiments, both the source / drain region 114 and the gate 116 are located above the semiconductor substrate 102. In some embodiments, the component 112 may be separated by shallow trench isolation (STI; not shown) between adjacent components 112. In some embodiments, the component 112 is formed using a suitable front-end production line (FEOL) process.

[0024] Interconnect structure 120 is formed on semiconductor substrate 102 and component 112. In some embodiments, interconnect structure 120 includes a plurality of dielectric layers 130 and a plurality of conductive features 140. In some embodiments, dielectric layers 130 are stacked on top of each other. For example, adjacent dielectric layers 130 are in physical contact with each other. In some embodiments, the material of dielectric layer 130 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, dielectric layer 130 may be formed of oxides or nitrides, such as silicon oxide, silicon nitride, hafnium oxide, hafnium zirconium oxide, etc. In some embodiments, different dielectric layers 130 are formed using the same material. However, the present invention is not limited thereto. Alternatively, different dielectric layers 130 may be formed of different materials. Dielectric layer 130 may be formed by suitable manufacturing techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the number of dielectric layers 130 is eight; however, the number of dielectric layers 130 may be fewer or more.

[0025] In some embodiments, the conductive feature 140 includes a plurality of vias 142 and a plurality of conductive patterns 144. For example... Figure 1A As shown, conductive feature 140 is embedded in dielectric layer 130. That is, via 142 and conductive pattern 144 are embedded in dielectric layer 130. For example, dielectric layer 130 laterally covers via 142 and conductive pattern 144. In some embodiments, conductive pattern 144 extends horizontally. Conductive pattern 144 may also be referred to as a wire. Meanwhile, via 142 extends vertically to connect conductive patterns 144 located in different layers. In other words, conductive patterns 144 are electrically connected to each other through via 142. In some embodiments, the bottommost via 142 is connected to component 112. For example, the bottommost via 142 is connected to the source / drain region 114 and gate 116 of component 112. In other words, the bottommost via 142 establishes an electrical connection between component 112 and conductive pattern 144. That is, conductive feature 140 is electrically connected to component 112. In some embodiments, the bottommost through-hole 142 may be referred to as the "contact structure" of component 112.

[0026] In some embodiments, the materials of the conductive pattern 144 and the via 142 include copper, nickel, cobalt, ruthenium, iridium, aluminum, platinum, palladium, gold, silver, osmium, tungsten, molybdenum, titanium, etc., or alloys thereof. The conductive pattern 144 and the via 142 can be formed by electrochemical plating (ECP) or deposition and / or photolithography and etching, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and electroless plating deposition (ELD). In some embodiments, the process temperature for forming the conductive pattern 144 and the via 142 is 425°C or below. In some embodiments, the conductive pattern 144 and the underlying via 142 are each formed by a single damascene process. In some embodiments, such as Figure 1A As shown, the via 142 and the underlying conductive pattern 144 are embedded in the corresponding dielectric layer 130. However, the present invention is not limited thereto. Alternatively, the conductive pattern 144 and the underlying via 142 can be formed simultaneously by a dual damascene process. In such an embodiment, the via 142 and the underlying conductive pattern 144 can be embedded in the same dielectric layer 130. In some embodiments, the top surface of each of the via 142 and the conductive pattern 144 is coplanar with the top surface of the corresponding dielectric layer 130. In some embodiments, the uppermost conductive feature 140 is the conductive pattern 144. However, the present invention is not limited thereto. In an alternative embodiment, the uppermost conductive feature 140 is the via 142. In addition, the uppermost conductive feature 140 may be exposed or covered by the dielectric layer 130.

[0027] Please refer to Figure 1B A first layer 202 is formed over the integrated circuit 100A. In some embodiments, the first layer 202 comprises aluminum nitride (AlN). The first layer 202 can be deposited using physical vapor deposition (PVD). For example, the first layer 202 is deposited in a PVD chamber using an aluminum target and a nitrogen-containing gas stream (e.g., nitrogen (N2)). The PVD process for depositing the first layer 202 can be pulsed DC sputtering or sputtering with a radio frequency (RF) bias. In some embodiments, a first layer 202 with high crystallinity is formed, such that the first layer 202 exhibits good thermal conductivity. However, alternatively, the first layer 202 can be crystalline, amorphous, or a combination thereof, as needed. To achieve high crystallinity, the PVD process is performed at low temperatures (e.g., between about 20°C and about 300°C) and low pressures (e.g., between about 1 Torr and about 3 Torr). The first layer 202 formed under the above conditions can have a thermal conductivity between about 230 W / mK and about 320 W / mK at room temperature. In some embodiments, the first layer 202 may have a first thickness T1. In some embodiments, the first thickness T1 may be between about 100 angstroms and about 200 angstroms.

[0028] Please refer to Figure 1CA process TT is performed to transform the top of the first layer 202 into a second layer 204. In some embodiments, the second layer 204 comprises aluminum oxide (AlO) or aluminum oxynitride (AlON), which can be considered as a partially oxidized form of the first layer 202 or an oxygen-doped form of the first layer 202. The second layer 204 may also be referred to as a leakage-reducing layer. In this embodiment, the process TT includes a nitrous oxide (N2O) plasma treatment. In some embodiments, the nitrous oxide (N2O) plasma treatment introduces oxygen into the top of the first layer 202 and transforms it into the second layer 204. In some embodiments, the nitrous oxide (N2O) plasma treatment for forming aluminum oxide (AlO) or aluminum oxynitride (AlON) may include the use of a dual-frequency plasma source, wherein the high frequency is between about 500 W and about 1200 W, and the low frequency is between about 50 W and about 250 W. For example, the nitrous oxide plasma treatment lasts between about 5 seconds and about 60 seconds. In an alternative embodiment, the nitrous oxide (N2O) plasma treatment for forming aluminum oxynitride (AlON) may include the use of a dual-frequency plasma source, wherein the high frequency is between about 200 MHz and about 600 MHz, and the low frequency is between about 50 MHz and about 300 MHz. For example, the nitrous oxide plasma treatment lasts between 1 second and about 15 seconds. The nitrous oxide (N2O) plasma treatment is performed at a low temperature, for example below 400°C. In an alternative embodiment, the treatment TT includes ultraviolet (UV) treatment in an inert gas environment, such as argon (Ar), helium (He), or a combination of both (Ar / He). In such an embodiment, the UV treatment can remove defects in the first layer 202. For example, the UV treatment lasts between about 6 seconds and about 60 seconds or between about 15 seconds and about 60 seconds, and the frequency remains between about 100 W and about 300 W. After the UV treatment, the treated first layer 202 is exposed to ambient air, and oxygen (O2) in the ambient air can combine with the top of the first layer 202 to form a second layer 204. In an alternative embodiment, the treatment TT may include UV treatment and nitrous oxide (N2O) plasma treatment. The former removes defects in the first layer 202, while the latter transforms the top of the first layer 202 into a second layer 204. The second layer 204, comprising aluminum oxide (AlO) or aluminum oxynitride (AlON), exhibits low leakage current compared to the first layer 202, which comprises aluminum nitride (AlN). The second layer 204 may be crystalline, amorphous, or a combination thereof, as needed. The treatment TT can be considered an oxygen doping process, and oxygen doping affects the lattice thermal conductivity due to additional phonon scattering. The second thickness T2 of the remaining first layer 202 (i.e., the AlN layer) may be less than, substantially equal to, or greater than the third thickness T3 of the second layer 204 (i.e., the AlO or AlON layer).In some embodiments, the initial thickness T1 can be between about 100 angstroms and about 200 angstroms, the second thickness T2 of the remaining first layer 202 (i.e., the AlN layer) is between about 80 angstroms and about 160 angstroms, and the second layer 204 (i.e., the AlO or AlON layer) is between about 40 angstroms and about 70 angstroms. The thickness difference between the remaining first layer 202 (i.e., the AlN layer) and the second layer 204 (i.e., the AlO or AlON layer) is between about 40 angstroms and about 90 angstroms. However, the present invention is not limited thereto. In some embodiments, the first layer 202 and the second layer 204 can be collectively referred to as dielectric pair 206 or composite dielectric layer.

[0029] Please refer to Figure 1D After forming dielectric pair 206, at least one additional dielectric pair 206 can be formed on dielectric pair 206. In other words, at least one additional dielectric pair 206 can be formed according to the desired total thickness of the thermal ductile material (TDM). For example, Figure 1B The first layer 202 and Figure 1C The formation of the second layer 204 can be repeated to form additional dielectric pairs 206. In this regard, it can be seen that... Figure 1B and Figure 1C The operations described can be viewed as repeatable cycles to achieve a desired thickness. In some embodiments, including... Figure 1B and 1C The operation can be performed once or repeated 1 to 100 times. The final dielectric pair 206 stack can be referred to as a thermally conductive material (TDM). That is, the thermally conductive material TDM includes multiple staggered first layers 202 and multiple second layers 204. For example, the thermally conductive material TDM includes multiple staggered AlN layers and multiple AlO layers, or the thermally conductive material TDM includes multiple staggered AlN layers and multiple AlON layers. When the cycle is performed only once, the thermally conductive material TDM includes one first layer 202 and one second layer 204, and one dielectric pair 206. For illustrative purposes but not to limit the scope of the present invention, Figure 1D The heat dissipation material TDM shown includes three (3) dielectric pairs 206. In an alternative embodiment, the heat dissipation material TDM may include fewer or more dielectric pairs 206 of the first 202 and the second layer 204.

[0030] In some embodiments, deposition is performed once or repeatedly. Figure 1B The first layer 202 and convert the top of the first layer 202 into Figure 1CThe second layer 204 is cycled to form the thermally dissipating material TDM. However, the present invention is not limited thereto. In some embodiments, a first layer 202 of AlN and a second layer 204 of AlO or AlON can be deposited separately. The first layer 202 of AlN can be deposited using ALD or CVD. The deposition of the first layer 202 may include the use of aluminum-containing precursors and nitrogen-containing precursors. Examples of aluminum-containing precursors may include trimethylaluminum (TMA) or triethylaluminum (TEA). Examples of nitrogen-containing precursors may include ammonia (NH3), tert-butylamine (TBAm), or phenylhydrazine. In some embodiments, the first layer 202 has high crystallinity, such that the first layer 202 exhibits good thermal conductivity. For example, the first layer 202 has a thermal conductivity between about 230 W / mK and about 320 W / mK at room temperature. In some embodiments, the first layer 202 is deposited to have a desired thickness (e.g., as shown in the figure). Figure 1C The second thickness T2 is shown. ALD or CVD can also be used to deposit a second layer 204 of AlO or AlON. When the second layer 204 comprises alumina (AlO), the deposition may include aluminum-containing precursors and oxygen-containing precursors. Examples of aluminum-containing precursors may include trimethylaluminum (TMA) or triethylaluminum (TEA). Examples of oxygen-containing precursors may include oxygen (O2) or nitrous oxide (N2O). When the second layer 204 comprises aluminum oxynitride (AlON), the deposition may include aluminum-containing precursors, oxygen-containing precursors, and nitrogen-containing precursors. Examples of oxygen-containing precursors may include oxygen (O2) or nitrous oxide (N2O). Examples of aluminum-containing precursors may include trimethylaluminum (TMA) or triethylaluminum (TEA). Examples of nitrogen-containing precursors may include ammonia (NH3), tert-butylamine (TBAm), or phenylhydrazine. Since the deposition of both the first layer 202 and the second layer 204 can be performed using either ALD or CVD, the first layer 202 and the second layer 204 can be deposited in the same processing chamber without disrupting the vacuum. In some embodiments, the second layer 204 is deposited to have the desired thickness (e.g., as shown in the image). Figure 1C The thickness T3 shown is a third thickness. The thickness of the first layer 202 (i.e., the AlN layer) can be less than, substantially the same as, or greater than the thickness of the second layer 204 (i.e., the AlO or AlON layer). In some embodiments, the thickness of the first layer 202 (i.e., the AlN layer) is between about 80 angstroms and about 160 angstroms, and the thickness of the second layer 204 (i.e., the AlO or AlON layer) is between about 40 angstroms and about 70 angstroms. The thickness difference between the first layer 202 (i.e., the AlN layer) and the second layer 204 (i.e., the AlO or AlON layer) is between about 40 angstroms and about 90 angstroms. However, the present invention is not limited thereto. In such embodiments, the thermally conductive material TDM is formed by performing one or more cycles of depositing the first layer 202 and depositing the second layer 204.

[0031] As described above, thermally conductive material TDM exhibits good thermal conductivity and low leakage current. Furthermore, TDM also possesses adhesive properties and can therefore be used as an adhesive. In some embodiments, the thermally conductive material TDM serves as bonding layer 210. In some embodiments, after forming bonding layer 210 on integrated circuit 100A, a planarization process can be performed on bonding layer 210. In some embodiments, the planarization process includes mechanical polishing, chemical mechanical polishing, etc. After the planarization process, bonding layer 210 has a substantially flat top surface. It should be noted that the planarization process here is optional; that is, it can be omitted in some embodiments.

[0032] Please refer to Figure 1E After forming the bonding layer 210, an integrated circuit 100B is provided. In some embodiments, the integrated circuit 100B and... Figure 1A Similar to integrated circuit 100A. In some embodiments, integrated circuit 100B includes a semiconductor substrate 102, a plurality of components 112, and an interconnect structure 120. Each component 112 includes a source / drain region 114 and a gate 116. The interconnect structure 120 includes, for example, a plurality of dielectric layers 130 and a plurality of conductive features 140. The conductive features 140 may include a plurality of vias 142 and a plurality of conductive patterns 144. In some embodiments, the uppermost conductive feature 140 of integrated circuit 100B is a via 142. In some embodiments, the semiconductor substrate 102, components 112, source / drain regions 114, gate 116, dielectric layers 130, vias 142, and conductive patterns 144 are similar to their counterparts in integrated circuit 100A, and therefore will not be described again here.

[0033] like Figure 1E As shown, integrated circuit 100B is placed on top of integrated circuit 100A and bonded to integrated circuit 100A. In some embodiments, integrated circuit 100B is attached to integrated circuit 100A via bonding layer 210. That is, bonding layer 210 is sandwiched between integrated circuit 100A and integrated circuit 100B. Figure 1E As shown, the bonding layer 210 is in physical contact with the dielectric layer 130 of integrated circuit 100A and the semiconductor substrate 102 of integrated circuit 100B.

[0034] In some embodiments, before attaching the integrated circuit 100B, the integrated circuit 100B can be placed on a carrier substrate (not shown). Then, the semiconductor substrate 102 of the integrated circuit 100B can be thinned to reduce the overall thickness of the integrated circuit 100B. The thinning process includes mechanical polishing, chemical mechanical polishing, etc. After thinning the semiconductor substrate 102 of the integrated circuit 100B, the integrated circuit 100B is placed on the bonding layer 210, thus bonding the integrated circuit 100B to the integrated circuit 100A. In some embodiments, the bonding between the integrated circuit 100A and the integrated circuit 100B is referred to as face-to-face bonding.

[0035] Please refer to Figure 1F Multiple through-holes 220 are formed. In some embodiments, the material in the through-holes 220 includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The through-holes 220 can be formed by electroplating, deposition, and / or photolithography and etching. Figure 1F As shown, via 220 passes through at least one of integrated circuit 100B, bonding layer 210, and dielectric layer 130 to make physical contact with one of conductive patterns 324. In other words, via 220 is electrically connected to interconnect structure 120 and then to integrated circuit 100A.

[0036] Please refer to Figure 1G Multiple bottom bump metal patterns 230 (UBMs) are formed on the conductive pattern 144 and via 220 of integrated circuit 100B. For example, the bottom bump metal patterns 230 are formed on the top dielectric layer 130, the top via 142, and the via 220. In some embodiments, the bottom bump metal patterns 230 are in physical contact with the top via 142 to be electrically connected to the interconnect structure 120 of integrated circuit 100B. Simultaneously, the bottom bump metal patterns 230 are also electrically connected to the interconnect structure 120 of integrated circuit 100A through physical contact with the via 220. In some embodiments, the bottom bump metal patterns 230 are formed by sputtering, PVD, electroplating, or other processes. In some embodiments, the bottom bump metal patterns 230 are made of aluminum, titanium, copper, tungsten, and / or their alloys.

[0037] After forming the bump base metal pattern 230, a plurality of conductive terminals 240 are disposed on the bump base metal pattern 230. In some embodiments, the conductive terminals 240 are attached to the bump base metal pattern 230 by solder. In some embodiments, the conductive terminals 240 are, for example, solder balls, ball grid array (BGA) balls, or controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 240 are made of a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof.

[0038] Subsequently, the interconnect structure 120 of integrated circuit 100B and the semiconductor substrate 102, the bonding layer 210, and the interconnect structure 120 of integrated circuit 100A and the semiconductor substrate 102 are subjected to a monomerization process to obtain a plurality of semiconductor devices 10. In some embodiments, the monomerization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monomerization process includes laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof.

[0039] In some embodiments, a bonding layer comprising at least one pair of AlN and AlO layers or at least one pair of AlN and AlON layers serves as an adhesive for bonding integrated circuits. In each pair, the highly crystalline AlN layer can exhibit good thermal conductivity, and the AlO or AlON layer can exhibit low leakage current. For example, a breakdown electric field higher than 3 MV / cm and a low leakage current density of 10-1 -7 ~10 -9 A / cm 2 Therefore, the bonding layer also provides a good heat dissipation path for the semiconductor device, including the bonded integrated circuit. As a result, the semiconductor device can have improved heat dissipation and thus improved yield and performance.

[0040] In some embodiments, thermally conductive material (TDM) serves as a bonding layer. However, the present invention is not limited thereto. TDM can also be used to form thermal patterns, etch stop layers, etc.

[0041] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. In some embodiments, the semiconductor device 10A includes... Figure 1G The integrated circuit 100B shown is similar to integrated circuit 100B', therefore similar components are represented by the same component symbols, and their detailed descriptions are omitted here. The difference between integrated circuit 100B' and integrated circuit 100B lies in the formation of the interconnect structure 120 and the heat dissipation pattern 150. Specifically, in some embodiments, at least one layer of the interconnect structure 120 may employ... Figures 3A-3E or Figures 4A-4C The method in. Note that, although Figures 3A-3E or Figures 4A-4C The method is illustrated as being used to form the via 142, but Figures 3A-3E or Figures 4A-4C The method can also be used to form conductive patterns 144.

[0042] Figures 3A-3E This is a schematic cross-sectional view illustrating a method for forming a semiconductor device (i.e., a layer of interconnect structure) according to some embodiments of the present invention.

[0043] Please refer to Figure 3AA heat dissipation material (TDM) is formed on top of structure S. Structure S can be... Figure 2 The interconnect structure 120 can be any dielectric layer 130 or semiconductor substrate 102. The heat dissipation material TDM can be formed by performing the cycle of forming the first layer 202 and forming the second layer 204 once or repeatedly as described above until a heat dissipation material TDM of the desired thickness is obtained. The thickness of the heat dissipation material TDM can be approximately the thickness of the dielectric layer 130 to be formed (e.g., ...). Figure 3E (As shown). In some embodiments, the thermal thermal material TDM includes a plurality of interleaved first layers 202 and a plurality of second layers 204. For example, the thermal thermal material TDM includes a plurality of interleaved AlN layers and a plurality of AlO layers, or the thermal thermal material TDM includes a plurality of interleaved AlN layers and a plurality of AlON layers. For illustrative purposes but not for limiting the scope of the invention, the thermal thermal material TDM includes five (5) dielectric pairs of first layers 202 and second layers 204. In alternative embodiments, the thermal thermal material TDM may include fewer or more dielectric pairs 206 of first layers 202 and second layers 204.

[0044] Please refer to Figure 3B The thermally conductive material (TDM) is patterned to form multiple openings (OPs). For example, the openings (OPs) penetrate the TDM to partially expose underlying conductive features 140, such as conductive patterns 144. In some embodiments, the patterning process of the TDM includes photolithography and etching processes. The etching process includes dry etching. For example, the TDM is patterned using reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, neutral beam etching (NBE), etc. In some embodiments, CF4 or C4F8 is used as the etching gas during the dry etching process.

[0045] Please refer to Figure 3CMultiple conductive features 140, such as vias 142, are formed in the opening OP. For example, a barrier material and a conductive material are conformally formed on the heat dissipation material TDM. In some embodiments, the barrier material is conformally formed over the exposed surfaces of the heat dissipation material TDM (e.g., the sidewalls and bottom surfaces of the opening OP and the top surface of the heat dissipation material TDM), and the conductive material is conformally formed over the barrier material and fills the opening OP. In some embodiments, the barrier material includes titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), and combinations thereof. In some embodiments, the barrier material is deposited on the heat dissipation material TDM by CVD, PVD, etc. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, conductive materials are deposited into the open-ended structure (OP) using methods such as PVD, ion beam deposition (IBD), CVD, ALD, molecular beam epitaxy (MBE), electrochemical plating (ECP), and electroless deposition (ELD). In some embodiments, the conductive material can be formed at a temperature above 425°C. Subsequently, a planarization process can be performed on the barrier material and the conductive material until the heat dissipation material (TDM) is exposed. In some embodiments, the planarization process includes mechanical polishing, chemical mechanical polishing, etc. After the planarization process, the top surfaces of the barrier material and the conductive material in the open-ended OP are exposed and are coplanar with the top surface of the heat dissipation material (TDM). In some embodiments, after the planarization process, a capping material is optionally formed on the exposed top surfaces of the barrier material and the conductive material. In some embodiments, the capping material includes cobalt, silicon nitride, or similar materials, and the capping material is deposited at a temperature below 450°C using PVD, CVD, ALD, or similar methods. In some embodiments, as... Figure 3C As shown, the formed via 142 includes a barrier layer 142a, a conductive layer 142b, and a capping layer 142c. In some embodiments, the barrier layer 142a is disposed between and surrounds the conductive layer 142b and the dielectric layer 130. The top surface of the barrier layer 142a and the top surface of the conductive layer 142b may be substantially coplanar. For example, the capping layer 142c is disposed on the top surface of the conductive layer 142b, and the top surface of the capping layer 142c is substantially coplanar with or above the top surface of the thermal ductile material (TDM). In embodiments where the capping layer 142c is omitted, the top surfaces of the barrier layer 142a and the conductive layer 142b may be substantially coplanar with the top surface of the thermal ductile material (TDM).

[0046] Please refer to Figure 3DAfter forming the via 142, the remaining heat dissipation material TDM is patterned to form at least one heat dissipation pattern 150. In some embodiments, the patterning process of the heat dissipation material TDM includes photolithography and etching processes. The etching process includes dry etching. For example, the heat dissipation material TDM can be patterned by reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, neutral beam etching (NBE), etc. In some embodiments, CF4 or C4F8 can be used as the etching gas during the dry etching process. During the patterning process, a mask can be used, for example, to protect the via 142 from damage. In some embodiments, such as Figure 3D As shown, the formed heat dissipation pattern 150 includes multiple interlaced first layers 202 and multiple second layers 204. For example, the heat dissipation material TDM includes multiple interlaced AlN layers and multiple AlO layers, or the heat dissipation material TDM includes multiple interlaced AlN layers and multiple AlON layers. This is for illustrative purposes and does not limit the scope of the present invention. Figure 3D The heat dissipation pattern 150 shown includes five (5) dielectric pairs of a first layer 202 and a second layer 204. The heat dissipation pattern 150 can be set in... Figure 2 The thermal pattern 150 can be disposed at any suitable location within the interconnect structure 120. For example, the thermal pattern 150 can be disposed in any dielectric layer 130 adjacent to the via 142. In an alternative embodiment, the thermal pattern 150 can be disposed in a dielectric layer 130 without the via 142. Alternatively, the thermal pattern 150 can be configured adjacent to the conductive pattern 144. In some embodiments, the thermal pattern 150 is formed as a via. However, the invention is not limited thereto. The thermal pattern 150 can have any suitable shape. For example, the thermal pattern 150 is linear. Additionally, there may be multiple thermal patterns 150 within a single dielectric layer 130. In some embodiments, the thermal pattern 150 penetrates only one dielectric layer 130. However, the invention is not limited thereto. In an alternative embodiment, the thermal pattern 150 continuously penetrates at least two dielectric layers 130.

[0047] Please refer to Figure 3EAfter forming conductive features (e.g., vias 142) and heat dissipation patterns 150, a dielectric layer 130 is formed to laterally cover the conductive features (e.g., vias 142) and heat dissipation patterns 150. In some embodiments, the dielectric layer 130 is made of a boron carbonitride (BCN)-based material, and the dielectric layer 130 is formed using suitable fabrication techniques, such as CVD, ALD, etc. For example, the dielectric layer 130 is deposited in a CVD or ALD chamber using triethylamine borane with He, H2, and NH3. The deposition process can be performed at a low temperature, for example, below 425°C. The K value of the formed dielectric layer 130 can be in the range of 1.9 to 2.8, and the hardness of the formed dielectric layer 130 can be in the range of 20 GPa to 30 GPa.

[0048] In alternative embodiments, the dielectric layer 130 may be made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layer 130 may be formed of oxides or nitrides, such as silicon oxide, silicon nitride, hafnium oxide, hafnium zirconium oxide, etc. The dielectric layer 130 may be formed using suitable fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0049] In some embodiments, at least one of the dielectric layers 130 is formed of a BCN-based material. For example, in Figure 2 In this embodiment, some dielectric layers 130 are formed of a BCN-based material, and more than one dielectric layer 130 is formed of a material other than a BCN-based material. In an alternative embodiment, all dielectric layers 130 are formed of a BCN-based material.

[0050] Figure 4A and Figure 4C This is a schematic cross-sectional view illustrating a method for forming a semiconductor device (i.e., a layer of interconnect structure) according to some embodiments of the present invention.

[0051] Please refer to Figure 4A An etch stop layer 128 is formed above structure S, and a dielectric layer 130 is formed above etch stop layer 128. Structure S can be... Figure 2 The interconnect structure 120 may be any dielectric layer 130 or semiconductor substrate 202. In some embodiments, the etch stop layer 128 comprises a heat-dissipating material TDM. In other words, the etch stop layer 128 can be formed by performing one or more cycles of forming the first layer 202 and forming the second layer 204 until an etch stop layer 128 of the desired thickness is obtained. In such embodiments, as Figure 4AAs shown, the etch stop layer 128 includes a plurality of interleaved first layers 202 and a plurality of interleaved second layers 204. For example, the etch stop layer 128 includes a plurality of interleaved AlN layers and a plurality of AlO layers, or the etch stop layer 128 includes a plurality of interleaved AlN layers and a plurality of AlON layers. This is for illustrative purposes and does not limit the scope of the present invention. Figure 4A The etch stop layer 128 shown includes two (2) dielectric pairs of the first layer 202 and the second layer 204. However, the present invention is not limited thereto. The etch stop layer 128 may include one (1) dielectric pair of the first layer 202 and the second layer 204 or more than two (2) dielectric pairs of the first layer 202 and the second layer 204. In some embodiments, such as Figure 2 As shown, the etch stop layer 128 can be in direct contact with the underlying conductive features 140 (e.g., vias 142 and conductive patterns 144) and / or the underlying heat dissipation pattern 150.

[0052] In an alternative embodiment, the etch stop layer 128 is made of materials including SiCN, AlN, AlON, AlO, AlOC, or combinations thereof, and the etch stop layer 128 is formed by CVD, ALD, or the like. For example, the etch stop layer 128 is made of SiC. p N q The etch stop layer 128 is formed by using Si(CH3)4 and NH3 as target sources via CVD or ALD processes. Alternatively, the etch stop layer 128 is made of AlN. x The etch stop layer 128 is formed by using Al(CH3)3 and NH3 as target sources via CVD or ALD processes. The etch stop layer 128 may comprise a single layer or multiple layers. However, the present invention is not limited thereto.

[0053] In some embodiments, the dielectric layer 130 may be Figure 2 Any dielectric layer 130. In some embodiments, dielectric layer 130 is formed on etch stop layer 128 and directly contacts second layer 204 (e.g., AlO or AlON) of etch stop layer 128. In some embodiments, the material of dielectric layer 130 includes BCN-based materials, and dielectric layer 130 is formed by suitable fabrication techniques, such as CVD, ALD, etc. For example, dielectric layer 130 is deposited in a CVD or ALD chamber using triethylamine borane with He, H2, and NH3. The deposition process can be performed at a low temperature below 425°C. The K value of the formed dielectric layer 130 can be in the range of 1.9 to 2.8, and the hardness of the formed dielectric layer 130 can be in the range of 20 GPa to 30 GPa.

[0054] In alternative embodiments, the dielectric layer 130 may be made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layer 130 may be formed of oxides or nitrides, such as silicon oxide, silicon nitride, hafnium oxide, hafnium zirconium oxide, etc. The dielectric layer 130 may be formed using suitable fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0055] Please refer to Figure 4B The etch stop layer 128 and dielectric layer 130 are patterned to form a plurality of openings (OPs). For example, the openings (OPs) penetrate the etch stop layer 128 and dielectric layer 130 to partially expose underlying conductive features, such as conductive pattern 144, via 142, source / drain region 114, and gate 116. In some embodiments, the patterning process in the etch stop layer 128 and dielectric layer 130 includes photolithography and etching processes. The etching process includes dry etching. For example, the etch stop layer 128 and dielectric layer 130 can be patterned by reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, neutral beam etching (NBE), etc. In some embodiments, during the etching process of dielectric layer 130, the etch stop layer 128 can prevent over-etching, thereby protecting the underlying conductive features such as conductive pattern 144, via 142, source / drain region 114, and gate 116 from damage.

[0056] Please refer to Figure 4CMultiple conductive features 140, such as vias 142, are formed in the opening OP. For example, barrier material and conductive material are conformally formed on dielectric layer 130. In some embodiments, barrier material is conformally formed over exposed surfaces of dielectric layer 130 (e.g., sidewalls and bottom surfaces of opening OP and top surface of dielectric layer 130), and conductive material is conformally formed over barrier material and fills opening OP. In some embodiments, barrier material includes titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), and combinations thereof. In some embodiments, barrier material is deposited on dielectric layer 130 by CVD, PVD, or the like. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, the conductive material is deposited into the opening OP by PVD, ion beam deposition (IBD), CVD, ALD, molecular beam epitaxy (MBE), electrochemical plating (ECP), electroless deposition (ELD), etc. In some embodiments, the conductive material can be formed at a temperature below 425°C. Thereafter, a planarization process can be performed on the barrier material and the conductive material until the dielectric layer 130 is exposed. In some embodiments, the planarization process includes mechanical polishing, chemical mechanical polishing, etc. After the planarization process, the top surfaces of the barrier material and the conductive material in the opening OP are exposed and are coplanar with the top surface of the dielectric layer 130. In some embodiments, after the planarization process, a capping material is optionally formed on the exposed top surfaces of the barrier material and the conductive material. In some embodiments, the capping material includes cobalt, silicon nitride, or similar materials, and the capping material is deposited by PVD, CVD, ALD, or similar materials at a temperature below 450°C. In some embodiments, as Figure 4C As shown, the formed via 142 includes a barrier layer 142a, a conductive layer 142b, and a capping layer 142c. In some embodiments, the barrier layer 142a is disposed between and surrounds the conductive layer 142b and the dielectric layer 130. The top surface of the barrier layer 142a and the top surface of the conductive layer 142b may be substantially coplanar. For example, the capping layer 142c is disposed on the top surface of the conductive layer 142b, and the top surface of the capping layer 142c is substantially coplanar with or above the top surface of the dielectric layer 130. In embodiments where the capping layer 142c is omitted, the top surfaces of the barrier layer 142a and the conductive layer 142b may be substantially coplanar with the top surface of the dielectric layer 130.

[0057] As described above, the heat dissipation material exhibits good thermal conductivity and low leakage current, thus the etch stop layer 128 and the heat dissipation pattern 150 can provide good heat dissipation. In some embodiments, the etch stop layer 128 can be formed directly beneath each dielectric layer 130 of the interconnect structure 120, and in contact with the conductive feature 140 and / or the heat dissipation pattern 150. The etch stop layer 128, the conductive feature 140, and the heat dissipation pattern 150 together can form a good heat dissipation path to improve the heat dissipation performance of the semiconductor device. Furthermore, by employing a BCN-based material as at least one dielectric layer of the interconnect structure, the dielectric layer has a low dielectric constant, higher hardness, and higher mechanical strength. Therefore, the yield and / or performance of the semiconductor device can be improved.

[0058] In some embodiments, the interconnect structure is considered to be formed during the back-end (BEOL) process. Generally, the thermal budget (i.e., process temperature margin) of the BEOL process is low. As mentioned above, the process temperature for forming the thermal material is low, and therefore falls within the thermal budget of the BEOL process. In other words, the thermal patterns formed using the thermal material can be integrated into the process or semiconductor device while remaining compatible with the BEOL thermal budget.

[0059] Figure 2 The integrated circuit 100B' can also be stacked on top of another integrated circuit. In some embodiments, such as Figure 5 As shown, Figure 2 Integrated circuit 100B' and integrated circuit 100A' are bonded together to form semiconductor device 10B. Integrated circuit 100A' and Figure 1G Similar to integrated circuit 100A, the difference is that the interconnect structure 120 of integrated circuit 100A' can adopt... Figures 3A-3E and / or Figures 4A-4C The method described herein forms the semiconductor device 10B. In the semiconductor device 10B, at least one of the bonding layer 210, the etch stop layer 128, and the heat dissipation pattern 150 may be formed of a heat dissipation material TDM, and / or at least one of the dielectric layers 130 may be formed of a BCN-based material.

[0060] In the above embodiments, the integrated circuits are bonded and stacked. However, the present invention is not limited thereto. In an alternative embodiment, in the semiconductor device 10C, integrated circuits 100A and 100B can be bonded face-to-face via a bonding layer 210. In such an embodiment, the bonding layer 210 can be formed on at least one of the integrated circuits 100A and 100B. For example, as Figure 6 As shown, bonding layer 210A is formed on integrated circuit 100A, bonding layer 210B is formed on integrated circuit 100B, and bonding layers 210A and 210B are bonded to each other. Bonding layers 210A and 210B are...Figure 1G The bonding layer 210 is similar and will not be described again here. In some embodiments, such as Figure 6 As shown, the bonding pads 212A and 212B in bonding layers 210A and 210B can be bonded to each other. However, the present invention is not limited thereto. In alternative embodiments, one of bonding layers 210A and 210B may be omitted. Figure 7 As shown, only a bonding layer 210A is disposed between integrated circuits 100A and 100B. Alternatively, integrated circuit 100A may be similar to integrated circuit 100A', and / or integrated circuit 100B may be similar to integrated circuit 100B', to improve heat dissipation.

[0061] In an alternative embodiment, in a semiconductor device including an integrated circuit, at least one of the etch stop layer and the thermal pattern is formed of a thermally conductive material (TDM), and / or at least one of the dielectric layers is formed of a BCN-based material. In an alternative embodiment, in a semiconductor device including a bonded integrated circuit, at least one of the bonding layer, the etch stop layer, and the thermal pattern is formed of a thermally conductive material (TDM), and / or at least one of the dielectric layers is formed of a BCN-based material.

[0062] Figure 8 A flowchart of a method for forming a semiconductor device according to the present disclosure is shown. Although the method is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than those shown and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed at individual times or simultaneously with other actions or sub-actions. In some embodiments, some of the stated actions or events may be omitted, and other actions or events not shown may be included.

[0063] At action 300, multiple layers are formed, and the multiple layers include multiple interleaved aluminum nitride layers and multiple aluminum oxide layers or multiple interleaved aluminum nitride layers and multiple aluminum oxynitride layers. Figure 3A Cross-sectional views corresponding to some embodiments of action 300 are shown.

[0064] At action 302, multiple conductive patterns are formed in the multilayer. Figure 3C Cross-sectional views corresponding to some embodiments of action 302 are shown.

[0065] At action 304, multiple layers are patterned to form at least one heat dissipation pattern. Figure 3D Cross-sectional views corresponding to some embodiments of action 304 are shown.

[0066] At action 306, a dielectric layer is formed next to the conductive pattern and at least one heat dissipation pattern. Figure 3ECross-sectional views corresponding to some embodiments of action 306 are shown.

[0067] According to some embodiments of the present invention, a semiconductor device includes a first integrated circuit, a second integrated circuit, and a bonding layer. The bonding layer is located between the first integrated circuit and the second integrated circuit, wherein the bonding layer includes a first layer and a second layer, the first layer being an aluminum nitride (AlN) layer, and the second layer being one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer.

[0068] According to some embodiments of the present invention, the thickness difference between the first layer and the second layer is between about 40 angstroms and about 90 angstroms.

[0069] According to some embodiments of the present invention, the first layer includes a plurality of first layers, the second layer includes a plurality of second layers, and the plurality of first layers and the plurality of second layers are interleaved.

[0070] According to some embodiments of the present invention, the bonding layer is in direct contact with the first integrated circuit and the second integrated circuit.

[0071] According to some embodiments of the present invention, the bonding layer directly contacts the dielectric layer of the interconnect structure of the first integrated circuit and the semiconductor substrate of the second integrated circuit.

[0072] According to some embodiments of the present invention, the aluminum nitride (AlN) layer is a crystalline aluminum nitride (AlN) layer.

[0073] According to some embodiments of the present invention, a semiconductor device includes an interconnect structure. The interconnect structure includes multiple dielectric layers, multiple conductive patterns, and at least one heat dissipation pattern. The at least one heat dissipation pattern includes a first layer and a second layer, wherein the first layer is an aluminum nitride (AlN) layer, and the second layer is one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer.

[0074] According to some embodiments of the present invention, the first layer is in direct contact with the second layer.

[0075] According to some embodiments of the present invention, at least one of the plurality of dielectric layers comprises a boron carbon nitride (BCN)-based material.

[0076] According to some embodiments of the present invention, at least one heat dissipation pattern includes multiple interlaced first layers and multiple second layers.

[0077] According to some embodiments of the present invention, the interconnect structure further includes an etch stop layer located below one of the plurality of dielectric layers, wherein the etch stop layer includes the first layer and the second layer.

[0078] According to some embodiments of the present invention, at least one of the plurality of conductive patterns is in direct contact with the etch stop layer.

[0079] According to some embodiments of the present invention, at least one heat dissipation pattern is in direct contact with the etch stop layer.

[0080] According to some embodiments of the present invention, the interconnect structure further includes an etch stop layer beneath one of the plurality of dielectric layers, wherein the etch stop layer comprises a plurality of interleaved first layers and a plurality of second layers.

[0081] According to some embodiments of the present invention, at least one heat dissipation pattern is disposed between two adjacent pairs of the plurality of conductive patterns.

[0082] According to some embodiments of the present invention, the aluminum nitride (AlN) layer is a crystalline aluminum nitride (AlN) layer.

[0083] According to some embodiments of the present invention, a method for forming a semiconductor device includes the following steps: forming a multilayer, the multilayer comprising a plurality of interleaved aluminum nitride layers and a plurality of aluminum oxide layers, or a plurality of interleaved aluminum nitride layers and a plurality of aluminum oxynitride layers; forming a plurality of conductive patterns in the multilayer; patterning the multilayer to form at least one heat dissipation pattern; and forming a dielectric layer adjacent to the conductive patterns and the at least one heat dissipation pattern.

[0084] According to some embodiments of the present invention, forming the multilayer includes performing multiple process cycles, and each cycle includes: depositing an aluminum nitride layer; and processing the aluminum nitride layer to convert the top of the aluminum nitride layer into an aluminum oxide layer or an aluminum oxynitride layer.

[0085] According to some embodiments of the present invention, the aluminum nitride layer is subjected to plasma treatment with nitrous oxide (N2O).

[0086] According to some embodiments of the present invention, processing the aluminum nitride layer includes exposing the aluminum nitride layer to ultraviolet (UV) radiation in the presence of argon (Ar) or helium (He).

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: a first integrated circuit and a second integrated circuit; and a bonding layer between the first integrated circuit and the second integrated circuit, wherein the bonding layer comprises a first layer and a second layer, the first layer is an aluminum nitride layer, and the second layer is one of an aluminum oxide layer and an aluminum oxynitride layer.

2. The semiconductor device of claim 1, wherein a thickness difference between the first layer and the second layer is between 40 angstroms and 90 angstroms.

3. The semiconductor device of claim 1, wherein the first layer comprises a plurality of first layers, the second layer comprises a plurality of second layers, and the plurality of first layers are interleaved with the plurality of second layers.

4. The semiconductor device of claim 1, wherein the bonding layer is in direct contact with the first integrated circuit and the second integrated circuit.

5. The semiconductor device of claim 1, wherein the bonding layer is in direct contact with a dielectric layer of an interconnect structure of the first integrated circuit and a semiconductor substrate of the second integrated circuit.

6. The semiconductor device of claim 1, wherein the aluminum nitride layer is a crystalline aluminum nitride layer.

7. A semiconductor device, comprising: an interconnect structure comprising a plurality of dielectric layers, a plurality of conductive patterns, and at least one thermal dissipation pattern, wherein the at least one thermal dissipation pattern comprises a first layer and a second layer, the first layer is an aluminum nitride layer, and the second layer is one of an aluminum oxide layer and an aluminum oxynitride layer.

8. The semiconductor device of claim 7, wherein the first layer is in direct contact with the second layer.

9. The semiconductor device of claim 7, wherein a material of at least one of the plurality of dielectric layers comprises a boron-carbon-nitride based material.

10. The semiconductor device of claim 7, wherein the at least one thermal dissipation pattern comprises a plurality of first layers interleaved with a plurality of second layers. ​

Images