Multi-channel voltage detection system
The modularly designed multi-channel voltage detection system solves the problem of poor flexibility in detecting multiple chips in existing technologies, and achieves efficient, flexible and accurate detection of multiple chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies for testing multiple chips require separate design of peripheral circuits and involve frequent desoldering and cumbersome operations, resulting in poor testing flexibility.
The modularly designed multi-channel voltage detection system includes a module under test and a test module. It uses a signal selector, a main control chip, and a signal conversion chip to process and convert signals from multiple chips. Combined with peripheral test circuits, it simulates the actual working environment and improves the flexibility of detection.
It enables simultaneous testing of multiple chips, improving testing efficiency and flexibility, and ensuring accurate signal transmission and test results.
Smart Images
Figure CN223992931U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a multi-channel voltage detection system. Background Technology
[0002] In order to avoid the problem of output voltage drift during chip manufacturing and use, the chip needs to be tested.
[0003] In related technologies, chip testing methods often involve designing corresponding peripheral circuits for the chip, then installing and embedding the chip into the peripheral circuits for testing. However, in practical applications, multiple chips are often used simultaneously, requiring testing of all of them. The existing testing methods not only require the separate design of peripheral circuits but also involve frequent desoldering and cumbersome operations when testing each chip individually, resulting in poor testing flexibility. Utility Model Content
[0004] To address the shortcomings of existing technologies, the multi-channel voltage detection system provided in this application adopts a modular design, which enables simultaneous detection of multiple chips and offers greater flexibility.
[0005] The above-mentioned inventive objective of this application is achieved through the following technical solutions:
[0006] This application provides a multi-channel voltage detection system, the system including a module under test and a test module, wherein:
[0007] The module under test is connected to multiple chips under test and is used to acquire first test signals from the multiple chips under test.
[0008] The test module is connected to the module under test and is used to select a second test signal from the first test signal and transmit the serial port test signal obtained by converting the second test signal to the host computer, so that the host computer can display the voltage test value corresponding to the chip under test through the Qt interface.
[0009] By adopting the above technical solution, the detection system employs a modular design, enabling the connection of multiple chips under test and the acquisition of their initial test signals. This achieves the acquisition of signals from multiple chips, meeting the requirement of simultaneously testing multiple chips. The testing module processes the signals, extracts valid information, converts and transmits it to the host computer for display, achieving accurate signal detection. The system's modular and configurable design enhances flexibility, facilitating the replacement and expansion with different chips. Compared to existing technologies, this system, through its modular design, can simultaneously test multiple chips, offering greater flexibility.
[0010] In a preferred embodiment, this application can be further configured as follows: the test module includes at least one signal selector, a main control chip, and a signal conversion chip, wherein: the signal selector is connected to multiple chips under test via the module under test, and is used to perform preliminary selection of the first test signal and output a transitional test signal; the main control chip is connected to the signal selector and is used to perform secondary selection of the transitional test signal and output a second test signal; the signal conversion chip is used to convert the second test signal into the serial port test signal and transmit the serial port test signal to the host computer.
[0011] By adopting the above technical solution, the signal selector connects multiple chips under test (DUTs), performs preliminary selection of the first test signal, and outputs a transitional test signal to manage complex multi-channel signals and prevent collisions. The main control chip further selects and extracts effective information from the transitional test signal to generate a simplified second test signal, improving signal availability. The signal conversion chip converts the second test signal into a standard serial port signal, ensuring reliable signal transmission to the host computer. Compared to directly transmitting the original signal, the three components working together form a multi-stage signal processing system that improves the accuracy of the test results.
[0012] In a preferred embodiment, this application may be further configured such that: the signal selector is a 74HC4067 selector, the input pin of the signal selector is connected to a plurality of chips under test via the module under test, and the control pin of the signal selector is connected to the main control chip.
[0013] In a preferred embodiment, this application may be further configured such that the main control chip is a C8051F060 chip, used to sample, quantize and digitally encode the transition test signal, and output the second test signal.
[0014] In a preferred embodiment, this application may be further configured such that the signal conversion chip is a MAX232 chip.
[0015] In a preferred embodiment, the present application may be further configured such that the test module further includes a power supply chip for supplying power to the main control chip, wherein the power supply chip is a MAX1818 chip.
[0016] In a preferred embodiment, this application can be further configured such that: the module under test further includes peripheral test circuitry corresponding to the chip under test, wherein:
[0017] The peripheral test circuit includes an input terminal, an output terminal, and a ground terminal. The input terminal and the output terminal of the peripheral test circuit are connected to the test module, and the ground terminal of the peripheral test circuit is grounded.
[0018] By adopting the above technical solution, the peripheral test circuit can accurately simulate the actual working environment of the chip, optimize test conditions, and improve detection accuracy. Compared with directly testing the original chip, adding peripheral circuits to the module under test enables customized testing, which helps to obtain more accurate results. Meanwhile, the standard three-terminal interface ensures compatibility and security. Compared with changing the entire test module, this solution, by adding peripheral circuits to the module under test, achieves customized testing for different chip types, improving the system's flexibility.
[0019] In a preferred embodiment, this application can be further configured as follows: the chip under test is an LM723 chip, and the peripheral test circuit corresponding to the chip under test includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a thermistor, a first capacitor, and a second capacitor, wherein:
[0020] The input terminals of the peripheral test circuit are respectively connected to the positive power supply pin and the collector power supply pin of the chip under test.
[0021] The output terminal of the peripheral test circuit is connected to the output pin of the chip under test and the current limiting sensing output pin via the fourth resistor. The output terminal of the peripheral test circuit is connected to the current sensing pin. The output terminal of the peripheral test circuit is connected to the frequency compensation pin of the chip under test via the third resistor and the second capacitor. The output terminal of the peripheral test circuit and the output terminal of the chip under test are connected to the inverting input pin of the chip under test via the third resistor.
[0022] The inverting input pin of the chip under test is connected to the ground terminal via the second resistor;
[0023] The non-inverting input pin of the chip under test is connected to the ground terminal via the fifth resistor and the thermistor in series. One end of the first capacitor is connected to the fifth resistor and the thermistor respectively, and the other end of the first capacitor is connected to the ground terminal.
[0024] The reference voltage output pin of the chip under test is grounded through the sixth resistor, the first resistor and the seventh resistor in series. The first resistor is a variable resistor and its resistance adjustment terminal is connected to the non-inverting input pin of the chip under test.
[0025] The ground terminal of the chip under test is connected to the ground terminal of the peripheral test circuit.
[0026] By adopting the above technical solution, a dedicated peripheral test circuit design for the LM723 chip provides a scalable template for testing other types of voltage regulator chips. Through appropriate modifications to component values and connections, this design can be adapted to the specific needs of other chip types, improving system flexibility. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the structure of a multi-channel voltage detection system provided in an embodiment of this application;
[0028] Figure 2 This is a schematic diagram of the Qt interface of a multi-channel voltage detection system provided in an embodiment of this application;
[0029] Figure 3 This is a schematic diagram of the structure of a peripheral circuit under test provided in an embodiment of this application.
[0030] Reference numerals in the attached diagram: R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; RT1, thermistor; C1, first capacitor; C2, second capacitor. Detailed Implementation
[0031] The present application will be further described in detail below with reference to the accompanying drawings.
[0032] Reference Figure 1 This is a schematic diagram of a multi-channel voltage detection system provided in an embodiment of this application. The system includes a module under test and a test module, wherein:
[0033] The module under test is connected to multiple chips under test and is used to acquire first test signals from the multiple chips under test.
[0034] The test module is connected to the module under test and is used to select a second test signal from the first test signal and transmit the serial port test signal obtained by converting the second test signal to the host computer, so that the host computer can display the voltage test value corresponding to the chip under test through the Qt interface.
[0035] In this embodiment, the multi-channel voltage detection system includes a module under test (DUT) and a test module. These two modules work together to simultaneously detect multiple DUT chips. The DUT is directly connected to multiple DUT chips to acquire their initial test signals. This design allows the system to connect to and monitor multiple DUT chips simultaneously, significantly improving testing efficiency. The initial test signals acquired by the DUT contain the raw voltage information of all DUT chips, laying the foundation for subsequent signal processing and analysis.
[0036] The test module is connected to the module under test (DUT), and its main function is to process and convert the first test signal. The test module first selects a second test signal from the first test signal. The system focuses on a specific chip or channel among multiple DUTs to achieve targeted testing. The selection process involves signal multiplexing or selection techniques to ensure that the system can efficiently process multiple input signals.
[0037] Subsequently, the test module converts the selected second test signal into a serial port test signal, which is then transmitted to the host computer. The host computer can be a computer or other device with data processing capabilities. Through serial communication, the system achieves efficient and reliable data transmission between the test module and the host computer. After receiving the serial port test signal, the host computer displays the corresponding voltage test value of the chip under test through a pre-designed Qt interface. Through the visual Qt interface, testers can quickly understand the voltage status of each chip under test, facilitating real-time monitoring and data comparison.
[0038] Based on the above embodiments, as an optional implementation, the test module includes at least one signal selector, a main control chip, and a signal conversion chip, wherein:
[0039] The signal selector is connected to multiple chips under test via the module under test, and is used to perform preliminary selection of the first test signal and output a transition test signal.
[0040] The main control chip is connected to the signal selector and is used to perform secondary selection on the transition test signal and output a second test signal.
[0041] The signal conversion chip is used to convert the second test signal into the serial port test signal and transmit the serial port test signal to the host computer.
[0042] The signal selector was introduced to address the signal conflicts and low processing efficiency that can occur when simultaneously monitoring multiple chips under test (DUTs). When a system needs to monitor multiple DUTs simultaneously, the initial test signals from all chips are transmitted to the DUT at the same time. Directly transmitting these signals to subsequent processing units would not only increase the complexity of signal processing but could also lead to signal interference and data loss. Therefore, using a signal selector for initial selection effectively manages and controls the signal flow, ensuring that the system can process signals from different DUTs in an orderly manner.
[0043] In practical implementation, the signal selector uses multiplexing technology to initially select the first test signal. The transition test signal output by the signal selector is a pre-selected and processed signal. It can select one or more signals from multiple input channels for output based on preset selection logic or external control signals. For example, if using a 74HC4067 selector, it can connect 16 input channels simultaneously and select one channel for output via a 4-bit control signal. This design allows the system to focus on a specific chip under test at any given time, enabling polling testing of multiple chips or on-demand selection.
[0044] The necessity for the main control chip to perform secondary selection on the transition test signal stems from the system's requirements for high precision and flexibility. Although the signal selector has completed the initial selection, the transition test signal may still contain information from multiple channels or contain redundant data. Through secondary selection by the main control chip, the system can more precisely control the signal processing, achieving a higher level of signal filtering and optimization. This secondary selection mechanism allows the system to dynamically adjust the test strategy according to real-time requirements, improving the relevance and efficiency of the test.
[0045] In practice, the main control chip first receives the transition test signal from the signal selector. The analog-to-digital converter inside the main control chip converts the analog transition test signal into a digital signal for subsequent digital processing. Then, the main control chip further filters and processes the digitized signal according to a preset algorithm or external instructions. This may include signal filtering, data compression, and feature extraction. Through these operations, the main control chip can extract the most critical and valuable information from the transition test signal, forming the second test signal. The second test signal output by the main control chip is a high-quality signal that has undergone comprehensive processing and optimization. Compared to the transition test signal, the second test signal has a higher signal-to-noise ratio, stronger representativeness, and better analyzability.
[0046] The converted serial port test signal is transmitted to the host computer through a standard serial interface. Since the second test signal output by the main control chip is typically based on a specific digital logic level, and the host computer usually requires a standard serial communication interface to receive data, the signal conversion chip enables the system to convert between different signal standards, ensuring that the data can be correctly received and parsed by the host computer.
[0047] Specifically, such as Figure 1As shown in the figure, a 74HC4067 signal selector is illustrated. The input pins of the signal selector are connected to multiple chips under test (DUTs) via the DUT module, and the control pins of the signal selector are connected to the main control chip. The main control chip is a C8051F060 chip, used to sample, quantize, and digitally encode the transition test signal, outputting the second test signal. The signal conversion chip is a MAX232 chip. Qt represents the Qt interface of the host computer.
[0048] The system specifically employs a 74HC4067 selector as the signal selector, a C8051F060 chip as the main control chip, and a MAX232 chip as the signal conversion chip. Visualization is achieved using a Qt interface on a host computer. The 74HC4067 selector has 16 input channels, enabling simultaneous connection to multiple chips under test (DUTs), meeting the system's multi-channel detection requirements. The selector's input pins are connected to multiple DUTs via the DUT module; this design allows the system to monitor the voltage status of multiple chips simultaneously. The selector's control pins are connected to the main control chip C8051F060, enabling the main control chip to precisely control the signal selection process.
[0049] The C8051F060 chip integrates a high-precision ADC, enabling precise sampling, quantization, and digital encoding conversion of the transient test signal output from the 74HC4067. This process converts analog signals into digital signals, facilitating subsequent processing and transmission. The high-performance processing core of the C8051F060 chip also allows for the implementation of complex signal processing algorithms, such as filtering and calibration, further improving test accuracy.
[0050] The MAX232 chip solves the signal level conversion problem. This chip can convert the TTL / CMOS level signals output by the C8051F060 into RS-232 compliant level signals. This conversion process not only ensures signal compatibility but also enhances signal transmission capability and anti-interference ability. The serial port test signal output by the MAX232 chip can communicate directly with the host computer via a standard serial port, simplifying system interface design and improving data transmission reliability.
[0051] On the host computer side, the use of the Qt interface for visualization is based on its cross-platform compatibility and powerful graphics processing capabilities. The Qt interface can intuitively display the serial port test signals received from the MAX232 chip, converting digital signals into graphical or numerical forms that are easy for users to understand.
[0052] For details, please see Figure 2This is a schematic diagram of the Qt interface of a multi-channel voltage detection system provided in an embodiment of this application. The diagram specifically includes a serial port setting area, a status reading area, and a voltage display area.
[0053] The serial port settings area includes drop-down menus for serial port and baud rate, allowing users to select the desired serial port and baud rate. The status read area displays the CAN address of the main control chip, the time interval for setting the status read interval, and Umax represents the maximum voltage value, showing the maximum voltage of the chip under test in a given state. The voltage display area shows the voltage values for each channel of the chip under test.
[0054] When the system actually starts, it first initializes the Qt interface, ensuring that all UI elements (such as buttons, text boxes, etc.) are displayed correctly. Then, it detects which serial port devices are available on the computer (such as USB serial ports, virtual serial ports, etc.) and adds these port names to the serial port dropdown menu (comboBox_comName). Users can then select the desired serial port device. Next, a serial communication object, uartCom, is created, which manages and handles the actual serial communication (such as opening the serial port, sending and receiving data). When the user clicks the "Open Serial Port" button on the interface, the connected slot function attempts to open the selected serial port and begin reading data. The raw data received from the serial port is then converted into a visual structure, which is then displayed on the Qt interface.
[0055] In one optional implementation, the test module further includes a power supply chip for supplying power to the main control chip, wherein the power supply chip is a MAX1818 chip.
[0056] The MAX1818 is a high-performance low-dropout linear regulator (LDO) that provides a stable, low-noise power output. In practical implementations, the MAX1818 chip is connected to the C8051F060 main control chip through a well-designed circuit. Typically, the input of the MAX1818 is connected to the system's main power supply, while its output directly provides the required stable voltage to the C8051F060.
[0057] Based on the above embodiments, in order to realize the modular structure of the module under test and improve the flexibility of the system, as an optional implementation, the module under test further includes a peripheral test circuit corresponding to the chip under test, wherein:
[0058] The peripheral test circuit includes an input terminal, an output terminal, and a ground terminal. The input terminal and the output terminal of the peripheral test circuit are connected to the test module, and the ground terminal of the peripheral test circuit is grounded.
[0059] The introduction of peripheral test circuitry is based on considerations of the complexity of real-world testing environments. In practical applications, different types of chips under test (DUTs) may require different test conditions and circuit configurations. By equipping each DUT with dedicated peripheral test circuitry, the system can better simulate the chip's actual operating environment and provide more accurate test results. This design allows the system to perform customized testing for different types of chips without altering the overall structure of the test module.
[0060] In practical implementation, the peripheral test circuit includes an input terminal, an output terminal, and a ground terminal. The input terminal is connected to the power supply to provide power; the output terminal is connected to the test module to transmit the test results back to the test module; and the ground terminal is directly grounded to ensure the stability and safety of the circuit. This three-terminal design provides a clear signal flow and power path, which is beneficial to signal integrity and measurement accuracy.
[0061] Based on the above embodiments, as an optional implementation method, please refer to... Figure 3 This is a schematic diagram of the structure of a peripheral circuit under test provided in an embodiment of this application. The chip under test is an LM723 chip. The peripheral test circuit corresponding to the chip under test includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a thermistor, a first capacitor, and a second capacitor, wherein:
[0062] The input terminals of the peripheral test circuit are respectively connected to the positive power supply pin and the collector power supply pin of the chip under test.
[0063] The output terminal of the peripheral test circuit is connected to the output pin of the chip under test and the current limiting sensing output pin via the fourth resistor. The output terminal of the peripheral test circuit is connected to the current sensing pin. The output terminal of the peripheral test circuit is connected to the frequency compensation pin of the chip under test via the third resistor and the second capacitor. The output terminal of the peripheral test circuit and the output terminal of the chip under test are connected to the inverting input pin of the chip under test via the third resistor.
[0064] The inverting input pin of the chip under test is connected to the ground terminal via the second resistor;
[0065] The non-inverting input pin of the chip under test is connected to the ground terminal via the fifth resistor and the thermistor in series. One end of the first capacitor is connected to the fifth resistor and the thermistor respectively, and the other end of the first capacitor is connected to the ground terminal.
[0066] The reference voltage output pin of the chip under test is grounded through the sixth resistor, the first resistor and the seventh resistor in series. The first resistor is a variable resistor and its resistance adjustment terminal is connected to the non-inverting input pin of the chip under test.
[0067] The ground terminal of the chip under test is connected to the ground terminal of the peripheral test circuit.
[0068] For LM723 chips under test from different packages and manufacturers, the peripheral test circuit consists of seven resistors (resistors one through seven), one thermistor, and two capacitors (capacitors one and two). This careful configuration of components not only simulates the typical application environment of the LM723 but also provides the ability to adjust and test its key parameters.
[0069] The inputs of the peripheral test circuit are connected to the positive and collector power pins of the LM723, ensuring the chip receives proper power. The output design is more complex, connecting to the LM723's output pin and current-limiting sensing output pin via a fourth resistor. This allows the system to monitor the chip's output voltage and current-limiting functionality. The output is also directly connected to the current-sensing pin for evaluating the chip's current-sensing capability. The design, connecting the frequency compensation pin via a third resistor and a second capacitor, allows the system to test and optimize the chip's frequency response characteristics. The output is connected to the inverting input pin via a third resistor, while the inverting input pin is grounded via a second resistor; this configuration allows the system to test and adjust the chip's feedback characteristics. A combination of a fifth resistor, a thermistor, and a first capacitor provides fine-grained control and filtering of the input signal. A series combination of a sixth resistor, a first resistor (variable resistor), and a seventh resistor not only tests the accuracy of the reference voltage but also simulates different load conditions by adjusting the first resistor. The adjustment terminal of the first resistor is connected to the non-inverting input pin; this design allows the system to dynamically adjust input conditions to comprehensively evaluate the chip's response characteristics.
[0070] By selecting appropriate resistor and capacitor values, the peripheral circuitry can minimize measurement errors and provide more accurate test results. Furthermore, the modular design allows this complex test circuit to function as a standalone unit, facilitating replacement and maintenance, which significantly improves the system's flexibility and maintainability.
[0071] The embodiments described herein are preferred embodiments of this utility model and are not intended to limit the scope of protection of this utility model. Therefore, all equivalent changes made to the structure, shape, and principle of this utility model should be included within the scope of protection of this utility model.
Claims
1. A multi-channel voltage detection system, characterized by, The system comprises a to-be-tested module and a test module, wherein: The to-be-tested module is connected with a plurality of to-be-tested chips, and is configured to acquire first test signals of the plurality of to-be-tested chips; The test module is connected with the to-be-tested module, and is configured to select second test signals from the first test signals, and transmit serial port test signals converted from the second test signals to an upper computer, so that the upper computer displays voltage test values corresponding to the to-be-tested chips through a Qt interface.
2. The multi-channel voltage detection system of claim 1, wherein, The test module comprises at least one signal selector, a master control chip and a signal conversion chip, wherein: The signal selector is connected with the plurality of to-be-tested chips through the to-be-tested module, and is configured to preliminarily select the first test signals and output transition test signals; The master control chip is connected with the signal selector, and is configured to secondarily select the transition test signals and output the second test signals; The signal conversion chip is configured to convert the second test signals into the serial port test signals, and transmit the serial port test signals to the upper computer.
3. The multi-channel voltage detection system of claim 2, wherein, The signal selector is a 74HC4067 selector, input pins of the signal selector are connected with the plurality of to-be-tested chips through the to-be-tested module, and control pins of the signal selector are connected with the master control chip.
4. The multi-channel voltage detection system of claim 2, wherein, The master control chip is a C8051F060 chip, and is configured to realize sampling, numerical quantization and digital encoding conversion of the transition test signals, and output the second test signals.
5. The multi-channel voltage detection system of claim 2, wherein, The signal conversion chip is a MAX232 chip.
6. The multi-channel voltage detection system of claim 2, wherein, The test module further comprises a power supply chip for supplying power to the master control chip, and the power supply chip is a MAX1818 chip.
7. The multi-channel voltage detection system of claim 1, wherein, The to-be-tested module further comprises a peripheral test circuit corresponding to the to-be-tested chip, wherein: The peripheral test circuit comprises an input end, an output end and a grounding end, the input end and the output end of the peripheral test circuit are connected with the test module, and the grounding end of the peripheral test circuit is grounded.
8. The multi-channel voltage detection system of claim 7, wherein, The to-be-tested chip is an LM723 chip, and the peripheral test circuit corresponding to the to-be-tested chip comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a thermistor, a first capacitor and a second capacitor, wherein: The input end of the peripheral test circuit is connected with a positive power supply pin and a collector power supply pin of the to-be-tested chip respectively; The output end of the peripheral test circuit is connected with an output pin and a current limiting sensing output pin of the to-be-tested chip through the fourth resistor respectively, the output end of the peripheral test circuit is connected with the current sensing pin, the output end of the peripheral test circuit is connected to a frequency compensation pin of the to-be-tested chip through the third resistor and the second capacitor, and the output end of the peripheral test circuit is connected to a reverse input pin of the to-be-tested chip through the third resistor; The reverse input pin of the to-be-tested chip is connected with the grounding end through the second resistor. The in-phase input pin of the to-be-tested chip is connected with the ground terminal in series through the fifth resistor and the thermistor, one end of the first capacitor is connected with the fifth resistor and the thermistor respectively, and the other end of the first capacitor is connected with the ground terminal; The reference voltage output pin of the to-be-tested chip is connected with the ground terminal in series through the sixth resistor, the first resistor and the seventh resistor, the first resistor is a variable resistor, and the resistance adjusting end of the first resistor is connected with the in-phase input pin of the to-be-tested chip; The ground terminal of the to-be-tested chip is connected with the ground terminal of the peripheral test circuit.