Control circuit for preventing power-on and power-off time sequence abnormity

Abstract

The utility model relates to the technical field of power supplies, in particular to a control circuit for preventing power-on and power-off time sequence abnormity, which comprises a first power supply input end, a second power supply input end, a first power supply circuit, a second power supply circuit, a voltage limiting circuit and a main control circuit, through the voltage limiting circuit, the voltage can be quickly responded and clamped, overvoltage damage is prevented, sensitive electronic elements are protected from being influenced by transient high-voltage pulses, and therefore the safety and stability of the whole system are enhanced; meanwhile, charging and discharging control is carried out on the first power supply circuit and the second power supply circuit through the first RC delay filter circuit and the second RC delay filter circuit respectively, it is ensured that different power supplies are powered on and powered off according to a preset sequence, and the stability and reliability of the system are improved. According to the design, the overall design is simple, the number of needed elements and the layout space are reduced, the manufacturing cost is reduced, meanwhile, the functions of other circuits are not affected, and the system is more compact and efficient.

Description

Technical Field

[0001] This utility model relates to the field of power supply technology, specifically to a control circuit for preventing abnormal power-on and power-off timing. Background Technology

[0002] The application of multi-power integrated circuits (ICs) is becoming increasingly widespread in modern electronic devices. These ICs not only undertake complex data processing tasks, but also need to manage the timing of multiple power supplies simultaneously to ensure the safety and stability of the entire system during power-on and power-off. However, existing power-on / power-off timing control circuits suffer from insecurity and instability during power-on and power-off, as well as complex circuit structures. Utility Model Content

[0003] This invention addresses the shortcomings and deficiencies of existing technologies by providing a control circuit with a simple circuit structure to prevent abnormal power-on / off timing.

[0004] To achieve the above objectives, the present invention provides a control circuit for preventing abnormal power-on / off timing, comprising a first power input terminal, a second power input terminal, a first power supply circuit, a second power supply circuit, a voltage limiting circuit, a main control circuit, a first RC delay filter circuit, and a second RC delay filter circuit. The first power input terminal is electrically connected to the first power supply circuit, the second power input terminal is electrically connected to the second power supply circuit, the first power supply circuit is electrically connected to the first RC delay filter circuit, and the second power supply circuit is electrically connected to the second RC delay filter circuit. The main control circuit is electrically connected to the voltage limiting circuit, the first RC delay filter circuit, and the second RC delay filter circuit, and the first RC delay filter circuit and the second RC delay filter circuit are electrically connected to the voltage limiting circuit.

[0005] Furthermore, the voltage limiting circuit includes a first clamping diode and a second clamping diode; the first clamping diode and the second clamping diode are connected in reverse series, one end of which is electrically connected to the first RC delay filter circuit, and the other end of which is electrically connected to the second RC delay filter circuit; the common terminal of the first clamping diode and the second clamping diode is electrically connected to the GPIO pin of the main control circuit.

[0006] Furthermore, the first RC delay filter circuit includes a first resistor and a first capacitor; the first resistor and the first capacitor are connected in series, one end of which is electrically connected to the GPIO pin of the main control circuit, and the other end is grounded; the common terminal of the first resistor and the first capacitor is electrically connected to the first clamping diode; and the first resistor is electrically connected to the second RC delay filter circuit.

[0007] Furthermore, the second RC delay filter circuit includes a second resistor and a second capacitor; the second resistor and the second capacitor are connected in series, one end of which is electrically connected to the first resistor, and the other end is grounded; the common terminal of the second resistor and the second capacitor is electrically connected to the second clamping diode.

[0008] Furthermore, the first power supply circuit includes a first power management chip, a third resistor, a third capacitor, and a fourth capacitor; the first pin of the first power management chip is electrically connected to the first power input terminal; one end of the third capacitor is grounded, and the other end is electrically connected to the first pin of the first power management chip; the second pin of the first power management chip is grounded; one end of the third resistor is electrically connected to the third pin of the first power management chip, and the other end is electrically connected to the first capacitor; one end of the fourth capacitor is grounded, and the other end is electrically connected to the fifth pin of the first power management chip.

[0009] Further, the second power supply circuit includes a second power management chip, an inductor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a fourth resistor, a fifth resistor, and a sixth resistor; one end of the fourth resistor is electrically connected to the fourth pin of the second power management chip, and the other end is electrically connected to the second capacitor; the fifth pin of the second power management chip is electrically connected to the second power input terminal; one end of the fifth capacitor is grounded, and the other end is electrically connected to the fifth pin of the second power management chip; one end of the sixth capacitor is grounded, and the other end is electrically connected to the fifth pin of the second power management chip. The second pin of the second power management chip is grounded; one end of the seventh capacitor is electrically connected to the first pin of the second power management chip, and the other end is electrically connected to the inductor; the inductor and the eighth capacitor are connected in series, one end is grounded, and the other end is electrically connected to the sixth pin of the second power management chip; the ninth capacitor and the tenth capacitor are connected in parallel, one end is grounded, and the other end is electrically connected to the eighth capacitor; the eleventh capacitor and the fifth resistor are connected in parallel, one end is electrically connected to the tenth capacitor, and the other end is electrically connected to the third pin of the second power management chip; one end of the sixth resistor is electrically connected to the fifth resistor, and the other end is grounded.

[0010] The beneficial effects of this utility model are:

[0011] This invention provides a control circuit to prevent abnormal power-on / off timing. Through a voltage limiting circuit, it can quickly respond to and clamp the voltage, preventing overvoltage damage and protecting sensitive electronic components from transient high-voltage pulses, thereby enhancing the safety and stability of the entire system. Simultaneously, through a first RC delay filter circuit and a second RC delay filter circuit, it controls the charging and discharging of the first and second power supply circuits respectively, ensuring that different power supplies are powered on and off in a predetermined sequence, improving the system's stability and reliability. The design of this application is not only simple in overall design, reducing the number of required components and layout space, and lowering manufacturing costs, but also does not affect the function of other circuits, making the system more compact and efficient. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the working principle of a control circuit for preventing abnormal power-on / off timing according to this utility model.

[0013] Figure 2 This is a circuit diagram of a voltage limiting circuit, a first RC delay filter circuit, and a second RC delay filter circuit in a control circuit for preventing abnormal power-on / off timing according to this utility model.

[0014] Figure 3 This is a circuit diagram of the first power supply circuit in a control circuit for preventing abnormal power-on / off timing according to the present invention.

[0015] Figure 4 This is a circuit diagram of the second power supply circuit in a control circuit for preventing abnormal power-on / off timing according to this utility model. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0017] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0018] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0019] This invention proposes a control circuit to prevent abnormal power-on / off timing.

[0020] In the embodiments of this utility model, such as Figure 1-4 As shown, a control circuit for preventing abnormal power-on / off timing includes a first power input terminal, a second power input terminal, a first power supply circuit, a second power supply circuit, a voltage limiting circuit, a main control circuit, a first RC delay filter circuit, and a second RC delay filter circuit. The first power input terminal is electrically connected to the first power supply circuit, the second power input terminal is electrically connected to the second power supply circuit, the first power supply circuit is electrically connected to the first RC delay filter circuit, and the second power supply circuit is electrically connected to the second RC delay filter circuit. The main control circuit is electrically connected to the voltage limiting circuit, the first RC delay filter circuit, and the second RC delay filter circuit, and the first RC delay filter circuit and the second RC delay filter circuit are electrically connected to the voltage limiting circuit.

[0021] In this embodiment, the voltage limiting circuit includes a first clamping diode and a second clamping diode; the first clamping diode and the second clamping diode are connected in reverse series, one end of which is electrically connected to the first RC delay filter circuit, and the other end of which is electrically connected to the second RC delay filter circuit; the common terminal of the first clamping diode and the second clamping diode is electrically connected to the GPIO pin of the main control circuit.

[0022] In this embodiment, the first RC delay filter circuit includes a first resistor and a first capacitor; the first resistor and the first capacitor are connected in series, one end of which is electrically connected to the GPIO pin of the main control circuit, and the other end is grounded; the common terminal of the first resistor and the first capacitor is electrically connected to the first clamping diode; and the first resistor is electrically connected to the second RC delay filter circuit.

[0023] In this embodiment, the second RC delay filter circuit includes a second resistor and a second capacitor; the second resistor and the second capacitor are connected in series, one end of which is electrically connected to the first resistor, and the other end is grounded; the common terminal of the second resistor and the second capacitor is electrically connected to the second clamping diode.

[0024] In this embodiment, the first power supply circuit includes a first power management chip, a third resistor, a third capacitor, and a fourth capacitor; the first pin of the first power management chip is electrically connected to the first power input terminal; one end of the third capacitor is grounded, and the other end is electrically connected to the first pin of the first power management chip; the second pin of the first power management chip is grounded; one end of the third resistor is electrically connected to the third pin of the first power management chip, and the other end is electrically connected to the first capacitor; one end of the fourth capacitor is grounded, and the other end is electrically connected to the fifth pin of the first power management chip.

[0025] In this embodiment, the second power supply circuit includes a second power management chip, an inductor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is electrically connected to the fourth pin of the second power management chip, and the other end is electrically connected to the second capacitor. The fifth pin of the second power management chip is electrically connected to the second power input terminal. One end of the fifth capacitor is grounded, and the other end is electrically connected to the fifth pin of the second power management chip. One end of the sixth capacitor is grounded, and the other end is electrically connected to the fifth pin of the second power management chip. The second power management chip's second pin is grounded; one end of the seventh capacitor is electrically connected to the first pin of the second power management chip, and the other end is electrically connected to the inductor; the inductor and the eighth capacitor are connected in series, one end of which is grounded, and the other end is electrically connected to the sixth pin of the second power management chip; the ninth and tenth capacitors are connected in parallel, one end of which is grounded, and the other end is electrically connected to the eighth capacitor; the eleventh capacitor and the fifth resistor are connected in parallel, one end of which is electrically connected to the tenth capacitor, and the other end is electrically connected to the third pin of the second power management chip; one end of the sixth resistor is electrically connected to the fifth resistor, and the other end is grounded.

[0026] Among them, the first clamping diode and the second clamping diode are Schottky diodes.

[0027] Specifically, the working principle of the control circuit for preventing abnormal power-on / off timing in this application is as follows:

[0028] In actual use, when a stable power input is provided to the first power input terminal, the second power input terminal, the first power supply circuit, and the second power supply circuit, and the machine is officially powered on and started: the first clamping diode will quickly conduct and begin charging the first capacitor C1. At the same time, due to the reverse voltage, the second clamping diode is in a non-conducting state, preventing current from flowing directly through it.

[0029] Therefore, the current needs to pass through the second RC delay filter circuit, and gradually charge the second capacitor C2 through the second resistor R2. Due to the certain delay time in this process, NET1_EN connected to the first capacitor C1 reaches a stable operating voltage earlier than NET2_EN connected to the second capacitor C2, thus realizing an orderly power-on process.

[0030] Conversely, during the process of powering off or shutting down the machine: as the positive voltage disappears, the first clamping diode stops conducting, and at this time the first capacitor C1 will slowly discharge through the first resistor R1.

[0031] Meanwhile, due to the reverse voltage difference generated after the power supply is removed, the second clamping diode begins to conduct, providing a discharge path for the second capacitor C2, causing the voltage of NET2_EN to drop rapidly.

[0032] Therefore, during a power outage, NET2_EN will lose voltage before NET1_EN, ensuring that the entire circuit can be safely shut down in the predetermined sequence.

[0033] By adjusting the parameters of the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2, the power-on and power-off sequence can be precisely controlled, ensuring the stability and safety of the system. This not only improves the safety of system operation but also enhances its overall reliability.

[0034] Compared to traditional control circuits, the design in this application is not only simpler, reducing component layout space and lowering the overall circuit cost, but also provides better performance and stability by utilizing the extremely fast switching speed and unidirectional conductivity of Schottky diodes, while reducing safety hazards. Furthermore, this design does not affect the normal operation of other circuits and enhances system reliability.

[0035] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A control circuit for preventing abnormal power-on / off timing, characterized in that, The first power input end, the second power input end, the first power supply circuit, the second power supply circuit, the voltage limiting circuit, the main control circuit, the first RC delay filter circuit and the second RC delay filter circuit are included; the first power input end is electrically connected with the first power supply circuit, the second power input end is electrically connected with the second power supply circuit, the first power supply circuit is electrically connected with the first RC delay filter circuit, and the second power supply circuit is electrically connected with the second RC delay filter circuit; the main control circuit is electrically connected with the voltage limiting circuit, the first RC delay filter circuit and the second RC delay filter circuit, and the first RC delay filter circuit and the second RC delay filter circuit are electrically connected with the voltage limiting circuit.

2. The control circuit for preventing power-on / power-off timing abnormality according to claim 1, wherein The voltage limiting circuit includes the first clamping diode and the second clamping diode; the first clamping diode and the second clamping diode are reversely connected in series, one end is electrically connected with the first RC delay filter circuit, and the other end is electrically connected with the second RC delay filter circuit; the common end of the first clamping diode and the second clamping diode is electrically connected with the GPIO pin of the main control circuit.

3. The control circuit for preventing power-on / power-off timing abnormality according to claim 2, wherein The first RC delay filter circuit includes the first resistor and the first capacitor; the first resistor and the first capacitor are connected in series, one end is electrically connected with the GPIO pin of the main control circuit, and the other end is grounded, the common end of the first resistor and the first capacitor is electrically connected with the first clamping diode, and the first resistor is electrically connected with the second RC delay filter circuit.

4. The control circuit for preventing power-on / off timing abnormality according to claim 3, wherein The second RC delay filter circuit includes the second resistor and the second capacitor; the second resistor and the second capacitor are connected in series, one end is electrically connected with the first resistor, and the other end is grounded, and the common end of the second resistor and the second capacitor is electrically connected with the second clamping diode.

5. The control circuit for preventing power-on / power-off timing abnormality according to claim 3, wherein The first power supply circuit includes the first power management chip, the third resistor, the third capacitor and the fourth capacitor; the first pin of the first power management chip is electrically connected with the first power input end, one end of the third capacitor is grounded, and the other end is electrically connected with the first pin of the first power management chip; the second pin of the first power management chip is grounded, one end of the third resistor is electrically connected with the third pin of the first power management chip, and the other end is electrically connected with the first capacitor; one end of the fourth capacitor is grounded, and the other end is electrically connected with the fifth pin of the first power management chip.

6. The control circuit for preventing power-on / power-off timing abnormality according to claim 4, wherein The second power supply circuit includes a second power management chip, an inductor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a fourth resistor, a fifth resistor and a sixth resistor; one end of the fourth resistor is electrically connected with a fourth pin of the second power management chip, and the other end is electrically connected with the second capacitor; a fifth pin of the second power management chip is electrically connected with the second power input end; one end of the fifth capacitor is grounded, and the other end is electrically connected with the fifth pin of the second power management chip; one end of the sixth capacitor is grounded, and the other end is electrically connected with the fifth pin of the second power management chip; a second pin of the second power management chip is grounded; one end of the seventh capacitor is electrically connected with a first pin of the second power management chip, and the other end is electrically connected with the inductor; the inductor and the eighth capacitor are connected in series, one end is grounded, and the other end is electrically connected with a sixth pin of the second power management chip; the ninth capacitor and the tenth capacitor are connected in parallel, one end is grounded, and the other end is electrically connected with the eighth capacitor; the eleventh capacitor and the fifth resistor are connected in parallel, one end is electrically connected with the tenth capacitor, and the other end is electrically connected with a third pin of the second power management chip; one end of the sixth resistor is electrically connected with the fifth resistor, and the other end is grounded.

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