Semiconductor structure

Abstract

The embodiment of the utility model relates to a semiconductor structure, which comprises a plurality of nanosheets, a gate structure, an S / D structure, a step structure and a side wall spacer. A plurality of nanosheets are placed over a substrate, where the substrate extends in a first direction and the nanosheets are arranged in a second direction substantially perpendicular to the first direction. A gate structure is disposed over the substrate, wherein the gate structure is disposed between and around the nanosheets. The S / D structure is disposed adjacent to the gate structure and the plurality of nanosheets. A stepped structure is disposed below the S / D structure, wherein the stepped structure overlaps at least one of the nanosheets in a first direction. A sidewall spacer is disposed between the stepped structure and at least one of the nanosheets. A method of manufacturing a semiconductor structure is also provided.

Description

Technical Field

[0001] This utility model relates to semiconductor structures and their manufacturing methods. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Technological advancements in semiconductor materials and design have led to increasingly smaller and more complex circuits. These advancements were made possible by further technological progress in processing and manufacturing technologies. As the semiconductor industry moves towards technology process nodes that pursue smaller product sizes and multiple functions, various approaches have been explored, but obstacles have been encountered in integrating devices with different functions. Utility Model Content

[0003] Embodiments of this utility model relate to a semiconductor structure comprising: a plurality of nanosheets disposed above a substrate, wherein the substrate extends along a first direction and the nanosheets are arranged along a second direction substantially perpendicular to the first direction; a gate structure disposed above the substrate, wherein the gate structure is disposed between and surrounds the nanosheets; an S / D structure disposed adjacent to the gate structure and the plurality of nanosheets; a stepped structure disposed below the S / D structure, wherein the stepped structure overlaps with at least one of the nanosheets along the first direction; and a sidewall spacer disposed between the stepped structure and the at least one of the nanosheets.

[0004] Embodiments of this utility model relate to a semiconductor structure comprising: a first transistor comprising: a plurality of first nanosheets disposed above a substrate, wherein the substrate extends in a horizontal direction and the first nanosheets are arranged in a vertical direction substantially perpendicular to the horizontal direction; a first gate structure disposed above the substrate, wherein the first gate structure is disposed between and surrounds the first nanosheets; and a first S / D structure disposed above the substrate and adjacent to the first gate structure, wherein the first S / D structure overlaps with a first number of the first nanosheets in the horizontal direction; and a second transistor comprising: a plurality of second nanosheets disposed above the substrate and arranged in the vertical direction; a second gate structure disposed above the substrate, wherein the second gate structure is disposed between and surrounds the second nanosheets; and a second S / D structure disposed above the substrate and adjacent to the second gate structure, wherein the second S / D structure overlaps with a second number of the second nanosheets in the horizontal direction, and the second number is different from the first number.

[0005] Embodiments of this utility model relate to a method for manufacturing a semiconductor structure, comprising: receiving a substrate having a stacked structure disposed thereon, wherein the stacked structure includes a plurality of first semiconductor layers, a plurality of second semiconductor layers arranged alternately with the plurality of first semiconductor layers, and a plurality of inner spacers disposed on two opposing sides of each of the second semiconductor layers; forming a stepped structure on the substrate and adjacent to the stacked structure, wherein the stepped structure overlaps with the sidewalls of at least one of the first semiconductor layers and the sidewalls of at least one of the second semiconductor layers; forming sidewall spacers disposed between the stepped structure and the stacked structure; and growing a source / drain structure above the stepped structure. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic top view of a semiconductor structure according to some embodiments of the present invention.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H According to some embodiments of this utility model, respectively along Figure 1 A schematic cross-sectional view of the semiconductor structure of lines A-A', B-B', C-C', D-D', E-E', F-F', G-G' and H-H'.

[0009] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C and Figure 14D These are schematic cross-sectional views along different cutting lines and at different stages of the semiconductor structure manufacturing process according to some embodiments of the present invention.

[0010] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F , Figure 15G and Figure 15H According to other embodiments of this utility model, respectively along Figure 1 A schematic cross-sectional view of the semiconductor structure of lines A-A', B-B', C-C', D-D', E-E', F-F', G-G' and H-H'.

[0011] Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C and Figure 23D These are schematic cross-sectional views along different cutting lines and at different stages of the semiconductor structure manufacturing process according to some embodiments of the present invention.

[0012] Figure 24 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided objectives. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, having a first member formed above or on a second member may include embodiments in which the first and second members form direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members do not form direct contact. Additionally, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms (such as "below," "below," "down," "above," "on," "on," and the like) may be used herein to describe the relationship between one element or component illustrated in the figures and another element or component(s). In addition to the orientations depicted in the figures, spatial relative terms are intended to encompass different orientations of the apparatus in use or operation. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise) and thus the spatial relative descriptive terms used herein may be interpreted accordingly.

[0015] As used herein, although terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish elements, components, regions, layers, or segments from one another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply a sequence or order. Furthermore, the terms “source / drain region” or “multiple source / drain regions” may refer to a source or a drain, individually or collectively, depending on the context.

[0016] While the numerical ranges and parameters described in this disclosure are approximate, the values ​​described in specific examples should be reported as precisely as possible. However, any numerical value inherently contains a specific error that is necessarily caused by normal deviations seen in the corresponding test measurements. Furthermore, as used herein, the terms “substantially,” “approximately,” and “about” generally mean a value or range that would be expected by one of ordinary skill in the art. Alternatively, the terms “substantially,” “approximately,” and “about” mean within an acceptable standard error of the average value considered by one of ordinary skill in the art. One of ordinary skill in the art should understand that the acceptable standard error may vary depending on the technology. Except in operational / working examples or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages (e.g., material quantities, durations, temperatures, operating conditions, ratios of quantities, and the like) disclosed herein should be understood to be modified in all instances by the terms “substantially,” “approximately,” or “about.” Therefore, unless indicated to the contrary, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as desired. Finally, each numerical parameter should be interpreted at least by way of the number of significant digits reported and by applying common rounding techniques. Ranges herein may be expressed as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints.

[0017] Figure 1 This is a schematic top view of a semiconductor structure 1 according to some embodiments of the present invention. The semiconductor structure 1 includes a first region R1 (designed for power performance advantages) and a second region R2 (designed for speed performance advantages). The first region R1 may include multiple transistors T1 and T2, and the second region R2 may include multiple transistors T3 and T4. Transistors T1 and T2 may have different types of conductivity. For example, transistor T1 may be an N-type transistor and transistor T2 may be a P-type transistor. Similarly, transistors T3 and T4 may have different types of conductivity. For example, transistor T3 may be a P-type transistor and transistor T4 may be an N-type transistor. Transistors T1, T2, T3, and T4 may be devices of different types or generations. Transistors T1, T2, T3, and T4 may include one or more types of transistors, such as planar transistors, multi-gate transistors, gate-all-around (GAA) field-effect transistors (GAAFETs), fin field-effect transistors (FinFETs), vertical transistors, nanosheet transistors, nanowire transistors, bipolar junction transistors (BJTs), high electron mobility transistors (HEMTs or HEM FETs), selectors (including bidirectional limit switching or tunneling types), or combinations thereof.

[0018] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H According to some embodiments of this utility model, respectively along Figure 1 A schematic cross-sectional view of semiconductor structure 1 with lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' is shown in the figure. For illustrative purposes, transistors T1, T2, T3, and T4 shown in the figure are GAAFETs (e.g., nanosheet transistors). However, this disclosure is not limited thereto.

[0019] like Figure 1 , Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H As shown, each of transistors T1, T2, T3, and T4 comprises a plurality of nanosheets 122. For example, each of transistors T1, T2, T3, and T4 comprises three nanosheets 1221, 1222, and 1223. In some embodiments, the nanosheets 1221 and 1222 of transistors T1 and T2 in the first region R1 are functional nanosheets (or functional channels). In some embodiments, the nanosheets 1223 of transistors T1 and T2 in the first region R1 are dummy nanosheets (or dummy channels). Each of transistors T1 and T2 in the first region R1 has fewer functional nanosheets than either transistor T3 or T4 in the second region R2. A channel length may be defined between the distances of the source and drain structures (e.g., the N-type source / drain structure 23 of transistor T2 or T3, or the P-type source / drain structure 25 of transistor T1 or T4). In some embodiments, the channel lengths of transistors T1, T2, T3, and T4 are substantially equal. Different numbers of functional nanosheets of transistors in different regions can be integrated to provide different performance advantages in different regions of semiconductor structure 1 according to different applications.

[0020] Transistors T1 and T2 may have similar structures but different types of conductivity. Transistors T1 and T2 are formed on a substrate 11 (containing multiple fin structures 113). The substrate 11 may contain bulk semiconductor material (e.g., silicon) or other semiconductor materials (e.g., silicon germanium, silicon carbide, gallium arsenide, or the like). The substrate 11 may be of a first conductivity type (e.g., a P-type semiconducting substrate (acceptor type)) or a second conductivity type (e.g., an N-type semiconducting substrate (donor type)).

[0021] An isolator 12 is disposed above the substrate 11 and between the fin structure 113. In some embodiments, the transistor T1 includes a plurality of nanosheets 122 disposed above the fin structure 113 of the substrate 11. In some embodiments, the substrate 11 extends along a first direction (e.g., the X direction), and the nanosheets 122 are arranged along a second direction (e.g., the Z direction) substantially perpendicular to the first direction. In some embodiments, the transistor T1 includes a gate structure 32 disposed above the substrate 11. In some embodiments, the gate structure 32 includes a high-dielectric layer 321 and a gate electrode 322 surrounded by the high-dielectric layer 321. In some embodiments, the transistor T1 includes a pair of source / drain (S / D) structures 25 adjacent to two opposing sides of the gate structure 32 and disposed on the two opposing sides. In some embodiments, the S / D structures 25 are disposed on the two opposing sides of the nanosheets 122.

[0022] To control the number of functional nanosheets, transistor T1 further includes a stepped structure 21 disposed below each of the S / D structures 25. In some embodiments, spacer layer 141 (including a pair of sidewall spacers) is disposed above spacer 12 and on two opposing sides of stepped structure 21. In some embodiments, the height of stepped structure 21 is defined by the height of spacer layer 141. In some embodiments, the top surface of stepped structure 21 is located below and aligned with the top surface of spacer layer 141. Stepped structure 21 overlaps with at least one of nanosheets 122 along a first direction. For example, stepped structure 21 overlaps with nanosheet 1223 along the X direction. In some embodiments, stepped structure 21 overlaps with the sidewalls of nanosheet 1223. Stepped structure 21 may include different portions of different semiconductor materials. In some embodiments, different portions of stepped structure 21 have different concentrations of elements selected from group III-V. In some embodiments, stepped structure 21 includes an upper portion 213 and a lower portion 212 disposed below the upper portion 213. In some embodiments, the upper portion 213 comprises polycrystalline silicon and the lower portion 212 comprises silicon-germanium. In some embodiments, the lower portion 212 has a germanium concentration in the range of 20% to 35%.

[0023] The S / D structure 25 is placed on top of the stepped structure 21, and thus the S / D structure 25 horizontally overlaps with nanosheets 1221 and 1222 and is separated from nanosheet 1223 by the stepped structure 21. Nanosheets 1221 and 1222 are functional channels of transistor T1, and nanosheet 1223 is a dummy channel of transistor T1. In some embodiments, transistor T1 further includes an epitaxial portion 201 disposed between the fin structure 113 and the stepped structure 21. The epitaxial portion 201 may be the lowermost portion of the epitaxial structure formed at the start of epitaxial growth. In some embodiments, the epitaxial portion 201 refers to the L0 layer.

[0024] To prevent current leakage between the S / D structure 25 and the nanosheet 1223, the transistor T1 may further include a sidewall spacer 22 disposed between the stepped structure 21 and the nanosheet 1223. The sidewall spacer 22 may comprise a dielectric material, such as oxide, silicon nitride, oxynitride, or a combination thereof. In some embodiments, the sidewall spacer 22 contacts the sidewall of the stepped structure 21. In some embodiments, the sidewall spacer 22 contacts the upper portion 213 and the lower portion 212. In some embodiments, the sidewall spacer 22 contacts the sidewall of the nanosheet 1223. The configuration of the sidewall spacer 22 is defined by the stepped structure 21 and the adjacent nanosheet 122. Figure 2A In some embodiments shown, the sidewall spacer 22 of transistor T1 has curved sidewalls facing the stepped structure 21. In some embodiments, the width of the sidewall spacer 22, measured along a first direction, is in the range of 1 nanometer (nm) to 4 nm. In some embodiments, the height of the sidewall spacer 22, measured along a second direction, is in the range of 10 nm to 20 nm.

[0025] Transistor T1 may further include a dielectric layer 24 disposed between the stepped structure 21 and the S / D structure 25. In some embodiments, the S / D structure 25 is separated from the stepped structure 21 by the dielectric layer 24. The dielectric layer 24 prevents current leakage between the S / D structure 25 and the nanosheet 1223. When the S / D structure 25 is an N-type epitaxial structure, the presence of the dielectric layer 24 does not affect the strain of the S / D structure 25. In some embodiments, the thickness of the dielectric layer 24 is in the range of 3 nm to 5 nm.

[0026] The semiconductor structure 1 may further include a plurality of dielectric layers (e.g., 311, 312, and 313) disposed above the substrate 11 and between adjacent gate structures 32. In some embodiments, dielectric layers 311 and 312 are collectively referred to as isolation structure 31. In some embodiments, dielectric layer 313 refers to a spacer of gate structure 32. In some embodiments, dielectric layer 312 is disposed above and conformally fitted to S / D structure 25.

[0027] like Figure 2C and Figure 2D As shown in the figure, transistor T2 can have similar characteristics to Figure 2A and Figure 2BThe structure of transistor T1 shown is different from that of transistor T2, but the dielectric layer 24 is located on top of the S / D structure 23. The conductivity type of transistor T2 may be different from that of transistor T1, and therefore, transistor T2 includes an S / D structure 23 having a conductivity type different from that of S / D structure 25. The material of the gate electrode 322 of the gate structure 32 of transistor T2 may be different from the material of the gate electrode 323 of the gate structure 32 of transistor T1. When the S / D structure 23 is a P-type epitaxial structure, the presence of the dielectric layer 24 between the S / D structure 23 and the stepped structure 21 will affect the strain of the S / D structure 23. In some embodiments, the dielectric layer 24 is placed above the S / D structure 23. In some embodiments, the S / D structure 23 contacts the stepped structure 21 (e.g., the upper part 213 of the stepped structure 21).

[0028] Transistors T3 and T4 in the second region R2 are similar to transistors T2 and T1 in the first region R1, but do not have the stepped structure 21. More specifically, transistor T3 is similar to transistor T2 but does not have the stepped structure 21. Figure 2C and Figure 2D The stepped structure 21 shown in the figure, and transistor T4 is similar to transistor T1 but does not have Figure 2A and Figure 2B The stepped structure 21 is shown. In some embodiments, transistors T2 and T3 have the same conductivity type. In some embodiments, transistors T1 and T4 have the same conductivity type but different conductivity types from transistors T2 and T3. Figure 2E In some embodiments shown, there is no stepped structure 21, and the S / D structure 23 overlaps with all nanosheets 1221, 1222, and 1223 along a first direction, wherein nanosheets 1221, 1222, and 1223 are all functional nanosheets of transistor T3. In some embodiments, the S / D structure 23 contacts the epitaxial portion 201. Figure 2F In some embodiments shown, the lower portion of the S / D structure 23 is surrounded by a spacer layer 141. In some embodiments, the bottom of the S / D structure 23 is located below the top surface of the spacer layer 141.

[0029] Similarly, in Figure 2G In some embodiments shown, there is no stepped structure 21, and the S / D structure 25 overlaps with all nanosheets 1221, 1222, and 1223 along a first direction, wherein nanosheets 1221, 1222, and 1223 are all functional nanosheets of transistor T4. In some embodiments, a dielectric layer 24 is placed between the epitaxial portion 201 and the S / D structure 25. In some embodiments, the dielectric layer 24 contacts the epitaxial portion 201 and the S / D structure 25. Figure 2HIn some embodiments shown, the dielectric layer 24 is placed between different portions of the spacer layer 141 (i.e., a pair of sidewall spacers). In some embodiments, the lower portion of the S / D structure 25 is surrounded by the spacer layer 141. In some embodiments, the bottom of the S / D structure 25 is located below the top surface of the spacer layer 141.

[0030] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C and Figure 14D This is a schematic cross-sectional view of different stages in the manufacturing method of semiconductor structure 1 according to some embodiments of the present invention. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 10A , Figure 11A and Figure 12A It is a schematic cross-sectional view along line A-A' or B-B' in different stages of the manufacturing method of semiconductor structure 1. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 10B , Figure 11B and Figure 12B These are different stages in the manufacturing method of semiconductor structure 1 according to some embodiments of the present invention. Figure 1 The schematic cross-sectional view of line I-I' shown in the figure.

[0031] Figure 9A and Figure 9B The semiconductor structure 1 is manufactured in stages according to some embodiments of the present invention. Figure 1 The schematic cross-sectional view of lines E-E' and J-J' shown in the figure. Figure 13A , Figure 13B , Figure 13C and Figure 13D The semiconductor structure 1 is manufactured in stages according to some embodiments of the present invention. Figure 1 The schematic cross-sectional views of lines C-C', D-D', E-E' and F-F' shown in the figure. Figure 14A , Figure 14B , Figure 14C and Figure 14D The semiconductor structure 1 is manufactured in stages according to some embodiments of the present invention. Figure 1 The schematic cross-sectional views of lines A-A', B-B', G-G' and H-H' shown in the figure.

[0032] refer to Figure 3A and Figure 3B A substrate 11 comprising a plurality of fin structures 113 is received or formed. The fin structures 113 extend along a first direction and are substantially parallel to each other. A plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 122 are alternately formed over the substrate 11 along a second direction. In some embodiments, the first semiconductor layers 121 and the second semiconductor layers 122 are alternately arranged over each of the fin structures 113. Figure 3B The three first semiconductor layers 121 (e.g., 1211, 1212, and 1213) and the three second semiconductor layers 122 (e.g., 1221, 1222, and 1223) are shown for illustrative purposes. The number of first semiconductor layers 121 and the number of second semiconductor layers 122 can be adjusted according to different applications. The number of second semiconductor layers 122 depends on the number of nanosheets to be formed, and the number of first semiconductor layers 121 corresponds to the number of second semiconductor layers 122.

[0033] In some embodiments, two different semiconductor materials are alternately deposited on the substrate 11, and one or more etching operations are performed on the two different semiconductor materials and the substrate 11, thereby forming a first semiconductor layer 121 and a second semiconductor layer 122 on the fin structure 113, such as... Figure 3A and Figure 3B As shown in the figure. In some embodiments, the lowest first semiconductor layer 1213 contacts the fin structure 113. In some embodiments, the first semiconductor layer 121 comprises silicon germanium, and the second semiconductor layer 122 comprises polysilicon. For illustrative purposes, the group of first semiconductor layers 121 and second semiconductor layers 122 stacked on a fin structure 113 refers to the strip structure 112.

[0034] The spacer 12 may be formed above the substrate 11 and between the fin structure 113. In some embodiments, the top surface of the spacer 12 is located below the top surface of the substrate 11. In some embodiments, the top surface of the spacer 12 is located below the top surface of the fin structure 113. In some embodiments, the top surface of the spacer 12 is located below the interface between the strip structure 112 and the fin structure 113.

[0035] Multiple dummy gate structures 13 are formed above the fin structure 113. In some embodiments, the dummy gate structures 13 are substantially parallel to each other and arranged along a first direction. In some embodiments, each of the dummy gate structures 13 is arranged along a third direction (e.g., Figure 1 (as shown in the Y direction). In some embodiments, each of the dummy gate structures 13 extends across the fin structure 113. The dummy gate structure 13 may include a dielectric layer 131 disposed on the substrate 11 and the fin structure 113, a polysilicon layer 132 disposed above the dielectric layer 131, a capping layer 133 disposed above the polysilicon layer 132, and a hard layer 134 disposed above the capping layer 133. The dielectric layer 131, capping layer 133, and hard layer 134 may comprise the same or different dielectric materials, such as oxides, nitrides, oxynitrides, high-dielectric-coefficient materials, low-dielectric-coefficient materials, or combinations thereof. In some embodiments, the dielectric layer 131 comprises silicon oxide. In some embodiments, the capping layer 133 comprises silicon nitride. In some embodiments, the hard layer 134 comprises silicon oxide, silicon oxynitride, or a combination thereof.

[0036] refer to Figure 4A and Figure 4B A dielectric layer 14 is formed over the substrate 11. The dielectric layer 14 may conform to the contours of the fin structure 113, the dummy gate structure 13, and the substrate 11. In some embodiments, conformal deposition is performed to form the dielectric layer 14. The dielectric layer 14 may be formed using suitable processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced PVD (PEPVD), plasma-enhanced ALD (PEALD), or combinations thereof.

[0037] refer to Figure 5A and Figure 5B A spacer etching operation is performed to form a spacer layer 141 on two opposing sides of each of the dummy gate structures 13, and the spacer layer 141 and the dummy gate structure 13 are used as a mask to form a plurality of trenches 61. Figure 5BIn some embodiments shown, portions of the spacers 12 between portions of the spacer layer 141 are removed. In some embodiments, a plurality of trenches 66 are formed in the spacers 12 between adjacent fin structures 113. In some embodiments, an etching operation is performed on the dielectric layer 14 to remove horizontal portions of the dielectric layer 14, thereby forming the spacer layer 141. In some embodiments, the dielectric material of the dielectric layer 14 is different from the dielectric material of the hard layer 134. In some embodiments, the dielectric materials of the dielectric layer 14 and the hard layer 134 have high etch selectivity relative to the etchant of the etching operation to form the spacer layer 141 (including the sidewall spacer pairs formed by the etching operation). In some embodiments, the etchant of the spacer etching operation is selective relative to the dielectric material of the dielectric layer 14 of the hard layer 134. In some embodiments, the spacer etching operation is a time-mode etching operation and is controlled to further remove some of the vertical portions of the dielectric layer 14 lining the sidewalls of the strip structure 112. In some embodiments, the formation of trenches 66 is performed simultaneously with the formation of spacer layer 141. In some embodiments, the trench 66 is formed by a spacer etching operation. For example... Figure 5B As shown, spacer layer 141 is further placed on the lower sidewall of each of the strip structures 112. In some embodiments, a portion of the strip structure 112 is removed during the subsequent formation of the trench 61, and the boundary of the removed portion of the strip structure 112 is at... Figure 5B The dashed lines are used for illustrative purposes. In some embodiments, such as Figure 5B As shown, the spacer layer 141 on the separator 12 has a height H141, wherein the height H141 is controlled such that the top surface of the spacer layer 141 is substantially aligned with or above the top surface of the bottom second semiconductor layer 1223.

[0038] The trench 61 can be formed by one or more etching operations performed on the first semiconductor layer 121 and the second semiconductor layer 122. In some embodiments, the trench 61 separates each strip structure 112 into multiple portions. For illustrative purposes, the strip structure 112 is referred to as the stack structure 112 after the trench 61 is formed. In some embodiments, a portion of the fin structure 113 beneath the removed portion of the strip structure 112 is removed. In some embodiments, the bottom of the trench 61 is located below the top surface of the spacer 12.

[0039] In some embodiments, a dry etching operation is performed. In some embodiments, the etchant used in the dry etching operation has a low etch selectivity ratio between the dielectric material and the semiconductor material. In some embodiments, trenches 61 and 66 and spacer layer 141 are formed simultaneously by the dry etching operation. In some embodiments, the dry etching operation is a time-mode etching operation. In some embodiments, the bottom of trench 66 is substantially flush with the bottom of trench 61.

[0040] refer to Figure 6A and Figure 6B The lateral portion of the first semiconductor layer 121 is removed. In some embodiments, an etching operation is performed on the exposed sidewalls of the first semiconductor layer 121 to form a plurality of grooves 62. In some embodiments, the etching operation includes an isotropic etching operation. In some embodiments, the etching operation includes a wet etching operation.

[0041] refer to Figure 7A and Figure 7B A dielectric layer 15 is formed over the substrate 11, the fin structure 113, the dummy gate structure 13, and the stacked structure 112. The dielectric layer 15 may conform to the contours of the substrate 11, the fin structure 113, the dummy gate structure 13, the isolator 12, and the stacked structure 112. The formation of the dielectric layer 15 may be similar to the formation of the dielectric layer 14, and repeated descriptions are omitted herein. In some embodiments, the dielectric material of the dielectric layer 15 is different from the dielectric material of the dielectric layer 14 for the purpose of desired etch selectivity in etch operations performed in subsequent processing. The dielectric layer 15 fills the recess 62, as... Figure 7A As shown in the image.

[0042] refer to Figure 8A and Figure 8B Perform an etching operation to remove Figure 7A The portion of the dielectric layer 15 outside the trench 62 shown is used to form a plurality of inner spacers 151. Epitaxial growth is then performed to form an epitaxial portion 201 at the bottom of each of the trenches 61. In some embodiments, during epitaxial growth, the epitaxial portion 201 grows along the fin structure 113 in the trench 61, such that the epitaxial portion 201 defines the bottom surface of the trench 61. In some embodiments, the epitaxial portion 201 has an upward growth direction. Epitaxial growth is controlled to limit crystal growth on the sidewalls of the stacked structure 112. In some embodiments, an etching operation is performed to ensure that no unwanted crystals are grown or retained on the sidewalls of the stacked structure 112. In some embodiments, the top surface of the epitaxial portion 201 is located at a height above the top surface of the fin structure 113. In some embodiments, the top surface of the epitaxial portion 201 is located below the lowermost second semiconductor layer 1223. In some embodiments, the top surface of the epitaxial portion 201 is connected to the sidewall of the lowermost inner spacer 151.

[0043] refer to Figure 9A and Figure 9BAfter the inner spacer 151 is formed, a mask layer 16 is formed in region R2. The mask layer 16 is formed to prevent the formation of stepped structures 21 in undesired areas during subsequent processing for the purpose of adjusting different functional pieces in regions R1 and R2. Due to the formation of the mask layer 16, the number of functional pieces in region R1 differs from the number in region R2. In some embodiments, the mask layer 16 comprises one or more high-dielectric-coefficient materials. In some embodiments, the mask layer 16 comprises aluminum oxide.

[0044] In some embodiments, the intermediate structures along lines C-C', E-E', and G-G' may be similar to or identical to the intermediate structures along line A-A' in different stages prior to the formation of the mask layer 16. The steps and operations performed prior to the formation of the mask layer 16 are fully executed over the substrate 11. Therefore, similarly, the intermediate structures in different stages of the manufacturing method along line I-I' may be similar to or identical to the intermediate structures along line A-A' in the corresponding stages of the manufacturing method prior to the formation of the mask layer 16.

[0045] refer to Figure 10A and Figure 10B A stepped structure 21 is formed in region R1 above the epitaxial portions 201 between the stacked structures 112 and the sidewall spacers 141. In some embodiments, epitaxial growth is performed and the parameters of the epitaxial growth are controlled to have a bottom-up growth direction. The stepped structure 21 may include different portions comprising different semiconductor materials. In some embodiments, the stepped structure 21 includes a lower portion 212 and an upper portion 213. In some embodiments, silicon and germanium are introduced at the start of epitaxial growth to form the lower portion 212. In some embodiments, germanium is introduced for a specific duration from the start of epitaxial growth and stops when the lower portion 212 is formed. In some embodiments, silicon is introduced throughout the entire duration of epitaxial growth. Depending on the result of the epitaxial growth, etching operations may be performed to adjust the contour of the stepped structure 21 or remove unwanted crystals formed on the sidewalls of the stacked structure 112 during epitaxial growth.

[0046] In an alternative embodiment, a first epitaxial growth is performed to form a lower portion 212 and a second epitaxial growth is performed to form an upper portion 213. In some embodiments, a first etching operation is performed after the first epitaxial growth to adjust the contour of the lower portion 212. In some embodiments, a second etching operation is performed after the second epitaxial growth to adjust the contour of the upper portion 213. In some embodiments, the first and second epitaxial growths are performed in the same chamber. In some embodiments, the first and second etching operations are performed in the same chamber. In some embodiments, the first and second epitaxial growths and the first and second etching operations are performed in the same chamber.

[0047] In some embodiments, the lower portion 212 contacts the extended portion 201. In some embodiments, the lower portion 212 has Figure 10A The U-shaped configuration is shown in the figure. In some embodiments, the lower portion 212 contacts the sidewall of the adjacent stacked structure 112. In some embodiments, the lower portion 212 contacts the lowermost inner spacer 151 of the adjacent stacked structure 112. In some embodiments, the lower portion 212 contacts the sidewall of the lowermost second semiconductor layer 1223. In some embodiments, the upper portion 213 has a curved lower surface conformally to the lower portion 212. In some embodiments, the upper portion 213 is separated from the adjacent stacked structure 112 by the lower portion 212. In some embodiments, the distance between the upper portion 213 and the adjacent stacked structure 112 along a first direction is in the range of 1 nanometer (nm) to 4 nm. The configuration of the stepped structure 21 is defined by the adjacent stacked structure 112 and the adjacent sidewall spacer 141. In some embodiments, the top surface of the stepped structure 21 is substantially aligned with or below the top surface of the sidewall spacer 141. In some embodiments, the top surface of the stepped structure 21 includes the lower portion 212 and the upper portion 213. In some embodiments, the lateral portion of the lower portion 212 is exposed through the upper portion 213.

[0048] refer to Figure 11A and Figure 11B The lateral portion of the lower portion 212 is removed to form a groove 63 between the upper portion 213 and the adjacent stacked structure 112. In some embodiments, an etching operation is performed on the lower portion 212 to form the groove 63. The etching operation may be dry etching, wet etching, or a combination thereof. The width of the groove 63 (measured along a first direction) may vary along a second direction, depending on the profile of the groove 63. In other words, the distance between the upper portion 213 and the stacked structure 112 may vary along the second direction. In some embodiments, the distance D63 between the corner at the top surface of the upper portion 213 and the stacked structure 112 defines the shortest distance between the upper portion 213 and the stacked structure 112. In some embodiments, the distance D63 is substantially equal to or greater than 0.8 nm. For clarity, [the following is provided] Figure 11A An enlarged view of the circular portion of the middle structure shown in the image.

[0049] refer to Figure 12A and Figure 12B A pair of sidewall spacers 22 are formed in Figure 11A The sidewall spacer 22 is formed in the groove 63 shown. It can be formed by depositing a dielectric material followed by an etching operation. The dielectric material can be formed using a suitable process (e.g., ALD, PEALD, or a combination thereof). The etching operation can be a wet etching operation, a dry etching operation, or a combination thereof. In some embodiments, the dielectric material is entirely formed in both regions R1 and R2. Figure 11A and Figure 11BAbove the middle structure. In some embodiments, the etching operation is performed entirely on the substrate 11. Figure 9A and Figure 9B The mask layer 16 covering region R2 shown is used to prevent the formation of the stepped structure 21 in region R2. The mask layer 16 covering region R2 can be removed after the stepped structure 21 is formed. In some embodiments, the mask layer 16 is removed after the stepped structure 21 is formed and before the lateral portion of the lower portion 212 is removed. In some embodiments, the mask layer 16 is removed after the sidewall spacer 22 is formed and before the P-type S / D structure is formed in a subsequent process.

[0050] refer to Figure 13A , Figure 13B , Figure 13C and Figure 13D An S / D structure 23 is formed in regions R1 and R2. In some embodiments, the S / D structure 23 is a P-type S / D structure. In some embodiments, a dielectric layer is formed before the formation of the S / D structure 23 to cover the N-type transistor, wherein the dielectric layer acts as a mask to prevent the formation of a P-type S / D structure on the N-type transistor. In some embodiments, Figure 1 The transistors T2 and T3 shown are P-type transistors and are exposed during the formation of the S / D structure 23. In some embodiments, Figure 1 The transistors T1 and T4 shown are N-type transistors and are covered during the formation of the S / D structure 23. In some embodiments, the S / D structure 23 of transistor T2 is formed on the upper portion 213 of the stepped structure 21. In some embodiments, the S / D structure 23 of transistor T2 contacts the top surface of the upper portion 213 of the stepped structure 21. In some embodiments, the S / D structure 23 of transistor T2 contacts the sidewall spacer 22. In some embodiments, such as Figure 13B As shown, the bottom surface of the S / D structure 23 of transistor T2 is substantially aligned with the top surface of the sidewall spacer 141. In some embodiments, the S / D structure 23 of transistor T3 is formed on the epitaxial portion 201. In some embodiments, the S / D structure 23 of transistor T3 contacts the top surface of the epitaxial portion 201. In some embodiments, as Figure 14B As shown, the bottom surface of the S / D structure 23 of transistor T3 is located below the top surface of the sidewall spacer 141.

[0051] like Figure 13A , Figure 13B , Figure 13C and Figure 13D As shown, the bottom surfaces of the S / D structures 23 in different regions R1 and R2 are located at different heights, and transistors T2 and T3, which have the same conductivity type but are located in different regions R1 and R2, can thus have different numbers of functional nanosheets. For example... Figure 13AAs shown, the bottom second semiconductor layer 1223 is electrically isolated from the S / D structure 23 of transistor T2. Therefore, the bottom second semiconductor layer 1223 of transistor T2 becomes a dummy nanosheet due to the presence of the stepped structure 21 and sidewall spacers 22. However, Figure 13C The S / D structure 23 of transistor T3 shown is electrically connected to the bottom second semiconductor layer 1223, and the bottom second semiconductor layer 1223 is a functional nanosheet of transistor T3. Therefore, the number of functional nanosheets of transistor T3 without the step structure 21 (i.e., a larger number of functional channels) is greater than the number of functional nanosheets of transistor T2 with the step structure 21.

[0052] refer to Figure 14A , Figure 14B , Figure 14C and Figure 14D An S / D structure 25 is formed in regions R1 and R2. In some embodiments, the S / D structure 23 is an N-type S / D structure. In some embodiments, a dielectric layer is formed to cover P-type transistors T2 and T3 before the S / D structure 25 is formed. Figure 1 The transistors T1 and T4 shown are N-type transistors and are exposed during the formation of the S / D structure 25. In some embodiments, Figure 1 The transistors T2 and T3 shown are P-type transistors and are covered during the formation of the S / D structure 25. In some embodiments, the dielectric layer covering the N-type transistors during the formation of the S / D structure 23 is removed before the formation of the S / D structure 25.

[0053] As described above, when the S / D structure 25 is an N-type S / D structure, the presence of the dielectric layer 24 beneath the S / D structure does not affect the strain of the S / D structure (or its effect on strain is insignificant and negligible). In some embodiments, the dielectric layer 24 is formed after the formation of the S / D structure 23 and before the formation of the S / D structure 25 for electrical isolation between the dummy nanosheet (e.g., the second semiconductor layer 1223 in region R1) and the S / D structure 25. In some embodiments, the dielectric layer 24 is formed entirely over the substrate 11 and an etching operation is performed to remove a portion of the dielectric layer 24. In some embodiments, the dielectric layer 24 is retained on the stepped structure 21 of the transistor T1 (e.g., ...). Figure 14A and Figure 14B As shown in the figure), on the epitaxial portion 201 of transistor T4 (such as Figure 14C and Figure 14D On the top surface of the S / D structure 23 of transistors T2 and T3 (as shown in the figure) and transistors T2 and T3 Figure 2C , Figure 2D , Figure 2E and Figure 2F(as shown in the figure). In some embodiments, if the sidewall spacer 22 provides sufficient electrical isolation, then the dielectric layer 24 may be omitted. In some embodiments, if the dielectric layer 24 is not present, then the formation of the S / D structure 25 may be performed before or after the formation of the S / D structure 23.

[0054] In some embodiments, the S / D structure 25 of transistor T1 is formed above the dielectric layer 24 on the upper portion 213 of the stepped structure 21. In some embodiments, the S / D structure 25 of transistor T1 is in contact with the dielectric layer 24. In some embodiments, the S / D structure 25 of transistor T1 is separated from the stepped structure 21 or the sidewall spacer 22. In some embodiments, the bottom surface of the S / D structure 25 of transistor T1 is located above the top surface of the sidewall spacer 141. In some embodiments, the S / D structure 25 of transistor T4 is formed above the dielectric layer 24 on the epitaxial portion 201. In some embodiments, the S / D structure 25 of transistor T4 is in contact with the dielectric layer 24. In some embodiments, the S / D structure 25 of transistor T4 is separated from the epitaxial portion 201 through the dielectric layer 24. In some embodiments, the bottom surface of the S / D structure 25 of transistor T4 is located below the top surface of the sidewall spacer 141.

[0055] The metal gate replacement process can be performed after the formation of S / D structures 23 and 25 to form Figure 1 and Figures 2A to 2H The semiconductor structure 1 shown in the figure. The first semiconductor layer 121 is composed of Figure 2A , Figure 2C , Figure 2E and Figure 2G The gate structure 32 shown is replaced. After the metal gate replacement, the second semiconductor layer 122 may refer to nanosheets 122. In some embodiments, some of the nanosheets 122 adjacent to and laterally overlapping the S / D structure 23 or 25 are designated as functional nanosheets, and some of the nanosheets 122 adjacent to and laterally overlapping the stepped structure 21 are designated as dummy nanosheets.

[0056] The stepped structure 21 of semiconductor structure 1 comprises multiple portions having different concentrations of elements selected from group III-V (e.g., germanium). In other embodiments, the stepped structure 21 may be a monolithic structure having a uniform distribution of semiconductor material.

[0057] In the following description, a semiconductor structure 2 with a monolithic epitaxial structure 21 is provided, wherein the step structure 21 has a uniform distribution of semiconductor material. The semiconductor structure 2 may have the same characteristics as... Figure 1 The schematic top view of the semiconductor structure 1 shown is shown in the figure. Therefore, Figure 1 A top view used to illustrate semiconductor structure 2 in the following description.

[0058] For clarity and simplicity, element symbols for elements having the same or similar functions are repeated in different embodiments. However, this usage is not intended to limit this disclosure to specific embodiments or specific elements. Furthermore, the conditions or parameters described in different embodiments may be combined or modified to form different combinations of embodiments, provided that the parameters or conditions used are not contradictory.

[0059] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F , Figure 15G and Figure 15H According to other embodiments of this utility model, respectively along Figure 1 The figure shows a schematic cross-sectional view of the semiconductor structure 2 with lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H'. For illustrative purposes, transistors T1, T2, T3, and T4 shown in the figure are GAAFETs (e.g., nanosheet transistors). However, this disclosure is not limited thereto.

[0060] Semiconductor structure 2 may be similar to semiconductor structure 1, but the stepped structure 21 of semiconductor structure 2 is a monolithic structure and has a uniform concentration of semiconductor material. For the sake of brevity, only the parts or processes of semiconductor structure 2 that differ from those of semiconductor structure 1 will be described below.

[0061] The stepped structure 21 of the semiconductor structure 2 may have substantially straight sidewalls facing the sidewall spacers 22. In some embodiments, the sidewall spacers 22 have straight sidewalls facing the stepped structure 21. In some embodiments, the stepped structure 21 comprises a material identical to that of the substrate 11. In some embodiments, the width of the sidewall spacers 22, measured along a first direction, is in the range of 1 nm to 4 nm. In some embodiments, the height of the sidewall spacers 22, measured along a second direction, is in the range of 10 nm to 20 nm.

[0062] like Figure 15A and Figure 15B As shown, the stepped structure 21 of transistor T1 is located between the epitaxial portion 201 and the dielectric layer 24. In some embodiments, the stepped structure 21 of transistor T1 contacts the top surface of the epitaxial portion 201 and the bottom surface of the dielectric layer 24. Figure 15C and Figure 15DAs shown, the stepped structure 21 of transistor T2 is located between the epitaxial portion 201 and the S / D structure 23. In some embodiments, the stepped structure 21 of transistor T2 contacts the top surface of the epitaxial portion 201 and the bottom surface of the S / D structure 23. In some embodiments, the bottom of the stepped structure 21 of transistor T2 is located below the top of the epitaxial portion 201. Figures 15A to 15D In some embodiments shown, in region R1, the bottom of the stepped structure 21 is located below the top of the extension portion 201 and above the bottom of the extension portion 201.

[0063] like Figure 15E and Figure 15F As shown, transistor T3 further includes an epitaxial portion 216 that penetrates the epitaxial portion 201. In some embodiments, the top surface of the epitaxial portion 216 is substantially aligned with the top surface of the epitaxial portion 201. In some embodiments, the S / D structure 23 in region R2 contacts the epitaxial portion 216. In some embodiments, the bottom surface of the S / D structure 23 contacts the top surface of the epitaxial portion 216. In some embodiments, the bottom of the S / D structure 23 in region R2 is located below the bottom of the epitaxial portion 201. Figure 15G and Figure 15H As shown, transistor T4 further includes an epitaxial portion 216 that penetrates the epitaxial portion 201. The epitaxial portion 216 of transistor T4 may be similar to the epitaxial portion 216 of transistor T3 but may contact the dielectric layer 24. In some embodiments, the S / D structure 25 in region R2 is separated from the epitaxial portion 216 by the dielectric layer 24. In some embodiments, the bottom surface of the dielectric layer 24 contacts the top surface of the epitaxial portion 216 of transistor T4.

[0064] Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C and Figure 23D This is a schematic cross-sectional view of different stages of the manufacturing method of the semiconductor structure 2 according to some embodiments of the present invention.

[0065] Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A These are different stages in the manufacturing method according to some embodiments of the present invention. Figure 1 A schematic cross-sectional view of semiconductor structure 2 with lines A-A' or C-C' in the diagram. Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B It is along the different stages of the manufacturing process. Figure 1 The schematic cross-sectional view of the semiconductor structure 2 along line I-I' shown in the figure. Figure 17C , Figure 18C , Figure 19C and Figure 20C This is a schematic cross-sectional view of the semiconductor structure 2 along line E-E' or G-G' in different stages of the manufacturing process. Figure 17D , Figure 18D , Figure 19D and Figure 20D This is a schematic cross-sectional view of the semiconductor structure 2 along line J-J' in different stages of the manufacturing process.

[0066] Figure 22A , Figure 22B , Figure 22C and Figure 22D These are the stages of the manufacturing method according to some embodiments of the present invention, respectively along Figure 1 The schematic cross-sectional view of the semiconductor structure 2 with lines C-C', D-D', E-E' and F-F' shown in the figure. Figure 23A , Figure 23B , Figure 23C and Figure 23D These are the stages of the manufacturing method according to some embodiments of the present invention, respectively along Figure 1 The schematic cross-sectional view of the semiconductor structure 2 with lines A-A', B-B', G-G' and H-H' shown in the figure.

[0067] refer to Figure 16A and Figure 16B Execute similar to Figures 3A to 10BThe operations described herein are performed, but a sacrificial portion 214 is formed instead of the stepped structure 21. The method of forming the lower portion 212 can be applied to forming the sacrificial portion 214 and is omitted hereafter. In some embodiments, the sacrificial portion 214 is formed directly on the epitaxial portion 201. In some embodiments, the sacrificial portion 214 contacts the sidewall of the adjacent stacked structure 112. In some embodiments, the sacrificial portion 214 contacts the lowermost inner spacer 151 of the adjacent stacked structure 112. In some embodiments, the sacrificial portion 214 contacts the sidewall of the lowermost second semiconductor layer 1123. The configuration of the sacrificial portion 214 is limited by the adjacent stacked structure 112 and the adjacent sidewall spacer 141. In some embodiments, the top surface of the sacrificial portion 214 is substantially aligned with or below the top surface of the sidewall spacer 141.

[0068] refer to Figure 17A , Figure 17B , Figure 17C and Figure 17D Sacrificial layer 26 was formed in Figure 16A and Figure 16B Above the intermediate structure shown. The sacrificial layer 26 may be entirely formed in regions R1 and R2. In some embodiments, conformal deposition (e.g., ALD) is performed to form the sacrificial layer 26. In some embodiments, the sacrificial layer 26 comprises one or more dielectric materials, such as nitrides, oxynitrides, or combinations thereof. In some embodiments, the material used to cover region R2 before the formation of the sacrificial portion 214 is removed prior to the formation of the sacrificial layer 26. Figure 9A and Figure 9B The mask layer 16 is shown in the figure. The thickness of the sacrificial layer 26 may define the width (or thickness) of the sidewall spacers 22 formed in subsequent processing. In some embodiments, the thickness of the sacrificial layer 26 is in the range of 1 nm to 4 nm. In some embodiments, the thickness of the sacrificial layer 26 is consistent across the substrate 11. In some embodiments, the sacrificial layer 26 contacts the sacrificial portion 214 in the first region R1 and the epitaxial portion 201 in the second region R2.

[0069] refer to Figure 18A , Figure 18B , Figure 18C and Figure 18D An etching operation is performed. In some embodiments, the etching operation includes a dry etching operation. In some embodiments, the etching operation is non-selective. In some embodiments, portions of the sacrificial layer 26, the sacrificial portion 214, the epitaxial portion 201, and the substrate 11 are removed simultaneously.

[0070] In alternative embodiments, the etching operation comprises multiple steps. In some embodiments, spacer etching is performed to remove a horizontal portion of the sacrificial layer 26 to form a sacrificial spacer 261 on the sidewalls of the dummy gate structure 13 and the sidewalls of the stacked structure 112 above the sacrificial portion 214 in the first region R1 or above the epitaxial portion 201 in the second region R2. In some embodiments, a step of selectively oriented etching of the semiconductor material of the sacrificial portion 214, the epitaxial portion 201, and the substrate 11 is performed. In some embodiments, the oriented etching uses the dummy gate structure 13 and the sacrificial spacer 261 as a mask to form a trench 64 that penetrates each of the sacrificial spacers 261 and stops at a depth of the epitaxial portion 201 below the sacrificial spacer 261 in the first region R1, and a trench 65 that penetrates the epitaxial portion 201 and stops at a depth of the fin structure 113 in the second region R2.

[0071] refer to Figure 19A , Figure 19B , Figure 19C and Figure 19D Epitaxial growth is performed to form a stepped structure 21 and an epitaxial portion 216 in the first region R1 and the second region R2, respectively. The method for forming the upper portion 213 can be applied to forming the stepped structure 21 and the epitaxial portion 216 of the semiconductor structure 2, and repeated descriptions are omitted herein. In some embodiments, the stepped structure 21 comprises polysilicon. In some embodiments, the stepped structure 21 comprises a semiconductor material that is the same as the semiconductor material of the substrate 11 or the epitaxial portion 201.

[0072] Step structure 21 is formed in Figure 18A The groove 64 shown is confined within and between the remaining portion of the sacrificial portion 214 and the sidewall spacer 141. In some embodiments, the top surface of the stepped structure 21 is substantially aligned with the top surface of the sacrificial portion 214. In some embodiments, the top surface of the stepped structure 21 is substantially aligned with or below the top surface of the sidewall spacer 141. An extension portion 216 is formed simultaneously with the stepped structure 21. The extension portion 216 is formed in... Figure 18C The groove 65 shown is confined to the remaining portion of the extension portion 201.

[0073] refer to Figure 20A , Figure 20B , Figure 20C and Figure 20D Remove the sacrificial spacer 261. In some embodiments, the remaining portion of the sacrificial portion 214 is exposed after the sacrificial spacer 261 is removed. In some embodiments, the remaining portion of the extension portion 201 is exposed after the sacrificial spacer 261 is removed.

[0074] refer to Figure 21A and Figure 21B ,implement Figure 11A , Figure 11B , Figure 12A and Figure 12B The operations described herein are used to form the sidewall spacer 22. For example... Figure 11A and Figure 11B As depicted, an etching operation is performed on the remaining portion of the sacrificial portion 214 in the first region R1 to remove the remaining portion of the sacrificial portion 214 before the sidewall spacer 22 is formed. In some embodiments, the etching operation for removing the sacrificial portion 214 is selective for the semiconductor material (e.g., SiGe) of the sacrificial portion 214 and the second region R2 remains the same as... Figure 20C and Figure 20D The second region shown in the figure. This forms the sidewall spacer 22. In some embodiments, the top surface of the sidewall spacer 22 is substantially aligned with the top surface of the stepped structure 21.

[0075] refer to Figure 22A , Figure 22B , Figure 22C and Figure 22D ,implement Figure 13A , Figure 13B , Figure 13C and Figure 13D The operations depicted herein form an S / D structure 23. In some embodiments, the S / D structure 23 is formed directly over the stepped structure 21 in the first region R1. In some embodiments, the S / D structure 23 contacts the sidewall spacer 22 in the first region R1. In some embodiments, the S / D structure 23 is formed directly over the extension portion 216 in the second region R2. In some embodiments, the S / D structure 23 contacts the remainder of the extension portion 201 in the second region R2.

[0076] refer to Figure 23A , Figure 23B , Figure 23C and Figure 23D ,implement Figure 14A , Figure 14B , Figure 14C and Figure 14DThe operations depicted herein form an S / D structure 25. In some embodiments, the S / D structure 25 in the first region R1 is formed directly over the dielectric layer 24 on the stepped structure 21 and the sidewall spacer 22. In some embodiments, the S / D structure 25 contacts the dielectric layer 24. In some embodiments, the S / D structure 25 in the first region R1 is separated from the stepped structure 21 or the sidewall spacer 22. In some embodiments, the S / D structure 25 in the second region R2 is formed directly over the dielectric layer 24 on the epitaxial portion 216. In some embodiments, the S / D structure 25 in the second region R2 contacts the dielectric layer 24. In some embodiments, the S / D structure 25 in the second region R2 is separated from the epitaxial portion 216 by the dielectric layer 24.

[0077] The metal gate replacement process can be performed after the formation of S / D structures 23 and 25 to form Figure 1 and Figures 15A to 15H The semiconductor structure 2 shown in the figure. The first semiconductor layer 121 is composed of Figure 15A , Figure 15C , Figure 15E and Figure 15G The gate structure 32 shown is replaced. After the metal gate replacement, the second semiconductor layer 122 may refer to nanosheets 122. In some embodiments, some of the nanosheets 122 adjacent to and laterally overlapping the S / D structure 23 or 25 are designated as functional nanosheets, and some of the nanosheets 122 adjacent to and laterally overlapping the stepped structure 21 are designated as dummy nanosheets.

[0078] The above embodiments illustrate manufacturing methods and semiconductor structures with equal channel lengths but different numbers of (functional) channels in different regions for different performance requirements or purposes. In cases where transistors with different channel lengths are provided in different regions of a semiconductor structure, several problems arise, such as low product yield and the difficulty and cost of forming transistors with smaller channel lengths. By comparison, the proposed structures and methods discussed in this disclosure avoid the aforementioned problems and enable more efficient manufacturing integration.

[0079] To conclude the processes described in the different embodiments above, method 700 is provided.

[0080] Figure 24This is a flowchart of a method 700 for manufacturing a semiconductor structure according to some embodiments of the present invention. Method 700 includes several operations (701, 702, 703, and 704), and the description and illustration are not intended to limit the sequence of operations. In operation 701, a substrate on which a stacked structure is disposed is received, wherein the stacked structure includes a plurality of first semiconductor layers, a plurality of second semiconductor layers arranged alternately with the plurality of first semiconductor layers, and a plurality of inner spacers disposed on two opposing sides of each of the second semiconductor layers. In operation 702, a stepped structure is formed on the substrate and adjacent to the stacked structure, wherein the stepped structure overlaps with the sidewalls of at least one of the first semiconductor layers and the sidewalls of at least one of the second semiconductor layers. In operation 703, sidewall spacers are formed, wherein the sidewall spacers are disposed between the stepped structure and the stacked structure. In operation 704, a source / drain structure is grown above the stepped structure.

[0081] The operation of method 700 can be rearranged or otherwise modified in a variety of ways. In some embodiments, additional processes are provided before, during, and after method 700, and only some of these other processes are briefly described herein. Therefore, other embodiments are within the range of aspects described herein.

[0082] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanosheets, a gate structure, a signal-to-dial (S / D) structure, a stepped structure, and sidewall spacers. The plurality of nanosheets are disposed above a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed above the substrate, wherein the gate structure is disposed between and surrounds the nanosheets. The S / D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S / D structure, wherein the stepped structure overlaps with at least one of the nanosheets along the first direction. The sidewall spacers are disposed between the stepped structure and the at least one of the nanosheets.

[0083] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first transistor and a second transistor. The first transistor includes a plurality of first nanosheets, a first gate structure, and a first S / D structure. The plurality of first nanosheets are disposed above a substrate, wherein the substrate extends in a horizontal direction, and the first nanosheets are arranged in a vertical direction substantially perpendicular to the horizontal direction. The first gate structure is disposed above the substrate, wherein the first gate structure is disposed between and surrounds the first nanosheets. The first S / D structure is disposed above the substrate and adjacent to the first gate structure, wherein the first S / D structure overlaps with a first number of first nanosheets in the horizontal direction. The second transistor includes a plurality of second nanosheets, a second gate structure, and a second S / D structure. The plurality of second nanosheets are disposed above the substrate and arranged in the vertical direction. The second gate structure is disposed above the substrate, wherein the second gate structure is disposed between and surrounds the second nanosheets. The second S / D structure is disposed above the substrate and adjacent to the second gate structure, wherein the second S / D structure overlaps with a second number of second nanosheets in the horizontal direction, and the second number is different from the first number.

[0084] According to some embodiments of the present invention, a method for manufacturing a semiconductor structure is provided. The method may include several operations: receiving a substrate on which a stacked structure is disposed, wherein the stacked structure includes a plurality of first semiconductor layers, a plurality of second semiconductor layers arranged alternately with the plurality of first semiconductor layers, and a plurality of inner spacers disposed on two opposing sides of each of the second semiconductor layers; forming a stepped structure on the substrate and adjacent to the stacked structure, wherein the stepped structure overlaps with the sidewalls of at least one of the first semiconductor layers and at least one of the second semiconductor layers; forming sidewall spacers, wherein the sidewall spacers are disposed between the stepped structure and the stacked structure; and growing a source / drain structure above the stepped structure.

[0085] The foregoing summary of features of several embodiments enables those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0086] Symbol Explanation

[0087] 1: Semiconductor Structure

[0088] 2: Semiconductor Structure

[0089] 11: Substrate

[0090] 12: Isolation component

[0091] 13: Dummy gate structure

[0092] 14: Dielectric layer

[0093] 15: Dielectric layer

[0094] 16: Mask layer

[0095] 21: Stepped structure

[0096] 22: Side wall spacer

[0097] 23: Source / Drain (S / D) Structure

[0098] 24: Dielectric layer

[0099] 25: S / D Structure

[0100] 26: Sacrificial Layer

[0101] 31: Isolation Structure

[0102] 32: Gate structure

[0103] 61: Trench

[0104] 62: Groove

[0105] 63: Groove

[0106] 64: Trench

[0107] 65: Trench

[0108] 66: Trench

[0109] 112: Strip structure / stacked structure

[0110] 113: Fin Structure

[0111] 121: First semiconductor layer

[0112] 122: Nanosheet / Second Semiconductor Layer

[0113] 131: Dielectric layer

[0114] 132: Polycrystalline silicon layer

[0115] 133: Cap layer

[0116] 134: Hard layer

[0117] 141: Spare layer

[0118] 151: Inner spacer

[0119] 201: Extensional part

[0120] 212:lower part

[0121] 213: Upper part

[0122] 214: Sacrifice

[0123] 216: Extensional portion

[0124] 261: Sacrificial spacer

[0125] 311: Dielectric layer

[0126] 312: Dielectric layer

[0127] 313: Dielectric layer

[0128] 321: High dielectric constant layer

[0129] 322: Gate electrode

[0130] 323: Gate electrode

[0131] 700: Method

[0132] 701: Operation

[0133] 702: Operation

[0134] 703: Operation

[0135] 704: Operation

[0136] 1211: First semiconductor layer

[0137] 1212: First semiconductor layer

[0138] 1213: First semiconductor layer

[0139] 1221: Nanosheet / Second Semiconductor Layer

[0140] 1222: Nanosheet / Second Semiconductor Layer

[0141] 1223: Nanosheet / Second Semiconductor Layer

[0142] D63: Distance

[0143] H141: Altitude

[0144] R1: First Region

[0145] R2: Second Region

[0146] T1: Transistor

[0147] T2: Transistor

[0148] T3: Transistor

[0149] T4: Transistor.

Claims

1. A semiconductor structure, characterized by It includes: a plurality of nanosheets disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction; a gate structure disposed over the substrate, wherein the gate structure is disposed between and around the nanosheets; an S / D structure disposed adjacent to the gate structure and the plurality of nanosheets; a staircase structure disposed under the S / D structure, wherein the staircase structure overlaps at least one of the nanosheets along the first direction; and a sidewall spacer disposed between the staircase structure and the at least one of the nanosheets. The staircase structure includes:

2. The semiconductor structure of claim 1, wherein a first epitaxial portion disposed under the S / D structure; and a second epitaxial portion disposed under the first epitaxial portion, wherein the second epitaxial portion and the first epitaxial portion comprise different semiconductor materials. The sidewall spacer contacts the first epitaxial portion and the second epitaxial portion.

3. The semiconductor structure of claim 2, wherein The sidewall spacer has a curved sidewall facing the staircase structure.

4. The semiconductor structure of claim 2, wherein The S / D structure has an N-type conductivity, and the semiconductor structure further includes:

5. The semiconductor structure of claim 1, wherein a dielectric layer disposed between the staircase structure and the S / D structure. The S / D structure has a P-type conductivity, and the semiconductor structure further includes:

6. The semiconductor structure of claim 1, wherein a dielectric layer disposed over the S / D structure. It includes:

7. A semiconductor structure, characterized by a first transistor including: a plurality of first nanosheets disposed over a substrate, wherein the substrate extends along a horizontal direction, and the first nanosheets are arranged along a vertical direction substantially perpendicular to the horizontal direction; a first gate structure disposed over the substrate, wherein the first gate structure is disposed between and around the first nanosheets; and a first S / D structure disposed over the substrate and adjacent to the first gate structure, wherein the first S / D structure overlaps a first number of the first nanosheets along the horizontal direction; and a second transistor including: a plurality of second nanosheets disposed over the substrate and arranged along the vertical direction; a second gate structure disposed over the substrate, wherein the second gate structure is disposed between and around the second nanosheets; and a second S / D structure disposed over the substrate and adjacent to the second gate structure, wherein the second S / D structure overlaps a second number of the second nanosheets along the horizontal direction, and the second number is different from the first number. The first transistor further includes:

8. The semiconductor structure of claim 7, wherein a staircase structure disposed under the first S / D structure; and a sidewall spacer disposed between the staircase structure and at least one of the first nanosheets under the first S / D structure. The sidewall spacer has a width along a first direction in a range from 1 nanometer to 4 nanometers, or 9. The semiconductor structure of claim 8, wherein The sidewall spacer has a length along a second direction in a range from 10 nanometers to 20 nanometers.

10. The semiconductor structure of claim 7, wherein ​ The first S / D structure includes a first source structure and a first drain structure disposed on two opposite sides of the first nanosheet, The second S / D structure includes a second source structure and a second drain structure disposed on two opposite sides of the second nanosheet, and A first distance between the first source structure and the first drain structure is substantially equal to a second distance between the second source structure and the second drain structure.

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