Display substrate, display panel and display device

Abstract

The utility model discloses a display substrate, a display panel and a display device, relates to the technical field of display, and can avoid uneven brightness of a display picture and improve the display effect. The display substrate comprises a substrate layer; the first conductive layer comprises a first grid electrode and a data signal line; the semiconductor layer is arranged on one side of the first insulating layer away from the substrate layer; the second conducting layer is arranged on the side, away from the substrate layer, of the second insulating layer and comprises a second grid electrode, a first electrode and a second electrode; the first grid electrode comprises a first structure part, a second structure part and a third structure part, the second structure part is connected between the first structure part and the third structure part, and the orthographic projection of the second structure part on the substrate layer is overlapped with the orthographic projection of the second grid electrode on the substrate layer; the orthographic projections of the first structure part and the third structure part on the substrate layer are not overlapped with the orthographic projection of the second grid electrode on the substrate layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate, display panel and display device. Background Technology

[0002] Currently, display devices with advantages such as high-generation production capacity and low cost are widely used in televisions, computers, mobile phones, and other fields. With the rise of display technology, improving the brightness of the displayed image is one of the important factors in enhancing the user experience. However, in existing technologies, the fabrication process of driving transistors usually involves conductiveing ​​the semiconductor layer below the gate after gate fabrication. Due to photoresist and gate masking, insufficient conductiveing ​​of the semiconductor layer can easily occur, resulting in poor driving transistor performance, uneven brightness of the displayed image, and affecting the display effect. Utility Model Content

[0003] This application provides a display substrate, a display panel, and a display device, which can avoid uneven brightness of the displayed image and improve the display effect.

[0004] A first aspect of this application provides a display substrate, characterized in that it comprises:

[0005] Substrate layer;

[0006] A first conductive layer is disposed on one side of the substrate layer, and the first conductive layer includes a first gate and a data signal line;

[0007] A first insulating layer is disposed on the side of the first conductive layer away from the substrate layer;

[0008] A semiconductor layer is disposed on the side of the first insulating layer away from the substrate layer, and the orthogonal projection of the semiconductor layer on the substrate layer covers the orthogonal projection of the first gate on the substrate layer;

[0009] A second insulating layer is disposed on the side of the semiconductor layer away from the substrate layer;

[0010] The second conductive layer is disposed on the side of the second insulating layer away from the substrate layer. The second conductive layer includes a second gate, a first electrode, and a second electrode. The first electrode is connected to one end of the semiconductor layer, and the second electrode is connected to the other end of the semiconductor layer. The data signal line is electrically connected to the first electrode.

[0011] The first gate includes a first structural portion, a second structural portion, and a third structural portion. The second structural portion is connected between the first structural portion and the third structural portion. The orthographic projection of the second structural portion on the substrate overlaps with the orthographic projection of the second gate on the substrate. The orthographic projections of the first structural portion and the third structural portion on the substrate do not overlap with the orthographic projection of the second gate on the substrate.

[0012] In some embodiments, the orthographic projection of the second structural portion on the substrate layer coincides with the orthographic projection of the second gate on the substrate layer.

[0013] In some embodiments, the orthographic projection boundary of the first structural portion near the data signal line on the substrate is a first boundary, the orthographic projection boundary of the semiconductor layer near the first electrode on the substrate is a third boundary, and the distance between the first boundary and the third boundary is a first distance.

[0014] The orthogonal projection boundary of the third structural portion near the second electrode on the substrate is the second boundary, the orthogonal projection boundary of the semiconductor layer near the second electrode on the substrate is the fourth boundary, and the distance between the second boundary and the fourth boundary is the second distance.

[0015] The first distance is greater than the second distance;

[0016] And / or,

[0017] The orthogonal projection boundary of the second gate near the first electrode on the substrate is the fifth boundary, and the distance between the fifth boundary and the third boundary is the third distance.

[0018] The orthogonal projection boundary of the second gate near the second electrode on the substrate is the sixth boundary, the distance between the sixth boundary and the fourth boundary is the fourth distance, and the third distance is greater than the fourth distance.

[0019] In some embodiments, the orthogonal projection edge of the third structural portion near the second electrode on the substrate layer is the first edge;

[0020] The orthogonal projection edge of the semiconductor layer near the second electrode on the substrate layer is the second edge, and the first edge and the second edge at least partially overlap.

[0021] In some embodiments, the area of ​​the overlapping region of the first gate and the semiconductor layer projected orthogonally in the thickness direction is the first area;

[0022] The area of ​​the overlapping region of the second gate and the semiconductor layer projected orthogonally in the thickness direction is the second area, and the first area is larger than the second area.

[0023] In some embodiments, the overlapping region of the orthographic projection of the first gate in the thickness direction and the orthographic projection of the semiconductor layer in the thickness direction is the first overlapping region, the size of the first overlapping region along the first direction is the first size, and the first direction is the direction from the first electrode to the second electrode;

[0024] The overlapping region of the orthographic projection of the second gate in the thickness direction and the orthographic projection of the semiconductor layer in the thickness direction is the second overlapping region, and the dimension of the second overlapping region along the first direction is the second dimension;

[0025] The first dimension is larger than the second dimension.

[0026] In some embodiments, the second insulating layer includes a first via, through which the first electrode is electrically connected to the semiconductor layer;

[0027] The first electrode covers the second insulating layer at the edge of the first via, and the first electrode completely covers the exposed surface of the semiconductor layer of the first via.

[0028] In some embodiments, the first insulating layer includes a third via, and the semiconductor layer includes a fourth via;

[0029] The first via is connected to the fourth via, the fourth via is connected to the third via, and the first electrode is electrically connected to the data signal line through the first via, the fourth via, and the third via.

[0030] In some embodiments, the second insulating layer includes a first via, the first electrode is electrically connected to the semiconductor layer through the first via, and the second electrode is electrically connected to the semiconductor layer through the first via;

[0031] The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

[0032] In some embodiments, the first via includes an exposed area for exposing a portion of the surface of the semiconductor layer on the side away from the substrate layer;

[0033] The orthographic projection of the exposed area onto the substrate layer does not overlap with the orthographic projection of the first electrode onto the substrate layer; and / or

[0034] The orthographic projection of the exposed area onto the substrate layer does not overlap with the orthographic projection of the second electrode onto the substrate layer.

[0035] In some embodiments, the second insulating layer includes a second via located in a spacer region between the second gate and the second electrode; and / or, the second via is located in a spacer region between the second gate and the first electrode;

[0036] The second via is used to expose a portion of the surface of the semiconductor layer away from the substrate layer.

[0037] In some embodiments, the first electrode covers a portion of the edge of the semiconductor layer;

[0038] The area of ​​the semiconductor layer covered by the first electrode is greater than or equal to the area of ​​the semiconductor layer covered by the second electrode.

[0039] In some embodiments, the second insulating layer includes a gate insulating structure located between the first electrode and the second electrode, wherein the orthographic projection of the second gate on the substrate falls within the orthographic projection of the gate insulating structure on the substrate.

[0040] In some embodiments, the gate insulating structure includes a fourth structural portion, a fifth structural portion, and a sixth structural portion, wherein the fifth structural portion is connected between the fourth structural portion and the sixth structural portion;

[0041] The orthographic projection of the fifth structural portion on the substrate layer coincides with the orthographic projection of the second gate on the substrate layer, while the orthographic projections of the fourth and sixth structural portions on the substrate layer do not overlap with the orthographic projection of the second gate on the substrate layer.

[0042] In some embodiments, the orthographic projection boundary of the fourth structural portion near the first electrode on the substrate is the seventh boundary, the orthographic projection boundary of the second gate near the first electrode on the substrate is the fifth boundary, and the distance between the seventh boundary and the fifth boundary is the fifth distance.

[0043] The orthographic projection boundary of the sixth structural portion near the second electrode on the substrate is the eighth boundary, the orthographic projection boundary of the second gate near the second electrode on the substrate is the sixth boundary, and the distance between the eighth boundary and the sixth boundary is the sixth distance.

[0044] The fifth distance is equal to the sixth distance;

[0045] In some implementations, the fifth distance is greater than or equal to 1 μm;

[0046] The sixth distance is greater than or equal to 1 μm.

[0047] In some embodiments, the orthographic projection of the gate insulation structure onto the substrate falls within the orthographic projection of the first gate onto the substrate.

[0048] In some embodiments, the display substrate further includes:

[0049] A third insulating layer is disposed on the side of the second conductive layer away from the substrate layer, and the third insulating layer includes a fifth via.

[0050] A first planarization layer is disposed on the side of the third insulating layer away from the substrate layer, and the first planarization layer includes a sixth via.

[0051] A third conductive layer is disposed on the side of the first planarization layer away from the substrate layer, and the third conductive layer includes a first pixel electrode;

[0052] The first pixel electrode is electrically connected to the second electrode through the sixth via and the fifth via.

[0053] In some embodiments, the display substrate includes:

[0054] Multiple sub-pixels arranged in an array, each sub-pixel including a pixel electrode and a driving transistor, the driving transistor including a first gate, a semiconductor layer, a first electrode, a second electrode, and a second gate;

[0055] Multiple gate lines, the gate lines being electrically connected to the driving transistor, and at least four of the gate lines connecting to the same row of sub-pixels.

[0056] In some embodiments, at least one of the gate lines is disposed between the light-emitting regions of the nth row sub-pixels and the (n-1)th row sub-pixels; and / or,

[0057] At least one of the gate lines is disposed between the light-emitting regions of the nth row sub-pixels and the (n+1)th row sub-pixels; and / or,

[0058] At least two of the gate lines are disposed in the light-emitting area of ​​the nth row of sub-pixels, wherein the (n-1)th row of sub-pixels, the nth row of sub-pixels and the (n+1)th row of sub-pixels are arranged in an array along a second direction, the second direction being the length direction of the data signal, and n being a natural number greater than 0.

[0059] In some implementations, adjacent columns of sub-pixels of different colors are connected by the same gate line.

[0060] In some implementations, it includes a plurality of pixel units that are repeatedly arranged and a plurality of data signal transmission lines, the data signal transmission lines being electrically connected to the data signal lines;

[0061] The pixel unit includes multiple sub-pixels;

[0062] Subpixels of the same color within the same pixel unit are connected to the same data signal transmission line.

[0063] In some embodiments, the first gate comprises Ti and / or Cu; and / or,

[0064] The second gate comprises Ti and / or Cu; and / or,

[0065] The angle range of the second gate edge slope angle is 30° to 40°.

[0066] In some embodiments, the overlapping region of the orthographic projection of the first gate in the thickness direction and the orthographic projection of the semiconductor layer in the thickness direction is the first overlapping region;

[0067] The overlapping region between the orthographic projection of the second gate in the thickness direction and the orthographic projection of the semiconductor layer in the thickness direction is the second overlapping region;

[0068] The ratio of the maximum dimension of the semiconductor layer along the first direction to the maximum dimension of the first overlapping region along the first direction is greater than 2; and / or,

[0069] The ratio of the maximum dimension of the semiconductor layer along the first direction to the maximum dimension of the second overlapping region along the first direction is greater than 4; and / or,

[0070] The ratio of the maximum dimension of the first overlapping region along the first direction to the maximum dimension of the second overlapping region along the first direction is greater than 2; and / or,

[0071] The ratio of the maximum dimension of the first electrode along the first direction to the maximum dimension of the second electrode along the first direction is greater than 1.5; and / or,

[0072] Wherein, the first direction is the direction in which the first electrode points to the second electrode.

[0073] In some embodiments, the ratio of the maximum dimension of the second structural portion along the first direction to the maximum dimension of the third structural portion along the first direction is greater than 1; and / or,

[0074] The ratio of the maximum dimension of the second structural portion along the first direction to the maximum dimension of the first structural portion along the first direction is greater than 1; and / or,

[0075] The maximum distance ratio between the first distance and the second distance is greater than 1; and / or,

[0076] The maximum distance ratio between the third distance and the fourth distance is greater than 1; and / or,

[0077] Wherein, the first direction is the direction in which the first electrode points to the second electrode.

[0078] A second aspect of this application provides a method for preparing a display substrate, comprising:

[0079] A first conductive thin film layer is disposed on one side of the substrate layer;

[0080] The first conductive thin film layer is etched to obtain the first conductive layer, wherein the first gate and data signal line are obtained after etching;

[0081] A first insulating layer and a semiconductor thin film layer are sequentially disposed on the side of the first conductive layer away from the substrate layer, wherein the orthogonal projection of the semiconductor thin film layer on the substrate layer covers the orthogonal projection of the first gate on the substrate layer;

[0082] The semiconductor thin film layer is etched to obtain a semiconductor layer, and the orthogonal projection of the semiconductor layer on the substrate layer covers the orthogonal projection of the first gate on the substrate layer;

[0083] A second insulating layer and a second conductive layer are sequentially disposed on the side of the semiconductor layer away from the substrate layer;

[0084] The second conductive layer is etched to obtain a second gate, a first electrode, and a second electrode. The first electrode is connected to one end of the semiconductor layer, and the second electrode is connected to the other end of the semiconductor layer. The data signal line is electrically connected to the first electrode. The orthographic projection of the second gate on the substrate layer falls within the orthographic projection of the first gate on the substrate layer.

[0085] The first gate includes a first structural portion, a second structural portion, and a third structural portion. The second structural portion is connected between the first structural portion and the third structural portion. The orthographic projection of the second structural portion on the substrate overlaps with the orthographic projection of the second gate on the substrate. The orthographic projections of the first structural portion and the third structural portion on the substrate do not overlap with the orthographic projection of the second gate on the substrate.

[0086] Photoresist is applied to the side of the etched second conductive layer away from the substrate layer;

[0087] The photoresist is exposed and developed to obtain a patterned photoresist. The orthogonal projection of the patterned photoresist on the substrate layer covers the non-conductive region to obtain a transition substrate. The non-conductive region is the region where the semiconductor layer covered by the second conductive layer is located.

[0088] The transition substrate is subjected to a conductor treatment so that the semiconductor layer is conductor-transformed in areas other than the non-conductor-transformed regions, thereby obtaining a display substrate.

[0089] A third aspect of this application provides a display panel, including:

[0090] The display substrate as described in the second aspect.

[0091] A fourth aspect of this application provides a display device, comprising:

[0092] The display panel as described in the third aspect.

[0093] The display substrate provided in this application embodiment features a dual-gate structure with an extended first gate. This increases the overlapping area of ​​the orthographic projections of the second gate, the first gate, and the semiconductor layer onto the substrate. In cases of insufficient semiconductor conductivity, the extended first gate can induce and excite charge carriers in the non-conductive region of the semiconductor layer, thereby improving the conductivity of the semiconductor layer in the non-conductive region. This reduces the contact resistance between the first and second electrodes, increases the supply current, and further enhances the conductivity of the driving transistor, improving the charging efficiency of the pixel electrode. This results in stable light emission from the sub-pixels, avoiding uneven display brightness caused by insufficient supply current and improving the display effect. Attached Figure Description

[0094] Figure 1 A schematic partial structural diagram of a display substrate provided in an embodiment of this application;

[0095] Figure 2 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0096] Figure 3 for Figure 2 Cross-sectional view along A-A1;

[0097] Figure 4 for Figure 2 Cross-sectional view along B-B1;

[0098] Figure 5 A schematic partial structural diagram of a display substrate provided in an embodiment of this application;

[0099] Figure 6A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0100] Figure 7 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0101] Figure 8 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0102] Figure 9 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0103] Figure 10 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0104] Figure 11 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0105] Figure 12 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0106] Figure 13 A schematic partial structural diagram of a display substrate provided in an embodiment of this application;

[0107] Figure 14 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0108] Figure 15 A schematic partial structural diagram of a display substrate provided in an embodiment of this application;

[0109] Figure 16 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0110] Figure 17 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0111] Figure 18 A schematic partial structural diagram of a display substrate provided in an embodiment of this application;

[0112] Figure 19 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0113] Figure 20 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0114] Figure 21A schematic partial top view of another display substrate provided in an embodiment of this application;

[0115] Figure 22 A process flow diagram of a display panel manufacturing method provided in this application embodiment;

[0116] Figure 23 A process flow diagram of another display panel manufacturing method provided in this application embodiment;

[0117] Figure 24 A schematic structural diagram of a display panel provided in an embodiment of this application;

[0118] Figure 25 This is a schematic structural diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0119] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0120] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0121] Currently, display devices with advantages such as high-generation production capacity and low cost are widely used in televisions, computers, mobile phones, and other fields. With the rise of display technology, improving the brightness of the displayed image is one of the important factors in enhancing the user experience. However, in existing technologies, the fabrication process of driving transistors usually involves conductiveing ​​the semiconductor layer below the gate after gate fabrication. Due to photoresist and gate masking, insufficient conductiveing ​​of the semiconductor layer can easily occur, resulting in poor driving transistor performance, uneven brightness of the displayed image, and affecting the display effect.

[0122] Figure 1 This is a schematic partial structural diagram of a display substrate provided in an embodiment of this application. (Reference) Figure 1 In typical Top Gate Bottom Contact (TGBC) technology, a first conductive layer 200 is fabricated on one side of the substrate 100, a semiconductor layer 400 is fabricated on the side of the first conductive layer 200 away from the substrate 100, a second insulating layer 500 is fabricated on the side of the semiconductor layer 400 away from the substrate 100, and a second conductive layer 600 is fabricated on the side of the second insulating layer 500 away from the substrate 100. A second gate 601, a first electrode 602, and a second electrode 603 are formed through etching. After the second gate 601, the first electrode 602, and the second electrode 603 are fabricated, the second insulating layer 500 beneath the second gate 601 is etched over a large area to expose the semiconductor layer 400 beneath the second insulating layer 500. Ion implantation is then performed into the exposed semiconductor layer 400 to conduct the exposed semiconductor layer 400, thereby reducing the contact resistance between the first electrode 602 and the second electrode 603 and improving the charging rate of the pixel electrode. However, during the conductor formation process, the optical adhesive 630 above the second gate 601, as well as the second gate 601, the first electrode 602, and the second electrode 603, all block the semiconductor layer 400. The blocked semiconductor layer 400 is prone to insufficient ion implantation during the conductor formation process, resulting in insufficient conductor formation in the blocked area of ​​the semiconductor layer 400. Insufficient conductor formation leads to excessive contact resistance of the first electrode and the second electrode, resulting in poor performance of the driving transistor. This in turn leads to insufficient power supply current to the pixel electrode. Insufficient current causes different brightness of the sub-pixels, or even failure to emit light, ultimately resulting in uneven display brightness of the display panel and problems such as bright and dark lines.

[0123] A first aspect of this application provides a display substrate.

[0124] Figure 2 This is a schematic partial top view of a display substrate provided in an embodiment of this application. Figure 3 for Figure 2 Cross-sectional view along A-A1, Figure 4 for Figure 2 A cross-sectional view along B-B1. For example, as shown... Figures 2 to 4As shown, the display substrate includes a substrate layer 100, a first conductive layer 200, a first insulating layer 300, a semiconductor layer 400, a second insulating layer 500, and a second conductive layer 600. The substrate layer 100 can be a glass substrate or a flexible substrate. The first conductive layer 200 is disposed on one side of the substrate layer 100, and includes a first gate 201 and a data signal line 202. The first insulating layer 300 is disposed on the side of the first conductive layer 200 away from the substrate layer 100. The first insulating layer 300 may include a single-layer silicon nitride layer, a single-layer silicon oxide layer, or a stacked structure of silicon nitride and silicon oxide layers. The semiconductor layer 400 is disposed on the side of the first insulating layer 300 away from the substrate layer 100, and the orthogonal projection of the semiconductor layer 400 on the substrate layer 100 covers the orthogonal projection of the first gate 201 on the substrate layer 100. The second insulating layer 500 is disposed on the side of the semiconductor layer 400 away from the substrate layer 100. The second conductive layer 600 is disposed on the side of the second insulating layer 500 away from the substrate layer 100. The second conductive layer 600 includes a second gate 601, a first electrode 602, and a second electrode 603. The first electrode 602 is connected to one end of the semiconductor layer 400, and the second electrode 603 is connected to the other end of the semiconductor layer 400. The first electrode 602 can serve as either a source or a drain, and the second electrode 603 can serve as either a source or a drain. The data signal line 202 is electrically connected to the first electrode 602. The data signal is transmitted to the second electrode 603 through the data signal line 202 and the first electrode 602. Under the control of the gate signal supplied to the first gate 201 and the second gate 601, the voltage difference between the gate and the source reaches the threshold voltage of the driving transistor, so that the first electrode 602 and the second electrode 603 are connected through the semiconductor layer 400, and the data signal is transmitted from the first electrode 602 to the second electrode 603. The first electrode 602, the second electrode 603, the first gate 201, the second gate 601, and the semiconductor layer 400 can form a driving transistor. The threshold voltage of the driving transistor is the minimum gate-source voltage required to form a conductive path between the source and drain terminals. The second electrode is electrically connected to the pixel electrode, transmitting the data signal to the pixel electrode to drive the pixel to emit light and achieve image display.

[0125] For example, such as Figures 2 to 4 As shown, the data signal line 202 is disposed on the same layer as the first gate 201. By placing the data signal line 202 in the first conductive layer 200, the space occupied by the data signal line 202 is reduced, so as to reasonably wire the circuit and reasonably arrange the first electrode, the second electrode and the first gate, thereby improving the aperture ratio of the display substrate.

[0126] For example, such as Figure 2As shown, the display substrate includes a gate line G, which provides gate signals to a first gate 201 and a second gate 601. A fifth via H5 connects the first gate 201 and the second gate 601, and both the first gate 201 and the second gate 601 are connected to the gate line G. The first gate 201 at least partially covers the second gate 601, and a gap is provided between the data signal line 202 and the first gate 201. The first electrode 602, the second electrode 603, and the second gate 601 all at least partially cover the semiconductor layer 400.

[0127] For example, such as Figure 3As shown, the first electrode 602, the second electrode 603, the first gate 201, the second gate 601, and the semiconductor layer 400 together form a driving transistor. The first gate 201 and the second gate 601 can be turned on to form a dual-gate structure. After the first gate 201 and the second gate 601 are connected, they can receive the same signal. The semiconductor layer 400 includes a conductive region 401 and a non-conductive region 402. The non-conductive region 402 may include the area of ​​the semiconductor layer below, which is covered by the second gate 601, the first electrode 602, and the second electrode 603. The conductive region 402 may include the area of ​​the semiconductor layer 400 that is not covered by the second gate 601, the first electrode 602, and the second electrode 603, i.e., the area of ​​the semiconductor layer 400 other than the non-conductive region. The orthogonal projection of the semiconductor layer 400 onto the substrate layer 100 covers the orthogonal projection of the first gate 201 onto the substrate layer 100. The first gate 201 includes a first structural portion 211, a second structural portion 212, and a third structural portion 213. The second structural portion 212 is connected between the first structural portion 211 and the third structural portion 213. The first structural portion 211, the second structural portion 212, and the third structural portion 213 are an integral structure. The orthogonal projection of the second structural portion 212 on the substrate layer 100 overlaps with the orthogonal projection of the second gate 601 on the substrate layer 100; the projections may completely overlap or partially overlap. The orthogonal projections of the first structural portion 211 and the third structural portion 213 on the substrate layer 100 do not overlap with the orthogonal projection of the second gate 601 on the substrate layer 100. However, the orthogonal projections of the first structural portion 211 and the third structural portion 213 on the substrate layer 100 overlap with the orthogonal projection of the semiconductor layer 400 on the substrate layer 100. By setting a dual-gate structure and lengthening both ends of the first gate 201 along the first direction X, the overlapping area of ​​the orthographic projections of the second gate 601 on the substrate 100, the first gate 201 on the substrate 100, and the semiconductor layer 400 on the substrate 100 is increased. In the case of insufficient conductivity of the semiconductor layer 400, the lengthened first gate 201 can enhance the carrier induction excitation of the semiconductor layer 400 in the non-conductive region 402, thereby improving the conductivity of the semiconductor layer 400 in the non-conductive region 402, reducing the contact resistance between the first electrode 602 and the second electrode 603, increasing the power supply current, and thus improving the electrical performance of the driving transistor. This provides sufficient power supply current for the pixel electrode, improves the charging efficiency of the pixel electrode, and enables the sub-pixel to emit light stably, avoiding uneven display brightness and bright / dark lines caused by insufficient power supply current, thereby improving the display effect of the display panel.

[0128] For example, the display substrate can be an array substrate of a liquid crystal display (LCD) panel or a driving substrate in an organic light-emitting diode (OLED) panel. In an LCD, driving transistors are connected to pixel electrodes to drive the liquid crystals to flip, thereby enabling light emission from the display panel. In an OLED, the pixel electrodes serve as the anodes of the light-emitting devices, and driving transistors are connected to the pixel electrodes to drive the light-emitting devices to emit light, thereby enabling light emission from the display panel.

[0129] For example, refer to Figure 2 and Figure 4 The orthographic projection of the second gate 601 onto the substrate 100 overlaps with the orthographic projection of the first gate 201 onto the substrate 100. A fifth via H5 is provided in the second insulating layer 500, and a sixth via H6 is provided in the first insulating layer 300. The fifth via H5 and the sixth via H6 are connected, and the orthographic projection of the sixth via H6 onto the substrate 100 falls within the orthographic projection of the fifth via H5 onto the substrate 100. The second gate 601 is electrically connected to the first gate 201 through the fifth via H5 and the sixth via H6.

[0130] The display substrate provided in this application embodiment features a dual-gate structure. By extending the first gate located below the semiconductor along a first direction, the overlapping area of ​​the orthogonal projections of the second gate, the first gate, and the semiconductor layer on the substrate is increased. In cases where the semiconductor layer is insufficiently conductive, the extended first gate can enhance the carrier induction excitation in the non-conductive region, thereby improving the conductivity of the semiconductor layer in the non-conductive region. This reduces the contact resistance between the first and second electrodes, increases the power supply current, and improves the electrical performance of the driving transistor. This provides sufficient power supply current for the pixel electrode, improves the charging efficiency of the pixel electrode, and enables stable light emission from the sub-pixels. This avoids uneven display brightness and bright / dark lines caused by insufficient power supply current, thus improving the display effect of the display panel.

[0131] Figure 5 This is a schematic partial structural diagram of a display substrate provided in an embodiment of this application. For example, refer to... Figure 3 and Figure 5The orthographic projection of the second structural portion 212 on the substrate 100 coincides with at least a partially non-conductive region 402. The non-conductive region 402 may include a first sub-region 411, a second sub-region 412, and a third sub-region 413. The orthographic projection of the second structural portion 212 on the substrate 100 coincides with the orthographic projection of the second gate 601 on the substrate 100, and the orthographic projection of the second structural portion 212 on the substrate 100 coincides with the orthographic projection of the second sub-region 412 on the substrate 100. The orthographic projection of the first structural portion 211 on the substrate 100 at least partially overlaps with the orthographic projection of the first sub-region 411 on the substrate 100, and the orthographic projection of the third structural portion 213 on the substrate 100 at least partially overlaps with the orthographic projection of the third sub-region 413 on the substrate 100. By setting the projections of the second structural part 212, the second sub-region 412 and the second gate 601 to overlap, the projection portions of the first structural part 211 and the first sub-region 411 overlap, and the projection portions of the third structural part 213 and the third sub-region 413 overlap, so that more charge carriers in the semiconductor layer 400 in the non-conductive region 402 are excited under the action of the electrical signal on the first gate 201, so as to compensate for the power supply current of the non-conductive region 402, improve the light emission stability of the display panel, and thus improve the display effect.

[0132] Figure 6 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 6 As shown, the orthographic projection boundary of the first structural portion 211 near the data signal line 202 on the substrate layer 100 is the first boundary K1, and the orthographic projection boundary of the semiconductor layer 400 near the first electrode 602 on the substrate layer 100 is the third boundary K3. The distance between the first boundary K1 and the third boundary K3 is the first distance L1. The orthographic projection boundary of the third structural portion 213 near the second electrode 603 on the substrate layer 100 is the second boundary K2, and the orthographic projection boundary of the semiconductor layer 400 near the second electrode 603 on the substrate layer 100 is the fourth boundary K4. The distance between the second boundary K2 and the fourth boundary K4 is the second distance L2. The first distance L1 is greater than the second distance L2. By setting a first distance L1 between the first boundary K1 and the third boundary K3, and setting the first distance L1 to be greater than the second distance L2, sufficient position space is provided for the data signal line 202, so that the first electrode 602 is electrically connected to the data signal line 202. This facilitates the transmission of data signals to the pixel electrode through the driving transistor. At the same time, it also ensures that the first gate is long enough so that more charge carriers in the semiconductor layer 400 in the non-conductive region 402 are induced and excited, thereby compensating for the power supply current of the non-conductive region 402 and improving the display effect.

[0133] For example, refer to Figure 6The size of the first distance L1 ranges from 4.5 μm to 5 μm, and can be 4.6 μm, 4.7 μm, 4.8 μm, or 4.9 μm. The size of the second distance L2 ranges from 0 μm to 3 μm, and can be 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 2.8 μm. The size of the third distance L3 ranges from 8 μm to 16 μm, and can be 9 μm, 11 μm, 13 μm, or 15 μm. The size of the fourth distance L4 ranges from 4 μm to 12 μm, and can be 5.5 μm, 6.5 μm, 7.5 μm, 8.5 μm, 9.5 μm, 10.5 μm, or 11.5 μm. The maximum distance ratio between the first distance L1 and the second distance L2 is greater than 1. The maximum distance ratio between the third distance L3 and the fourth distance L4 is greater than 1.

[0134] For example, such as Figure 6 As shown, the orthogonal projection boundary of the second gate 601 near the first electrode 602 on the substrate 100 is the fifth boundary K5, and the distance between the fifth boundary K5 and the third boundary K3 is the third distance L3; the orthogonal projection boundary of the second gate 601 near the second electrode 603 on the substrate 100 is the sixth boundary, and the distance between the sixth boundary K6 and the fourth boundary K4 is the fourth distance L4. The third distance L3 is greater than the fourth distance L4. By setting the third distance L3 between the fifth boundary K5 and the third boundary K3, and the fourth distance L4 between the sixth boundary K6 and the fourth boundary K4, space can be reserved for the connection of the first electrode 602 to the semiconductor layer 400, and space can be reserved for the connection of the second electrode 603 to the semiconductor layer 400, so as to realize signal transmission.

[0135] Figure 7 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 7 As shown, the orthogonal projection edge of the third structural portion 213 near the second electrode 603 on the substrate layer 100 is designated as the first edge M1. The orthogonal projection edge of the semiconductor layer 400 near the second electrode 603 on the substrate layer 100 is designated as the second edge M2. The first edge M1 and the second edge M2 at least partially overlap. The first edge M1 and the second edge M2 may partially overlap or completely overlap. When the first edge M1 and the second edge M2 overlap, the semiconductor layer 400 covering the second electrode 603 is induced and excited by the first gate 201 to compensate for the insufficient conductivity in the area covered by the second electrode 603. The compensation effect when the first edge M1 and the second edge M2 completely overlap is higher than the compensation effect when the first edge M1 and the second edge M2 partially overlap.

[0136] In some implementations, reference Figure 7The first gate may include Ti or Cu, or an alloy of Ti and Cu. The second gate 601 may include Ti or Cu, or an alloy of Ti and Cu. The edge slope angle α1 of the second gate 601 ranges from 30° to 40°. For example, the edge slope angle α1 of the second gate 601 can be 33°, 35°, 38°, or 39°. For example, the edge slope angle α1 of the second gate 601 can be less than 45° to avoid cracking of the film layer above the second gate 601 due to an excessively large edge slope angle, thereby improving the product's service life and stability.

[0137] Figure 8 This is a schematic partial top view of a display substrate provided for an embodiment of this application. For example, refer to... Figure 8 The first conductive layer includes a first gate 201 and a data signal line 202. The minimum distance between the data signal line 202 and the first gate 201 along a first direction X is a first pitch k. The first pitch k ranges from 4 μm to 5 μm; for example, the first pitch k can be 4.2 μm, 4.5 μm, 4.6 μm, 4.7 μm, or 4.9 μm. The width of the first gate along the first direction X is a first width W, and the size of the first width W ranges from 15 μm to 30 μm. For example, the first width W can be 16 μm, 18 μm, 20 μm, 22 μm, 44 μm, 26 μm, or 28 μm. The main linewidth of the data signal line 202 along the first direction X is a second width b, and the size of the second width b is 2 μm to 5 μm. For example, the second width b can be 2.5 μm, 3.5 μm, 4.5 μm, or 5 μm.

[0138] For example, refer to Figure 3 and Figure 8 The data signal line includes a protrusion 202-1, which is disposed on the side of the data signal line 202 in the first direction X near the first gate 201. The protrusion 202-1 is a partial widening of the data signal line 202, providing space for the placement of the first via H1 and the third via H3, so that the data signal line 202 can be easily electrically connected to the first electrode 602 through the vias. The second structural portion 212 is the main body of the first gate 201. The first structural portion 211 and the third structural portion 213 are extended along the width direction of the second structural portion, so that more charge carriers in the semiconductor layer 400 in the non-conductive region 402 are induced and excited, thereby compensating for the supply current of the non-conductive region 402 and improving the display effect.

[0139] For example, refer to Figure 3 and Figure 8The second structural portion 212 has a size ranging from 6 μm to 8 μm along the first direction X. For example, the size of the second structural portion 212 along the first direction X can be 6.3 μm, 6.5 μm, 7 μm, 7.5 μm, or 7.8 μm. The third structural portion 213 has a size ranging from 5 μm to 8 μm along the first direction. For example, the size of the third structural portion 213 along the first direction can be 5.5 μm, 6 μm, 7 μm, or 7.5 μm. The first structural portion 211 has a size ranging from 5 μm to 8 μm along the first direction X. For example, the size of the first structural portion 211 along the first direction can be 5.5 μm, 6 μm, 7 μm, or 7.5 μm. Wherein, the first direction X is the direction from the first electrode 602 to the second electrode 603, and the second direction Y is the length direction of the data signal line. The ratio of the maximum size of the second structural portion 212 along the first direction X to the maximum size of the third structural portion 213 along the first direction is greater than 1. The ratio of the maximum dimension of the second structural part 212 along the first direction X to the maximum dimension of the first structural part 211 along the first direction X can be greater than 1.

[0140] For example, the ratio of the maximum dimension of the second structural portion 212 along the first direction X to the maximum dimension of the first structural portion 211 along the first direction X can be greater than 1.5, and the ratio of the maximum dimension of the second structural portion 212 along the first direction X to the maximum dimension of the third structural portion 213 along the first direction X can be greater than 1.5.

[0141] Figure 9 A schematic partial top view of another display substrate provided in an embodiment of this application. Exemplary, see reference... Figure 3 and Figure 9 A semiconductor layer 400 covers a first gate 201, and a first insulating layer 300 is disposed between the semiconductor layer 400 and the first gate 201. The size of the semiconductor layer 400 along the first direction X ranges from 35μm to 40μm, and the size of the semiconductor layer 400 along the first direction X can be 36μm, 37μm, 36μm or 38μm.

[0142] For example, refer to Figure 3 and Figure 9 The area of ​​the overlapping region of the first gate 201 and the semiconductor layer 400 projected orthogonally in the thickness direction Z is the first area. The overlapping region of the first gate 201 and the semiconductor layer 400 projected orthogonally in the thickness direction Z is the first overlapping region S1 formed by the overlapping of the orthogonal projection of the second structural part 212 of the first gate 201 in the thickness direction Z and the orthogonal projection of the semiconductor layer 400 in the thickness direction Z. The area of ​​the first overlapping region S1 is the first area.

[0143] Figure 10 This is a schematic partial top view of another display substrate provided in an embodiment of this application. Exemplary, in conjunction with... Figure 3 , Figure 4 and Figure 10 A second insulating layer 500 covers the semiconductor layer 400, and the second insulating layer 500 has a fifth via H5 and a first via H1. A sixth via H6 is provided in the first insulating layer 300 below the fifth via H5, and the fifth via H5 covers the sixth via H6. The second gate 601 can be electrically connected to the first gate 201 through the fifth via H5 and the sixth via H6. The first via H1 can be used to connect the data signal line 202 and the first electrode 602, and the first via H1 can also be used to connect the second electrode 603 and the pixel electrode.

[0144] Figure 11 A schematic partial top view of another display substrate provided in an embodiment of this application. Exemplary, see reference... Figure 3 and Figure 11 The second gate 601 covers the first gate 201, the first electrode 602 partially covers the semiconductor layer 400, the second electrode 603 partially covers the semiconductor layer 400, the first gate 201 and the second gate 601 are connected through the first connection via M, and both the first gate 201 and the second gate 601 are connected to the gate line G.

[0145] For example, refer to Figure 11 The first linewidth 'a' of the gate line G along the second direction Y ranges from 2 μm to 5 μm, and can be 2.5 μm, 3.5 μm, 4.5 μm, or 5 μm. The fourth dimension L14 of the second gate 601 along the second direction Y ranges from 10 μm to 22 μm, and can be 11 μm, 15 μm, 17 μm, 19 μm, or 21 μm. The third dimension L13 of the first gate 201 along the second direction Y ranges from 10 μm to 30 μm, and can be 15 μm, 19 μm, 23 μm, 25 μm, or 27 μm.

[0146] For example, refer to Figure 9 and Figure 11 The overlapping region of the orthographic projection of the second gate 601 in the thickness direction Z and the orthographic projection of the semiconductor layer 400 in the thickness direction Z is the second overlapping region S2. The area of ​​the second overlapping region S2 is the second area, that is, the second overlapping region S2 formed by the overlapping of the orthographic projection of the second gate 601 in the thickness direction Z and the orthographic projection of the second sub-region 412 in the thickness direction Z. The area of ​​the second overlapping region S2 is the second area. The first area is larger than the second area. The orthographic projection of the second gate 601 on the substrate completely covers the first gate 201. The first gate can provide induced charge to the non-conductive region blocked by the second gate 601 to better compensate for the phenomenon of insufficient conductivity.

[0147] For example, refer to Figure 9 and Figure 11 The product of the maximum dimension of the first gate 201 along the first direction X and the maximum dimension of the first gate 201 along the second direction Y is the first area, and the product of the maximum dimension of the second gate 601 along the first direction X and the maximum dimension of the first gate 201 along the second direction Y is the second area, and the first area is greater than the second area.

[0148] Figure 12 This is a schematic partial top view of a display substrate provided for an embodiment of this application. For example, refer to... Figure 12 , for example, in combination Figure 3 , Figure 11 and Figure 12 The overlapping region of the orthographic projection of the first gate 201 in the thickness direction Z and the orthographic projection of the semiconductor layer 400 in the thickness direction Z is called the first overlapping region S1. The dimension of the first overlapping region S1 along the first direction X is called the first dimension L11. The first direction X is the direction from the first electrode 602 to the second electrode 603. The overlapping region of the orthographic projection of the second gate 601 in the thickness direction Z and the orthographic projection of the semiconductor layer 400 in the thickness direction Z is called the second overlapping region S2. The dimension of the second overlapping region along the first direction X is called the second dimension L12. The first dimension L11 is larger than the second dimension L12.

[0149] For example, refer to Figure 3 and Figure 12 The size of the conductive region 401 along the first direction ranges from 4 μm to 9 μm. For example, the size of the conductive region 401 along the first direction can be 5 μm, 6 μm, 7 μm, or 8 μm. The size of the non-conductive region 402 along the first direction X ranges from 4 μm to 31 μm. For example, the size of the non-conductive region 402 along the first direction X can be 8 μm, 10 μm, 13 μm, 15 μm, 20 μm, 25 μm, 27 μm, or 29 μm. The first dimension L11 of the first overlapping region S1 along the first direction X ranges from 10 μm to 22.5 μm. For example, the first dimension L11 of the first overlapping region S1 along the first direction X can be 12.5 μm, 14.5 μm, 15 μm, 17.5 μm, 19.5 μm, or 21.5 μm. The ratio of the maximum dimension of the semiconductor layer 400 along the first direction X to the maximum dimension of the first overlapping region S1 along the first direction X is greater than 2.

[0150] For example, refer to Figure 3 , Figure 9 and Figure 12The second dimension L12 of the second overlapping region S2 along the first direction X ranges from 6 μm to 8 μm, and the dimension range of the second dimension L12 of the second overlapping region S2 along the first direction X is the same as the dimension range of the second gate 601 along the first direction X. For example, the second dimension L12 can be 6.5 μm, 6.8 μm, 7 μm, 7.5 μm, or 7.8 μm. The ratio of the maximum dimension of the semiconductor layer 400 along the first direction X to the maximum dimension of the second overlapping region S2 along the first direction X is greater than 4.

[0151] For example, the ratio of the maximum size of the first overlapping region S1 along the first direction X to the maximum size of the second overlapping region S2 along the first direction X is greater than 2.

[0152] For example, refer to Figures 3 to 12 The first electrode 602 has a size ranging from 9.5 μm to 14 μm along the first direction X. For example, the size of the first electrode 602 along the first direction X can be 10 μm, 11 μm, 12 μm, or 13 μm. The second electrode 603 has a size ranging from 5 μm to 8 μm along the first direction X. For example, the size of the second electrode 603 along the first direction X can be 6 μm, 6.5 μm, 7 μm, or 7.5 μm. The ratio of the maximum size of the first electrode 602 along the first direction X to the maximum size of the second electrode 603 along the first direction X is greater than 1.5.

[0153] For example, refer to Figure 3 , Figure 9 , Figure 11 and Figure 12 The first overlapping region S1 has the same size range along the second direction Y as the semiconductor layer 400 along the second direction Y. The second overlapping region S2 also has the same size range along the second direction Y as the semiconductor layer 400. For example, the size of the semiconductor layer 400 along the second direction Y can be 4.1 μm, 4.5 μm, 4.9 μm, 5.5 μm, or 5.9 μm.

[0154] For example, in combination Figure 3 and Figure 12The first electrode 602 covers the second insulating layer 500 with a first coverage dimension j of 2.5 μm along the first direction X. The second electrode 603 covers the second insulating layer 500 with a second coverage dimension g of 1 μm along the first direction X. The conductor region 401 has a conductor width e of 2 μm along the first direction X. The gate line G has a first linewidth a of 2.5 μm along the second direction, and the data signal line 202 body has a second width b of 2.5 μm along the second direction Y. The edge of the second gate 601 extends beyond the edge of the semiconductor layer 400 along the second direction Y by a first coverage dimension c of 3 μm. By setting the edge of the second gate 601 to extend beyond the edge of the semiconductor layer 400 along the second direction Y, the second gate 601 can completely cover the semiconductor layer 400, preventing the channel region from being conductord during the conductor formation process. The third width d of the third structural portion 213 along the first direction X is 3μm, which lengthens the first gate 201 along the first direction X to compensate for the non-conductive region 402, while ensuring that the length of the channel region is precisely defined by the second gate 601, thus improving uniformity. The first distance k between the data signal line 202 and the first gate 201 along the first direction X is 4.5μm. The second distance h between the semiconductor layer 400 and the second gate 601 along the second direction Y is 6μm. The connecting via between the first gate 201 and the second gate 601 is the fifth via H5, and the third distance m between the fifth via H5 and the channel region along the second direction Y is 2μm, wherein the channel region overlaps with the semiconductor layer 400.

[0155] It should be noted that the size settings of the display substrate provided in this application embodiment can be adjusted within a corresponding size range according to the actual product size requirements, and the specific size settings are not listed one by one.

[0156] The display substrate provided in this application embodiment sets the size relationship between the first gate, the second gate, and the semiconductor layer so that the projections of the first gate, the second gate, and the semiconductor layer overlap with each other. By setting the overlapping area of ​​the orthographic projection of the first gate on the substrate layer and the orthographic projection of the semiconductor layer on the substrate layer to be greater than the overlapping area of ​​the orthographic projection of the second gate on the substrate layer and the orthographic projection of the semiconductor layer on the substrate layer, the semiconductor layer blocked by the second gate is compensated, thereby stimulating the carriers of the semiconductor layer and providing more power supply current for the sub-pixels.

[0157] Figure 13 This is a schematic partial structural diagram of a display substrate provided for an embodiment of this application. For example, as shown... Figure 13As shown, the second insulating layer 500 includes a first via H1, and the first electrode 602 is electrically connected to the semiconductor layer 400 through the first via H1. The first electrode 602 covers the edge of the second insulating layer 500 of the first via H1, and the first electrode 602 can completely cover the exposed surface of the semiconductor layer 400 of the first via H1. The second electrode 603 covers the edge of the second insulating layer 500 of the first via, and the second electrode 603 completely covers the exposed surface of the semiconductor layer 400 of the first via H1. The first electrode is electrically connected to the data signal line 202 through the first via H1, and the second electrode 603 is electrically connected to the semiconductor layer 400 through the first via H1. By setting the first electrode 602 and the second electrode 603 to completely cover the first via H1 and partially cover the edge of the second insulating layer 500 of the first via H1, over-etching of the semiconductor layer 400 below the second insulating layer 500 can be avoided during the fabrication of the second conductive layer 600. This avoids the display panel cracking problem caused by the step difference between the second conductive layer 600 and the upper film layer due to over-etching, and improves the stability of the display panel.

[0158] For example, refer to Figure 3 , Figures 5 to 7 as well as Figure 13 The first electrode 602 at least partially covers the edge of the semiconductor layer 400 and at least partially covers the second insulating layer 500. The semiconductor layer 400 has no vias. The first electrode 602 bypasses the semiconductor layer 400 and is directly electrically connected to the data signal line 202 through a first via H1 and a third via H3. The orthographic projection of the third via H3 onto the substrate layer 100 falls within the orthographic projection of the first via H1 onto the substrate layer 100, and also falls within the orthographic projection of the data signal line 202 onto the substrate layer 100. The second electrode 603 partially covers the second insulating layer 500 and is electrically connected to the pixel electrode through the first via H1.

[0159] Figure 14 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 14As shown, the first insulating layer 300 includes a third via H3, and the semiconductor layer 400 includes a fourth via H4. The first via H1 communicates with the fourth via H4, and the fourth via H4 communicates with the third via H3. The first electrode 602 is electrically connected to the data signal line 202 through the first via H1, the fourth via H4, and the third via H3. The second electrode 603 is electrically connected to the pixel electrode through the first via H1. The orthographic projections of the third via H3 and the fourth via H4 on the substrate 100 both fall within the orthographic projection of the data signal line 202 on the substrate 100. The orthographic projection of the semiconductor layer 400 on the substrate 100 completely covers the orthographic projection of the protrusion 202-1 on the substrate 100. The orthographic projection of the first via H1 on the substrate 100 can cover the orthographic projection of the third via H3 on the substrate 100, and also cover the orthographic projection of the fourth via H4 on the substrate 100. By setting the third via H3 and the fourth via H4, on the one hand, the first electrode 602, the semiconductor layer 400 and the second insulating layer 500 can be connected, and on the other hand, the step difference between the second conductive layer 600 and the second insulating layer 500 can be reduced, so as to improve the coverage of the film layer above the second conductive layer and avoid the problem of cracks in the display panel caused by excessive film layer step difference.

[0160] Figure 15 This is a schematic partial structural diagram of a display substrate provided for an embodiment of this application. For example, as shown... Figure 15 As shown, the second insulating layer 500 includes a first via H1. The first via H1 is electrically connected to the semiconductor layer 400, and the second electrode 603 is electrically connected to the semiconductor layer through the first via H1. Exposed regions H11 are provided between the first electrode 602 and the second gate 601, and between the second electrode 603 and the second gate 601. Exposed regions H11 expose a portion of the surface of the semiconductor layer 400 away from the substrate layer 100. The orthographic projection of the exposed region H11 onto the substrate layer 100 does not overlap with the orthographic projection of the first electrode 602 onto the substrate layer 100, nor does it overlap with the orthographic projection of the second electrode 603 onto the substrate layer 100. By providing exposed regions between the first electrode and the second gate, and between the second electrode and the second gate, more ions can be implanted into the semiconductor layer during the conductor-encapsulation process, improving the conductivity of the driving transistor.

[0161] Figure 16 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 16As shown, the second insulating layer 500 includes a first via H1 and a second via H2. The first electrode 602 is electrically connected to the semiconductor layer 400 through the first via H1, and the second electrode 603 is also electrically connected to the semiconductor layer 400 through the first via H1. The orthographic projection of the first via H1 onto the substrate layer 100 overlaps with the orthographic projection of the first electrode 602 onto the substrate layer 100, and the orthographic projection of the first via H1 onto the substrate layer 100 overlaps with the orthographic projection of the second electrode 603 onto the substrate layer 100. The first via H1 includes an exposed region H11, which is disposed between the first electrode 602 and the first gate 602. The exposed region H11 exposes a portion of the surface of the semiconductor layer 400 away from the substrate layer 100. The orthographic projection of the exposed region H11 on the substrate 100 does not overlap with the orthographic projection of the first electrode 602 on the substrate 100, nor does it overlap with the orthographic projection of the second electrode 603 on the substrate 100. By providing the exposed region H11 between the first electrode and the second gate, and by providing the second via between the second electrode and the second gate, more ions can be implanted into the semiconductor layer during the conductor-encapsulation process, thereby improving the conductivity of the driving transistor.

[0162] Figure 17 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 17 As shown, the second insulating layer 500 includes a second via H2, which can be disposed in the gap region between the second gate 601 and the second electrode 603. The second via H2 can also be disposed in the gap region between the second gate 601 and the first electrode 602. The second via H2 can be disposed simultaneously in both the gap region between the second gate 601 and the second electrode 603 and the gap region between the second gate 601 and the first electrode 602. The orthographic projection of the second via H2 onto the substrate layer 100 does not overlap with the orthographic projection of the first via H1 onto the substrate layer 100, and the orthographic projection of the second via H2 onto the substrate layer 100 falls within the orthographic projection of the first gate 201 onto the substrate layer 100. The second via H2 is used to expose a portion of the semiconductor layer surface away from the substrate layer, facilitating the conductor-forming process of the semiconductor layer 400.

[0163] In some embodiments, the first electrode 602 covers a portion of the edge of the semiconductor layer 400. The area of ​​the semiconductor layer 400 covered by the first electrode 602 is greater than or equal to the area of ​​the semiconductor layer 400 covered by the second electrode 603.

[0164] For example, refer to Figures 13 to 17The first electrode 602 has a size ranging from 2.5 μm to 5 μm along the first direction X, and its size along the first direction X can be 2.8 μm, 3 μm, 3.5 μm, 4 μm, or 4.5 μm. The first electrode 602 has a size ranging from 6 μm to 8 μm along the second direction Y, and its size along the second direction Y can be 6.5 μm, 6.8 μm, 7 μm, 7.5 μm, or 7.8 μm. The second electrode 603 has a size ranging from 1 μm to 5 μm along the first direction X, and its size along the first direction X can be 2.3 μm, 3.5 μm, 4 μm, 4.5 μm, or 4.9 μm. The second electrode 603 has a size ranging from 6 μm to 8 μm along the second direction Y, and its size along the second direction Y can be 6.1 μm, 6.5 μm, 7.3 μm, 7.5 μm, or 7.9 μm. The area covered by the first electrode 602 over the semiconductor layer 400 is greater than or equal to the area covered by the second electrode 603 over the semiconductor layer 400. By configuring the first electrode 602 and the second electrode 603 to cover the semiconductor layer, the space occupied by the electrodes is rationally planned, thereby improving the consistency of the fabrication of the second conductive layer.

[0165] Figure 18 This is a schematic partial structural diagram of a display substrate provided for an embodiment of this application. For example, as shown... Figure 18 As shown, the second insulating layer 500 includes a gate insulating structure 501, which is located between the first electrode 602 and the second electrode 603. The orthographic projection of the second gate 601 on the substrate layer 100 falls within the orthographic projection of the gate insulating structure 501 on the substrate layer 100. The gate insulating structure 501 includes a fourth structural portion 511, a fifth structural portion 512, and a sixth structural portion 513, with the fifth structural portion 512 connecting the fourth structural portion 511 and the sixth structural portion 513. The orthographic projection of the fifth structural portion 512 on the substrate layer 100 coincides with the orthographic projection of the second gate 601 on the substrate layer 100, while the orthographic projections of the fourth structural portion 511 and the sixth structural portion 513 on the substrate layer 100 do not overlap with the orthographic projection of the second gate 601 on the substrate layer 100. By configuring the fourth and sixth structural portions, the orthogonal projection of the second gate 601 onto the substrate 100 can be completely contained within the orthogonal projection of the gate insulating structure 501 onto the substrate. Specifically, the edge of the orthogonal projection of the gate insulating structure 501 below the second gate 601 onto the substrate 100 extends beyond the edge of the orthogonal projection of the second gate 601 onto the substrate 100. This avoids excessive step differences between the second gate 601, the second insulating layer 500, and the semiconductor layer 400 during the fabrication of the second gate 601. Consequently, it prevents cracking of the film layer above the second conductive layer 600 due to excessive film layer step differences, and also prevents moisture intrusion that could oxidize the second conductive layer, causing the driving transistor to fail, thus improving product reliability.

[0166] For example, refer to Figures 3 to 18 The orthographic projection of the second gate 601 on the substrate 100 falls completely within the orthographic projection of the gate insulating structure 501 on the substrate. That is, the edge of the orthographic projection of the gate insulating structure 501 below the second gate 601 on the substrate 100 exceeds the edge of the orthographic projection of the second gate 601 on the substrate 100. By lengthening the width of the gate insulating mechanism in the first direction X, the step difference between the second gate 601, the second insulating layer 500, and the semiconductor layer 400 can be reduced. This avoids cracking of the film layer above the second conductive layer 600 due to excessive film layer step difference, and also avoids moisture intrusion that could cause oxidation of the second conductive layer, leading to failure of the driving transistor and improving product reliability.

[0167] For example, refer to Figures 3 to 7 , Figures 13 to 18 As shown, the data signal line 202 is disposed on the same layer as the first gate 201. By placing the data signal line in the first conductive layer, the space occupied by the data signal is reduced, so as to reasonably wire the circuit and reasonably arrange the first electrode, the second electrode and the first gate, thereby improving the aperture ratio of the display substrate.

[0168] For example, such as Figure 18 As shown, the orthographic projection boundary of the fourth structural portion 511 near the first electrode 602 on the substrate 100 is the seventh boundary K7, and the orthographic projection boundary of the second gate 601 near the first electrode 602 on the substrate 100 is the fifth boundary K5. The distance between the seventh boundary K7 and the fifth boundary K5 is the fifth distance L5. The orthographic projection boundary of the sixth structural portion 513 near the second electrode 603 on the substrate 100 is the eighth boundary K8, and the orthographic projection boundary of the second gate 601 near the second electrode 603 on the substrate 100 is the sixth boundary K6. The distance between the eighth boundary K8 and the sixth boundary K6 is the sixth distance L6. The fifth distance L5 can be equal to the sixth distance L6 to ensure that the step difference between the second gate 601 and the second insulating layer 500 on the adjacent side remains consistent, thereby improving the consistency of film fabrication.

[0169] For example, the fifth distance L5 can be greater than or equal to 1 μm, and the sixth distance L6 can be greater than or equal to 1 μm.

[0170] For example, the fifth distance L5 can be 1.5μm, 2.5μm, 3.5μm, 4.5μm, or 5.5μm. The sixth distance L6 can be 1.5μm, 2.5μm, 3.5μm, 4.5μm, or 5.5μm.

[0171] In some implementations, reference Figure 18The orthographic projection of the gate insulating structure 501 on the substrate 100 falls within the orthographic projection of the first gate 201 on the substrate 100. The orthographic projection of the fifth structural portion 512 on the substrate 100 completely coincides with the orthographic projection of the second structural portion 212 on the substrate 100. The orthographic projection of the fourth structural portion on the substrate 100 at least partially coincides with the orthographic projection of the first structural portion on the substrate 100, and the orthographic projection of the sixth structural portion on the substrate 100 at least partially coincides with the orthographic projection of the third structural portion on the substrate 100. By setting the orthographic projection of the second gate 601 on the substrate 100 to fall within the orthographic projection of the second insulating layer 500 on the substrate 100, and by setting the orthographic projection of the gate insulating structure 501 on the substrate 100 to fall within the orthographic projection of the first gate 201 on the substrate 100, the orthographic projection of the gate insulating structure 501 on the substrate 100 is made to fall within the orthographic projection of the first gate 201 on the substrate 100. While lengthening the first gate 201, the second insulating layer 500 is also lengthened. This can avoid the step difference between the second insulating layer 500, the second conductive layer 600 and the film layer above the second conductive layer, and at the same time, it can achieve the conductor treatment of the semiconductor layer, so as to avoid cracks in the display panel and meet the stable light output of the display panel.

[0172] Figure 19 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. For example, as shown... Figure 19As shown, the display substrate further includes a third insulating layer 610, a fourth insulating layer 620, a first planarization layer 700, a third conductive layer 900, a fifth insulating layer 810, and a fourth conductive layer 800. The third insulating layer 610, the fourth insulating layer 620, the first planarization layer 700, the third conductive layer 900, the fifth insulating layer 810, and the fourth conductive layer 800 can all be referred to as the upper film layer of the second conductive layer. The third insulating layer 610 is disposed on the side of the second conductive layer 600 away from the substrate layer 100, and the third insulating layer 610 includes a seventh via H7. The fourth insulating layer 620 is disposed on the side of the third insulating layer 610 away from the substrate layer 100, and the fourth insulating layer 620 includes an eighth via H8. The first planarization layer 700 is disposed on the side of the third insulating layer 610 away from the substrate layer 100, and the first planarization layer 700 includes a ninth via H9. The third conductive layer 900 is disposed on the side of the first planarization layer 700 away from the substrate layer 100. A fourth conductive layer 800 is disposed between a fifth insulating layer 810 and a first planarization layer 700. The fifth insulating layer 810 is disposed between a third conductive layer 900 and a fourth conductive layer 800, and includes a tenth via H10. The third conductive layer 900 includes a first pixel electrode 901, and the fourth conductive layer 800 includes a second pixel electrode 801. The first pixel electrode 901 is electrically connected to the second electrode 603 through a sixth via and a fifth via. A data signal line 202 is electrically connected to the first electrode 602. The third conductive layer 900 and the fourth conductive layer 800 are connected to form a liquid crystal capacitor, allowing data signals to be transmitted to the pixel electrode through the first electrode 602, the semiconductor layer 400, and the second electrode 603, ensuring the charging rate of the pixel electrode and achieving stable display of the image on the display panel.

[0173] For example, the data signal is transmitted to the pixel electrode through the driving transistor to form a capacitor, thereby improving the charging rate of the pixel electrode and avoiding display problems caused by insufficient power supply current.

[0174] In some embodiments, the display substrate further includes a plurality of sub-pixels and a plurality of gate lines arranged in an array. Each sub-pixel includes a first pixel electrode 901, a second pixel electrode 801, and a driving transistor. The driving transistor includes a first gate 201, a semiconductor layer 400, a first electrode 602, a second electrode 603, and a second gate 601. The gate lines are electrically connected to the driving transistors, and at least four gate lines connect to the same row of sub-pixels. The gate lines may be disposed on the same layer as the first gate 201 or the second gate 601.

[0175] For example, at least four gate lines are configured to provide a signal to one row of sub-pixels in a multi-row configuration. At least one of the gate lines is located between the light-emitting regions of the nth row of sub-pixels and the (n-1)th row of sub-pixels. At least one of the gate lines is located between the light-emitting regions of the nth row of sub-pixels and the (n+1)th row of sub-pixels. At least two other gate lines intersect the light-emitting region of the nth row of sub-pixels. The (n-1)th, nth, and (n+1)th row sub-pixels are arranged in an array along a second direction Y, where Y is the length direction of the data signal, and n is a natural number greater than 0.

[0176] Figure 20 This is a schematic partial top view of a display substrate provided for an embodiment of this application. For example, as shown... Figure 20 As shown, the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4 can provide gate drive signals to the nth row of sub-pixels in a multi-row sub-pixel network. The first gate line G1 can be positioned between the light-emitting areas of the nth row of sub-pixels and the (n-1)th row of sub-pixels. The fourth gate line G4 can be positioned between the light-emitting areas of the nth row of sub-pixels and the (n+1)th row of sub-pixels; the second gate line G2 and the third gate line G3 can intersect with the nth row of sub-pixels. The light-emitting areas of each sub-pixel are located in... Figure 12 The Chinese character is represented as LA. Figure 12 BM represents the light-shielding layer. By arranging multiple grid lines in an array and setting at least four grid lines to drive a row of sub-pixels, space occupied by grid lines is saved, and reasonable wiring of the display panel is achieved.

[0177] It should be noted that the first direction X is the row extension direction, and the second direction Y is the column extension direction.

[0178] In some embodiments, the display substrate includes multiple repeating data signal transmission lines and multiple pixel units. A row of subpixels may include multiple subpixel units. Subpixels of the same color within the same pixel unit are connected to the same data signal transmission line, wherein each data signal transmission line of the same color may connect multiple subpixels of different colors in a row of subpixels. Two adjacent columns of subpixels of different colors may be connected to the same gate line. The subpixels, through the combined action of the gate line and the data transmission signal line, control the liquid crystal flipping to complete light emission.

[0179] For example, Figure 21 A schematic partial top view of another display substrate provided in an embodiment of this application. Exemplary, such as... Figure 21As shown, the smallest repeating unit of subpixels of different colors in the display substrate includes 24 columns of subpixels, corresponding to six data signal transmission lines. The smallest repeating unit of subpixels of different colors refers to the smallest group of subpixels, each group corresponding to a different color, typically including red, green, and blue subpixels, which are regularly repeated across the entire display substrate to form the complete pixel structure of the display panel. The arrangement of these repeating units defines the basic arrangement of the subpixels, ensuring the proper distribution of different colors in the display panel.

[0180] For example, refer to Figure 21 The area enclosed by the dashed box A3 represents the smallest repeating unit where driving transistors are connected to gate lines. In some embodiments, in the smallest repeating unit where driving transistors are connected to gate lines, each gate line is connected to two driving transistors. The smallest repeating unit where driving transistors are connected to gate lines refers to the minimum arrangement of driving transistors and gate lines formed within the repeating unit throughout the entire display substrate. The smallest repeating unit where driving transistors are connected to gate lines can be configured with specific patterns or arrangements to connect driving transistors to gate lines, thereby ensuring the uniformity and consistency of display driving.

[0181] For example, refer to Figure 21 Multiple gate lines extend along a first direction X, and multiple data lines extend along a second direction Y. The multiple gate lines may include a first gate line G1, a second gate line G2, a third gate line G3, a fourth gate line G4…a twelfth gate line G12. The multiple data signal transmission lines may include a first data signal transmission line RD1, a second data signal transmission line GD1, a third data signal transmission line BD1, a fourth data signal transmission line RD2, a fifth data signal transmission line GD2, and a sixth data signal transmission line BD2. The first data signal transmission line RD1 can provide data signals to multiple columns of red sub-pixels. The fourth data signal transmission line RD2 can provide data signals to different columns of red sub-pixels. The second data signal transmission line GD1 can provide data signals to multiple columns of green sub-pixels. The fifth data signal transmission line GD2 can provide data signals to different columns of green sub-pixels. The third data signal transmission line BD1 can provide data signals to multiple columns of blue sub-pixels. The sixth data signal transmission line BD2 can provide data signals to different columns of blue sub-pixels.

[0182] In some embodiments, reference Figure 21The system comprises multiple gate lines, including a first gate line G1, a second gate line G2, a third gate line G3, and a fourth gate line G4 arranged sequentially along the second direction Y. The smallest repeating unit connecting the driving transistors to the gate lines comprises a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, a fourth sub-pixel sp4, a fifth sub-pixel sp5, a sixth sub-pixel sp6, a seventh sub-pixel sp7, and an eighth sub-pixel sp8 arranged sequentially along the first direction X. The first gate line G1 connects to the driving transistors in the first sub-pixel sp1 and the second sub-pixel sp2; the third gate line G3 connects to the driving transistors in the third sub-pixel sp3 and the fourth sub-pixel sp4; the second gate line G2 connects to the driving transistors in the fifth sub-pixel sp5 and the sixth sub-pixel sp6; and the fourth gate line G4 connects to the driving transistors in the seventh sub-pixel sp7 and the eighth sub-pixel sp8. By using multiple gate lines, multiple data signal transmission lines, and multiple repeating sub-pixel units, the spatial layout of the signal lines can be rationally planned, while ensuring the uniformity and consistency of the display driving.

[0183] A second aspect of this application provides a method for preparing a display substrate. Figure 22 This is a process flow diagram of a display panel manufacturing method provided in an embodiment of this application. Figure 23 This is a process flow diagram of another display panel fabrication method provided in an embodiment of this application. Figures 22 to 23 As shown, the method for fabricating the display substrate includes two stages. The first stage includes steps S100 to S600, and the second stage includes steps S700 to S910. The method for fabricating the display substrate of this application is as follows:

[0184] S100: A first conductive thin film layer 220 is provided on one side of the substrate layer 100.

[0185] S200: The first conductive thin film layer 220 is etched to obtain the first conductive layer 200, wherein the first gate 201 and data signal line 202 are obtained after etching. The etching may include photolithography and wet etching.

[0186] S300: A first insulating layer 300 and a semiconductor thin film layer 420 are sequentially disposed on the side of the first conductive layer 200 away from the substrate layer 100, wherein the orthogonal projection of the semiconductor thin film layer 420 on the substrate layer 100 covers the orthogonal projection of the first gate 201 on the substrate layer 100.

[0187] S400: The semiconductor thin film layer 420 is etched to obtain the semiconductor layer 400. The orthogonal projection of the semiconductor layer 400 on the substrate layer 100 covers the orthogonal projection of the first gate 201 on the substrate layer 100.

[0188] S500: A second insulating layer 500 and a second conductive layer 600 are sequentially disposed on the side of the semiconductor layer 400 away from the substrate layer 100.

[0189] S600: The second conductive layer 600 is etched to obtain the second gate 601, the first electrode 602 and the second electrode 603. The first electrode 602 is connected to one end of the semiconductor layer 400, and the second electrode 603 is connected to the other end of the semiconductor layer 400. The data signal line 202 is electrically connected to the first electrode 602. The orthographic projection of the second gate 601 on the substrate layer 100 falls into the orthographic projection of the first gate 201 on the substrate layer 100.

[0190] The first gate 201 includes a first structural portion 211, a second structural portion 212, and a third structural portion 213. The second structural portion 212 is connected between the first structural portion 211 and the third structural portion 213. The orthographic projection of the second structural portion 212 on the substrate 100 overlaps with the orthographic projection of the second gate 601 on the substrate 100. The orthographic projections of the first structural portion 211 and the third structural portion 213 on the substrate 100 do not overlap with the orthographic projection of the second gate 601 on the substrate 100.

[0191] S700: Photoresist is applied to the side of the etched second conductive layer 600 away from the substrate layer 100.

[0192] S800: The photoresist is exposed and developed to obtain a patterned photoresist. The orthogonal projection of the patterned photoresist on the substrate layer covers the non-conductive region 402 to obtain a transition substrate. The non-conductive region 402 is the region where the semiconductor layer 400 is covered by the second conductive layer 600.

[0193] S900: Conducting a conductive process on the transition substrate to make the semiconductor layer conductive in areas other than the non-conductive region, resulting in a conductive region 401, and thus a display substrate.

[0194] Step S900 further includes S910: removing the photoresist and simultaneously fabricating a third insulating layer 610, a fourth insulating layer 620, a first planarization layer 700, a third conductive layer 900, a fifth insulating layer 810, and a fourth conductive layer 800 on the side of the second conductive layer away from the substrate layer 100. The third insulating layer 610 includes a seventh via H7. The fourth insulating layer 620 includes an eighth via H8. The first planarization layer 700 includes a ninth via H9. The fifth insulating layer 810 includes a tenth via H10. The third conductive layer 900 includes a first pixel electrode 901, and the fourth conductive layer 800 includes a second pixel electrode 801. The first pixel electrode 901 is electrically connected to the second electrode 603 through a sixth via and a fifth via. The data signal line 202 is electrically connected to the first electrode 602, and the third conductive layer 900 and the fourth conductive layer 800 are connected to form a liquid crystal capacitor, so that the data signal can be transmitted to the pixel electrode through the first electrode 602, the semiconductor layer 400 and the second electrode 603 to realize the display of the screen on the display panel.

[0195] This application provides a method for fabricating a display panel. By setting a double-gate structure and extending the first gate along the first direction X, the orthogonal projections of the second gate on the substrate, the first gate on the substrate, and the semiconductor layer on the substrate overlap. In the case of insufficient semiconductor conductivity, the first gate can excite the carriers in the non-conductive region of the semiconductor layer, improve the conductivity of the semiconductor layer in the non-conductive region, reduce the contact resistance between the first and second electrodes, increase the supply current, and thus improve the performance of the driving transistor. This provides sufficient supply current to the pixel electrode, enabling the sub-pixels to emit light stably, avoiding uneven display brightness and bright / dark lines caused by insufficient supply current, and improving the display effect of the display panel.

[0196] A third aspect of the embodiments of this application provides a display panel, including the display substrate of the first aspect. Figure 24 This is a schematic structural diagram of a display panel provided in an embodiment of this application.

[0197] For example, such as Figure 24 As shown, in a liquid crystal display, the display panel includes a display substrate 1000, a liquid crystal layer 1001, and a color filter substrate 1002, the color filter substrate including a light-shielding layer.

[0198] For example, an LCD display module includes a backlight and a display panel.

[0199] For example, in an OLED, the display panel includes a display substrate and a light-emitting device.

[0200] The display panel provided in this application embodiment features a dual-gate structure with upper and lower sections. The first gate, located below the semiconductor, is elongated along a first direction. This increases the overlapping area of ​​the orthogonal projections of the second gate, the first gate, and the semiconductor layer onto the substrate. In cases of insufficient semiconductor conductivity, the elongated first gate can enhance carrier excitation in the non-conductive region of the semiconductor layer, thereby improving conductivity. This reduces the contact resistance between the first and second electrodes, increases the power supply current, and improves the electrical performance of the driving transistor. Sufficient power supply current is provided to the pixel electrodes, increasing their charging efficiency and enabling stable light emission from sub-pixels. This avoids uneven brightness and bright / dark lines caused by insufficient power supply current, thus improving the display panel's overall display effect.

[0201] A fourth aspect of the embodiments of this application provides a display device. Figure 25 This is a schematic structural diagram of a display device provided in an embodiment of this application. Exemplary. (For example...) Figure 25 As shown, the display device 3000 includes a display panel 2000.

[0202] The display device provided in this application embodiment features a dual-gate structure with upper and lower sections. The first gate, located below the semiconductor, is elongated along a first direction. This increases the overlapping area of ​​the orthographic projections of the second gate, the first gate, and the semiconductor layer onto the substrate. In cases of insufficient semiconductor conductivity, the elongated first gate can enhance the carrier induction excitation in the non-conductive region of the semiconductor layer, thereby improving the conductivity of the semiconductor layer in the non-conductive region. This reduces the contact resistance between the first and second electrodes, increases the supply current, and improves the electrical performance of the driving transistor. Sufficient supply current is provided to the pixel electrode, increasing its charging efficiency and enabling stable light emission from the sub-pixels. This avoids uneven display brightness and bright / dark lines caused by insufficient supply current, thus improving the display effect of the display panel.

[0203] The display devices provided in this application embodiment may include televisions, computers, smartphones, smart wearable devices, laptops, and tablets, etc. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices, etc.

[0204] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0205] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0206] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0207] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate layer; a first conductive layer disposed on one side of the substrate layer, the first conductive layer comprising a first gate and a data signal line; a first insulating layer disposed on a side of the first conductive layer away from the substrate layer; a semiconductor layer disposed on a side of the first insulating layer away from the substrate layer, a projection of the semiconductor layer on the substrate layer covering a projection of the first gate on the substrate layer; a second insulating layer disposed on a side of the semiconductor layer away from the substrate layer; a second conductive layer disposed on a side of the second insulating layer away from the substrate layer, the second conductive layer comprising a second gate, a first electrode and a second electrode, the first electrode being connected to one end of the semiconductor layer, the second electrode being connected to the other end of the semiconductor layer, and the data signal line being electrically connected to the first electrode; the first gate comprising a first structure part, a second structure part and a third structure part, the second structure part being connected between the first structure part and the third structure part, a projection of the second structure part on the substrate layer overlapping a projection of the second gate on the substrate layer, and projections of the first structure part and the third structure part on the substrate layer not overlapping the projection of the second gate on the substrate layer.

2. The display substrate according to claim 1, wherein the projection of the second structure part on the substrate layer coincides with the projection of the second gate on the substrate layer.

3. The display substrate according to claim 2, wherein a boundary of a projection of the first structure part on the substrate layer near one end of the data signal line is a first boundary, a boundary of a projection of the semiconductor layer on the substrate layer near one end of the first electrode is a third boundary, and a distance between the first boundary and the third boundary is a first distance; a boundary of a projection of the third structure part on the substrate layer near one end of the second electrode is a second boundary, a boundary of a projection of the semiconductor layer on the substrate layer near one end of the second electrode is a fourth boundary, and a distance between the second boundary and the fourth boundary is a second distance; the first distance is greater than the second distance; and / or a boundary of a projection of the second gate on the substrate layer near one end of the first electrode is a fifth boundary, and a distance between the fifth boundary and the third boundary is a third distance; a boundary of a projection of the second gate on the substrate layer near one end of the second electrode is a sixth boundary, a distance between the sixth boundary and the fourth boundary is a fourth distance, and the third distance is greater than the fourth distance.

4. The display substrate according to claim 1, wherein a boundary of a projection of the third structure part on the substrate layer near one end of the second electrode is a first boundary; a boundary of a projection of the semiconductor layer on the substrate layer near one end of the second electrode is a second boundary, and the first boundary at least partially coincides with the second boundary.

5. The display substrate according to claim 4, wherein ​ An overlapping area of the first gate and a thickness direction orthographic projection of the semiconductor layer has a first area; An overlapping area of the second gate and a thickness direction orthographic projection of the semiconductor layer has a second area, and the first area is greater than the second area. 6.The display substrate of claim 4, wherein, An overlapping area of the thickness direction orthographic projection of the first gate and the thickness direction orthographic projection of the semiconductor layer is a first overlapping area, and a size of the first overlapping area along a first direction is a first size, the first direction being a direction in which the first electrode points to the second electrode; An overlapping area of the thickness direction orthographic projection of the second gate and the thickness direction orthographic projection of the semiconductor layer is a second overlapping area, and a size of the second overlapping area along the first direction is a second size; The first size is greater than the second size. 7.The display substrate of claim 2, wherein, The second insulating layer includes a first via, and the first electrode and the semiconductor layer are electrically connected through the first via; The first electrode covers the second insulating layer at an edge of the first via, and the first electrode completely covers a surface of the semiconductor layer exposed by the first via. 8.The display substrate of claim 7, wherein, The first insulating layer includes a third via, and the semiconductor layer includes a fourth via; The first via is in communication with the fourth via, the fourth via is in communication with the third via, and the first electrode is electrically connected with the data signal line through the first via, the fourth via, and the third via. 9.The display substrate of claim 2, wherein, The second insulating layer includes a first via, and the first electrode and the semiconductor layer are electrically connected through the first via, and the second electrode and the semiconductor layer are electrically connected through the first via; A thickness direction orthographic projection of the first via on the substrate layer partially overlaps with a thickness direction orthographic projection of the first electrode on the substrate layer, and a thickness direction orthographic projection of the first via on the substrate layer partially overlaps with a thickness direction orthographic projection of the second electrode on the substrate layer. 10.The display substrate of claim 9, wherein, The first via includes an exposed area for exposing a part of a surface of the semiconductor layer away from the substrate layer; A thickness direction orthographic projection of the exposed area on the substrate layer does not overlap with a thickness direction orthographic projection of the first electrode on the substrate layer; And / or, A thickness direction orthographic projection of the exposed area on the substrate layer does not overlap with a thickness direction orthographic projection of the second electrode on the substrate layer. 11.The display substrate of claim 9, wherein, The second insulating layer includes a second via, and the second via is located in a spacing area between the second gate and the second electrode; And / or, the second via is located in a spacing area between the second gate and the first electrode; The second via is used for exposing a part of a surface of the semiconductor layer away from the substrate layer. 12.The display substrate of claim 1, wherein, The first electrode covers an edge of the semiconductor layer; An area of the semiconductor layer covered by the first electrode is greater than or equal to an area of the semiconductor layer covered by the second electrode.

13. The display substrate of claim 1, wherein, The second insulating layer comprises a gate insulating structure, the gate insulating structure is located between the first electrode and the second electrode, and a projection of the second gate electrode on the substrate layer falls within a projection of the gate insulating structure on the substrate layer.

14. The display substrate of claim 13, wherein, The gate insulating structure comprises a fourth structure part, a fifth structure part, and a sixth structure part, the fifth structure part is connected between the fourth structure part and the sixth structure part; A projection of the fifth structure part on the substrate layer coincides with a projection of the second gate electrode on the substrate layer, and projections of the fourth structure part and the sixth structure part on the substrate layer do not overlap with a projection of the second gate electrode on the substrate layer.

15. The display substrate of claim 14, wherein, A boundary of a projection of the fourth structure part on the substrate layer near one end of the first electrode is a seventh boundary, a boundary of a projection of the second gate electrode on the substrate layer near one end of the first electrode is a fifth boundary, and a distance between the seventh boundary and the fifth boundary is a fifth distance; A boundary of a projection of the sixth structure part on the substrate layer near one end of the second electrode is an eighth boundary, a boundary of a projection of the second gate electrode on the substrate layer near one end of the second electrode is a sixth boundary, and a distance between the eighth boundary and the sixth boundary is a sixth distance; The fifth distance is equal to the sixth distance.

16. The display substrate of claim 15, wherein, The fifth distance is greater than or equal to 1 μm; The sixth distance is greater than or equal to 1 μm.

17. The display substrate of claim 14, wherein, A projection of the gate insulating structure on the substrate layer falls within a projection of the first gate electrode on the substrate layer.

18. The display substrate according to any one of claims 1 to 17, characterized in that, Further comprising: A third insulating layer disposed on a side of the second conductive layer away from the substrate layer, the third insulating layer comprising a fifth via hole; A first planar layer disposed on a side of the third insulating layer away from the substrate layer, the first planar layer comprising a sixth via hole; A third conductive layer disposed on a side of the first planar layer away from the substrate layer, the third conductive layer comprising a first pixel electrode; The first pixel electrode is electrically connected to the second electrode through the sixth via hole and the fifth via hole. 19.The display substrate of claim 18, wherein, Comprising: A plurality of sub-pixels arranged in an array, the sub-pixels comprising the pixel electrode and a driving transistor, the driving transistor comprising a first gate electrode, a semiconductor layer, a first electrode, a second electrode, and a second gate electrode; A plurality of gate lines, the gate lines being electrically connected to the driving transistor, and at least four of the gate lines being connected to sub-pixels in the same row.

20. The display substrate of claim 19, wherein, At least one of the gate lines is arranged between the light-emitting regions of the nth row of sub-pixels and the (n-1)th row of sub-pixels; and / or, At least one of the gate lines is arranged between the light-emitting regions of the nth row of sub-pixels and the (n+1)th row of sub-pixels; and / or, At least two of the gate lines are arranged within the light-emitting region of the nth row of sub-pixels, wherein the (n-1)th row of sub-pixels, the nth row of sub-pixels, and the (n+1)th row of sub-pixels are arranged in a second direction, the second direction being the length direction of the data signal, and n is a natural number greater than 0.

21. The display substrate of claim 20, wherein, The sub-pixels of adjacent two columns of different colors are connected to the same gate line. 22.The display substrate of claim 21, wherein, The display substrate comprises a plurality of pixel units and a plurality of data signal transmission lines arranged repeatedly, and the data signal transmission lines are electrically connected to the data signal lines; The pixel unit comprises a plurality of sub-pixels; The sub-pixels of the same color in the same pixel unit are connected to the same data signal transmission line.

23. The display substrate of any one of claims 1 to 17, wherein, The first gate electrode comprises Ti and / or Cu; and / or, The second gate electrode comprises Ti and / or Cu; and / or, The edge slope angle of the second gate electrode ranges from 30° to 40°.

24. The display substrate of any one of claims 1 to 17, wherein, The overlapping area of the first gate electrode in the thickness direction and the overlapping area of the semiconductor layer in the thickness direction is a first overlapping area; The overlapping area of the second gate electrode in the thickness direction and the overlapping area of the semiconductor layer in the thickness direction is a second overlapping area; The ratio of the maximum dimension of the semiconductor layer in the first direction to the maximum dimension of the first overlapping area in the first direction is greater than 2; and / or, The ratio of the maximum dimension of the semiconductor layer in the first direction to the maximum dimension of the second overlapping area in the first direction is greater than 4; and / or, The ratio of the maximum dimension of the first overlapping area in the first direction to the maximum dimension of the second overlapping area in the first direction is greater than 2; and / or, The ratio of the maximum dimension of the first electrode in the first direction to the maximum dimension of the second electrode in the first direction is greater than 1.5; and / or, The first direction is the direction in which the first electrode points to the second electrode.

25. The display substrate of claim 3, wherein, The ratio of the maximum dimension of the second structure in the first direction to the maximum dimension of the third structure in the first direction is greater than 1; and / or, The ratio of the maximum dimension of the second structure in the first direction to the maximum dimension of the first structure in the first direction is greater than 1; and / or, The maximum distance ratio of the first distance to the second distance is greater than 1; and / or, The maximum distance ratio of the third distance to the fourth distance is greater than 1; and / or, The first direction is the direction in which the first electrode points to the second electrode.

26. A display panel comprising: The display substrate comprises: The display substrate of any one of claims 1 to 25.

27. A display device comprising: The display substrate comprises: A display panel as claimed in claim 26.

Images