Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, a gate structure, and a source / drain structure. The fin structure comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are vertically separated from each other, and the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer. The gate structure surrounds the fin structure and is located on the fin structure. The source / drain structure is located on the substrate and adjacent to the fin structure, and the source / drain structure has a uniform critical dimension along the thickness direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned numerous generations of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (i.e., the number of interconnects per wafer area) has generally increased, while geometry (i.e., the size and / or dimensions of IC features and / or the spacing between these features) has decreased. This shrinkage typically provides advantages by increasing production efficiency and reducing associated costs. However, as ICs in advanced node applications continue to shrink to even smaller sub-micron dimensions, reducing channel resistance while maintaining the required current becomes an increasingly significant challenge. Therefore, improved structures and manufacturing methods are needed. Utility Model Content

[0003] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, a gate structure, and a source / drain structure. The fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate and has a first width. The second semiconductor layer is located on the first semiconductor layer, perpendicularly separated from the first semiconductor layer, and has a second width. The third semiconductor layer is located above the second semiconductor layer, perpendicularly separated from the second semiconductor layer, such that the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and has a third width, wherein the first width, the second width, and the third width are equal. The gate structure surrounds the fin structure and is located above the fin structure. The source / drain structure is located on the substrate, adjacent to the fin structure.

[0004] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a first fin structure, a second fin structure, a gate structure, and a source / drain structure. The first fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate and has a first sidewall. The second semiconductor layer is located above the first semiconductor layer and has a second sidewall. The third semiconductor layer is located above the second semiconductor layer, such that the second semiconductor layer is located between the first and third semiconductor layers, and has a third sidewall. The second fin structure includes a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer. The fourth semiconductor layer is located on the substrate and has a fourth sidewall, wherein a first critical dimension is present between the fourth sidewall and the first sidewall. The fifth semiconductor layer is located above the fourth semiconductor layer and has a fifth sidewall, wherein a second critical dimension is present between the fifth sidewall and the second sidewall. The sixth semiconductor layer is located above the fifth semiconductor layer, such that the fifth semiconductor layer is located between the fourth and sixth semiconductor layers, and has a sixth sidewall, wherein a third critical dimension is present between the sixth sidewall and the third sidewall, and the first critical dimension, the second critical dimension, and the third critical dimension are equal. The gate structure surrounds the first fin structure and the second fin structure. The source / drain structure is located on the substrate, between the first fin structure and the second fin structure.

[0005] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, a gate structure, and a source / drain structure. The fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate. A second semiconductor layer is located above the first semiconductor layer and perpendicularly separated from it. A third semiconductor layer is located above the second semiconductor layer and perpendicularly separated from it, such that the second semiconductor layer is located between the first and third semiconductor layers. The gate structure surrounds the fin structure and is located on the fin structure. The source / drain structure is located on the substrate, adjacent to the fin structure, wherein the source / drain structure has a uniform critical dimension along the thickness direction. Attached Figure Description

[0006] The various features disclosed herein can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1 to 5 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments;

[0008] Figures 6 to 23 It is according to some embodiments along Figure 5 A cross-sectional side view of each stage of the semiconductor device manufacturing structure, taken from section AA.

[0009] Figure 16-1 According to some alternative embodiments along Figure 5 The cross-sectional side view of each stage of manufacturing a semiconductor device structure is taken from section AA.

[0010] [Symbol Explanation]

[0011] 100: Semiconductor Device Structure

[0012] 101:Substrate

[0013] 104: Semiconductor layer stacking

[0014] 106: First semiconductor layer

[0015] 108: Second semiconductor layer

[0016] 112: Fin structure

[0017] 114: Trench

[0018] 116:Ibe

[0019] 118: Insulating materials

[0020] 120: Isolation Area

[0021] 130: Sacrificial gate structure

[0022] 132: Sacrificial gate dielectric layer

[0023] 134: Sacrificial gate electrode layer

[0024] 136: Masking layer

[0025] 138: Gate spacer

[0026] 141: Etching Steps

[0027] 143a: Passivation layer

[0028] 143b: Passivation layer

[0029] 143c: Passivation layer

[0030] 144: Internal spacers

[0031] 145: Processing Steps

[0032] 146: S / D characteristics

[0033] 147: Etching Steps

[0034] 148: Faceted Structure

[0035] 149: Processing Steps

[0036] 151: Etching Steps

[0037] 153: Processing Steps

[0038] 155: Etching Step

[0039] 162:CESL

[0040] 164: First ILD layer

[0041] 166: Opening

[0042] 178:IL

[0043] 180: Gate dielectric layer

[0044] 182: Gate electrode layer

[0045] 184: Silicide layer

[0046] 186:S / D Contact

[0047] 190: Alternative gate structure

[0048] 1802: Trench

[0049] 1802bs1: Bottom surface

[0050] 1802bs2: Bottom surface

[0051] 1802bs3: Bottom surface

[0052] 1802bs4: Bottom surface

[0053] 1802s: Sidewall

[0054] AA: Section

[0055] CD1: First critical size

[0056] CD2: Second critical size

[0057] CD3: Third critical size

[0058] D1: Depth

[0059] D2: Depth

[0060] D3: Depth

[0061] D4: Depth

[0062] W1: Width

[0063] X: Direction

[0064] Y: direction

[0065] Z: Direction Detailed Implementation

[0066] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed. Furthermore, for simplicity and clarity, various features may be drawn at any scale.

[0067] Furthermore, for ease of description, this disclosure uses spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the accompanying drawings. The spatially relative terms are intended to cover not only the orientations shown in the drawings but also different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. This device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0068] While the embodiments disclosed herein are discussed in relation to nanostructured channel field-effect transistors (FETs), some of the embodiments described herein can be used in other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Other modifications that can be made within the scope of this disclosure will be readily understood by those skilled in the art. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes, thereby enabling the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Next, remove the sacrificial layer, and then the remaining spacers can be used to pattern the GAA structure.

[0069] Figures 1 to 23 This illustration shows a non-limiting process for manufacturing a semiconductor device structure 100 according to an embodiment of this disclosure. It should be understood that additional embodiments of this method may be implemented. Figures 1 to 23 Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or eliminated. The order of operations / processes is unrestricted and can be interchanged.

[0070] Figures 1 to 5 These are perspective views of various stages in the manufacture of a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), indium phosphide (InP), or combinations thereof. In one embodiment, the substrate 101 is made of silicon. The substrate 101 may be doped or undoped. The substrate 101 may be a host semiconductor substrate, such as a host silicon substrate as a wafer, a silicon-on-insulator (SOI) substrate, a multilayer or gradient substrate, etc.

[0071] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0072] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels, such as nanosheet channel FETs, in multi-gate devices. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked above substrate 101. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0073] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the layers epitaxially grown by the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0074] The first semiconductor layer 106, or a portion thereof, may form nanosheet channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term "nanosheet" is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of such material portion. Thus, the term "nanosheet" refers to an elongated portion of material with a circular or substantially circular cross-section, as well as bundled or rod-shaped portions of material including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0075] Each first semiconductor layer 106 has a thickness ranging from approximately 5 nanometers (nm) to approximately 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from approximately 2 nm to approximately 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are as follows... Figure 1 The alternating configurations shown are for illustrative purposes and are not intended to limit the scope beyond what is specifically described in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on a predetermined number of channels in the semiconductor device structure 100.

[0076] exist Figure 2In this embodiment, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106, a second semiconductor layer 108, and a well portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multi-patterning operation including lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam lithography process. The etching process penetrates the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected area to form trenches 114, thereby leaving multiple extended fin structures 112. The trenches 114 extend along the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114.

[0077] exist Figure 3 In the process, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation such as chemical mechanical polishing (CMP) and / or etching-back is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0078] exist Figure 4In this process, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes a portion of fin structure 112, such as semiconductor layer stack 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of second semiconductor layer 108 in contact with well 116 formed by substrate 101.

[0079] exist Figure 5 In this embodiment, one or more sacrificial gate structures 130 (only two are shown) are formed over a semiconductor device structure 100. The sacrificial gate structures 130 are formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing a blanket layer of these layers and patterning them to form the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers and anisotropically etching the aforementioned one or more layers. Although two sacrificial gate structures 130 are shown, in some embodiments, three or more sacrificial gate structures 130 may be arranged along the X direction.

[0080] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide (SiO2). x The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include multiple layers, such as oxide layers and nitride layers. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or combinations thereof. In some embodiments, the gate spacer 138 may be a bilayer comprising a first dielectric layer 138a (e.g., SiO2) and a second dielectric layer 138b (e.g., SiN).

[0081] A portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100. A portion of the fin structure 112 exposed on the opposite side of the sacrificial gate structure 130 defines the source / drain (S / D) region of the semiconductor device structure 100. In some cases, some S / D regions can be shared among various transistors. For example, individual S / D regions can be connected together and function as a multi-functional transistor. It should be understood that the source and drain regions are used interchangeably because the epitaxial components formed in these regions are substantially the same. Depending on the context, the source / drain region can refer to the source or drain individually or collectively.

[0082] Figures 6 to 23 It is according to some embodiments along Figure 5 A cross-sectional side view of the various stages of the semiconductor device structure 100, taken from section AA.

[0083] Figures 7 to 16 The various stages of a cyclic process for removing fin structure 112 to form a trench in an S / D region (e.g., a region on the opposite side of sacrificial gate structure 130) are illustrated. Specifically, the trench (and subsequent epitaxial S / D components) are formed with a substantially straight vertical sidewall profile. The cyclic process may include multiple processing cycles, each including an etching step, a passivation step, and a processing step. The etching step in each processing cycle is configured to remove a portion of the first semiconductor layer 106 and the second semiconductor layer 108. The passivation step in each processing cycle is configured to protect the exposed surfaces of the trench from over-etching during subsequent etching processes. The processing step in each processing cycle is configured to soften the previously formed passivation layer for easy removal in a subsequent etching step in the next processing cycle. The cyclic process is performed until the desired trench depth is reached.

[0084] Figure 7Etching step 141 of the first processing cycle in the cyclic process is shown. Etching step 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108, thereby forming a trench 1802 with a first depth. A portion of the insulating material 118 surrounding the fin structure 112 may also be removed. Etching step 141 can be a dry etching process, such as RIE, neutral beam etching (NBE), or any suitable anisotropic etching process. In one exemplary embodiment, etching step 141 is a plasma etching process. Etching step 141 may be performed until the topmost second semiconductor layer 108 is completely etched. After etching step 141, the trench 1802 may have a depth D1 defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the trench 1802. In some embodiments, the bottom surface 1802bsl of the trench 1802 is located at or near the interface defined by the topmost second semiconductor layer 108 and the first semiconductor layer 106 immediately below the topmost second semiconductor layer 108.

[0085] Etching step 141 is a plasma etching process using hydrocarbon-based etching chemicals, bromine-based etching chemicals, chlorine-based etching chemicals, fluorine-based etching chemicals, etc. Exemplary hydrocarbon-based etching chemicals may include methane (CH4), ethane (C2H6), propane (C3H8), etc., or combinations thereof. Exemplary bromine-based etching chemicals may include hydrogen bromide (HBr), bromine (Br2), boron tribromide (BBr3), etc., or combinations thereof. Exemplary chlorine-based etching chemicals may include chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), boron trichloride (BCl3), etc., or combinations thereof. Exemplary fluorine-based gases may include tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), difluoromethane (CH2F2), difluoroethane (C2H4F2), trifluoromethane (CHF3), hexafluoroethane (C2F6), and combinations thereof. Diluent gases such as helium (He) and nitrogen (N2) may also be used in combination with etching chemicals. Inert gases, such as argon (Ar), neon (Ne), and krypton (Kr), may be provided to the etching chemicals to increase the bombardment effect and enhance the etching rate of the first semiconductor layer 106 and the second semiconductor layer 108.

[0086] In some embodiments, the plasma etching process may utilize a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source, a dipole antenna plasma source, a resonant antenna plasma source, an electron cyclotron resonance (ECR) plasma source, or a glow discharge plasma (GDP) source driven by an RF power generator, or a microwave plasma source using a tunable frequency ranging from about 2 MHz to about 2.45 GHz, such as about 13.56 MHz. The processing chamber may operate at a pressure ranging from about 5 mTorr to about 20 mTorr and a temperature ranging from about 20 degrees Celsius to about 240 degrees Celsius. The RF power generator operates to provide a source power between about 100 W and about 300 W. A bias power ranging from about 100 W to about 300 W is provided to a substrate support on which the semiconductor device structure 100 is disposed to provide etching directionality. The source power and bias power can be controlled so that the ion acceleration energy is between about 20 eV and about 200 eV. In some cases, pulsed plasma etching can be used. In some cases, the generator output can be controlled by a pulse signal having a duty cycle in the range of about 5% to 95%. Alternatively, the plasma etching process can use only bias power (source power zero). In some embodiments, the plasma etching process can be performed in a plasma etching chamber with in-situ ALD capability. In an exemplary embodiment, the plasma etching process uses a plasma formed from a gas mixture containing, for example, CH4, Cl2, HBr, and CHF3.

[0087] Figure 8 The diagram illustrates the passivation step of the first processing cycle in a cyclic process. The passivation step is performed to form a passivation layer 143a on the exposed surfaces of trench 1802 (such as the sidewalls 1802s and bottom surface 1802bsl of trench 1802). The passivation layer 143a protects the exposed surfaces of trench 1802 from over-etching in the lateral direction during subsequent etching steps. In some embodiments, the passivation layer 143a may be configured to reduce the impact of the exposed surfaces of trench 1802 on subsequent etching processes (such as...). Figure 10The etching selectivity of the etchant in etching step 147) is illustrated. During the passivation step, a bias power is applied to the substrate support to direct most of the etching chemicals to the bottom of trench 1802. Therefore, when the passivation layer 143a at the sidewalls 1802s and bottom surface 1802bs1 of trench 1802 is exposed to the etchant, the rate of removal of the passivation layer 143a at the bottom surface 1802bs1 of trench 1802 is faster than the passivation rate. In this way, the passivation layer 143a reduces the effect of the etchant on the sidewalls 1802s of trench 1802, thereby allowing trench 1802 to extend vertically with a straight and symmetrical sidewall profile during subsequent etching steps. In some embodiments, the passivation layer 143a may have a thickness between about 1 nm and about 3 nm.

[0088] The passivation layer 143a can be a dielectric material or an oxide-based passivation layer, such as SiO, SiON, SiN, SiO2, or any combination thereof. In some embodiments, the passivation layer 143a can be formed by exposing the exposed surface of the trench 1802 to a gas mixture comprising a silicon-containing precursor (e.g., SiCl4), an oxygen-containing precursor (e.g., O2), and / or a nitrogen-containing precursor (e.g., N2). The precursors can flow into the processing chamber simultaneously or sequentially. In some embodiments, hydrogen halides such as hydrogen bromide (HBr) can flow together with the silicon-containing and oxygen-containing precursors. In some embodiments, the passivation layer 143a is deposited by an in-situ ALD process in the same processing chamber as the plasma etching process used for etching step 141. For example, an in-situ ALD technique using precursors such as DIPAS (di(isopropylamino)silane) and BTBAS (bis(tert-butylamino)silane) combined with Ar or O2 plasma treatment can be used to form a silicon-containing thin film. For example, a silicon-containing source gas, such as DIPAS or BTBAS, is provided to the processing chamber, and a plasma of a reactive gas, such as an oxygen-containing gas or a nitrogen-containing gas, is supplied to the processing chamber to form a passivation layer 143a. A silicon-containing film is formed by free radical oxidation from the reactive gas plasma or by a nitride material derived from the silicon-containing source gas.

[0089] In some embodiments, the passivation step may use the same plasma source as etching step 141. The processing chamber may operate at a pressure ranging from about 5 mTorr to about 20 mTorr. An RF power generator operates to provide a source power ranging from about 100 W to about 300 W. During the passivation step, a bias power ranging from about 10 W to about 50 W is provided to the substrate support. In some embodiments, the source power used during the passivation step (e.g., 200 W to about 500 W) is greater than the source power used during etching step 141 (e.g., 100 W to about 300 W), and the bias power used during the passivation step (e.g., 10 W to about 50 W) is lower than the bias power used during etching step 141 (e.g., 100 W to about 300 W). In some embodiments, etching step 141 and the passivation step may be performed in the same processing chamber having in-situ ALD capability. In one exemplary embodiment, the passivation step in the first processing cycle uses, for example, a plasma formed from a gas mixture comprising N2 and / or O2.

[0090] Figure 9 The diagram illustrates processing step 145 of the first processing cycle in the cyclic process. Processing step 145 is performed to bombard and soften the passivation layer 143a. The softened passivation layer 143a can be easily removed during a subsequent etching step in the next processing cycle. Processing step 145 can be a plasma bombardment process using hydrogen (H2), N2, Ar, or any combination thereof. In some embodiments, processing step 145 uses neutral free radicals of substances formed from nitrogen-containing gases, hydrogen-containing gases, or combinations thereof.

[0091] In some embodiments, processing step 145 may utilize the same plasma source as etching step 141. The processing chamber may operate at a pressure in the range of about 50 mTorr to about 100 mTorr. During processing step 145, a bias power is applied to the substrate support to direct most ions and / or radicals to the bottom of trench 1802 to obtain greater directionality. Greater directionality may also be achieved by reducing the frequency of the bias power. In some embodiments, the source power used during processing step 145 (e.g., 50 W to about 100 W) is less than the source power used during etching step 141 (e.g., 100 W to about 300 W), and the bias power used during the passivation step (e.g., 200 W to about 400 W) is greater than the bias power used during etching step 141 (e.g., 100 W to about 300 W). In some embodiments, processing step 145 in the first processing cycle may be performed in the same processing chamber as the passivation step of the first processing cycle.

[0092] Figure 10 The etching step 147 of the second processing cycle in the cyclic process is shown. Etching step 147 is performed to remove the softened passivation layer 143a. Figure 9The first semiconductor layer 106 and the second semiconductor layer 108 are used to form a trench 1802 having a second depth. The trench 1802 is formed to have a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the trench 1802 in the depth direction of the trench 1802. The etching step 147 can be performed using etching chemicals similar to or the same as those used in etching step 141. Except for using a higher bias power, etching step 147 is substantially the same as etching step 141. In some embodiments, the bias power used in etching step 147 of the second processing cycle is greater than the bias power used in processing step 145 of the first processing cycle.

[0093] In one embodiment, the source power used during etching step 147 (e.g., about 100 W to about 300 W) is substantially the same as the source power used during etching step 141 (e.g., about 100 W to about 300 W), and the bias power used during etching step 147 (e.g., about 200 W to about 500 W) is greater than the bias power used during etching step 141 (e.g., about 100 W to about 300 W). Alternatively, the source power used during etching step 147 is greater than the source power used during etching step 141. The processing chamber pressure used during etching step 141 and etching step 147 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In one exemplary embodiment, etching step 147 uses a plasma formed from a gas mixture comprising, for example, CH4, Cl2, HBr, and CHF3.

[0094] Etching step 147 extends the depth of trench 1802. In some embodiments, etching step 147 is performed until the second tallest second semiconductor layer 108 in the semiconductor layer stack 104 is completely etched. After etching step 147, trench 1802 may have a depth D2 defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs2 of trench 1802. In other words, the depth of trench 1802 extends from depth D1 to depth D2. In some embodiments, the bottom surface 1802bs2 of trench 1802 is located at or near the interface defined by the second tallest second semiconductor layer 108 of semiconductor layer stack 104 and the first semiconductor layer 106 immediately below it.

[0095] Figure 11The passivation step of the second processing cycle in the cyclic process is illustrated. The passivation step is performed to form a passivation layer 143b on the exposed surfaces of trench 1802, such as the sidewalls 1802s and bottom surface 1802bs2 of trench 1802. Passivation layer 143b may be formed of the same material as passivation layer 143a. Similarly, passivation layer 143b protects the exposed surfaces of trench 1802 from over-etching in the lateral direction during subsequent etching steps. A bias power may also be applied to the substrate support during the passivation step to direct most of the etching chemicals to the bottom of trench 1802. Passivation layer 143b reduces the effect of the etchant on the sidewalls 1802s of trench 1802. Therefore, trench 1802 can extend vertically with a straight and symmetrical sidewall profile during subsequent etching steps. In some embodiments, passivation layer 143b may have a thickness between about 1 nm and about 3 nm.

[0096] Except for using a higher bias power, the passivation step in the second processing cycle is substantially the same as the passivation step in the first processing cycle. In some embodiments, the bias power used during the passivation step in the second processing cycle (e.g., about 20 W to about 80 W) is greater than the bias power of the passivation step performed in the first processing cycle (e.g., 10 W to about 50 W), and the source power used during the passivation step in the second processing cycle (e.g., about 200 W to about 500 W) is substantially the same as the source power of the passivation step performed in the first processing cycle (e.g., about 200 W to about 500 W). In some embodiments, the passivation step in the second processing cycle may be performed in the same processing chamber as the etching step 147 of the first processing cycle. The processing chamber may be operated at a pressure in the range of about 5 mTorr to about 20 mTorr. In one exemplary embodiment, the passivation step in the second processing cycle uses, for example, a plasma formed from a gas mixture comprising N2 and / or O2.

[0097] Figure 12A processing step 149 of a second processing cycle in a cyclic process is shown. Processing step 149 is performed to bombard and soften the passivation layer 143b, thereby allowing easy removal of the softened passivation layer 143b during a subsequent etching step in the next processing cycle. Processing step 149 of the second processing cycle is substantially the same as processing step 145 of the first processing cycle, except that a greater bias power is used. In some embodiments, the bias power used during processing step 149 of the second processing cycle (e.g., about 300 W to about 500 W) is greater than the bias power of processing step 145 performed in processing step 145 of the second processing cycle (e.g., 200 W to about 400 W), and the source power used during processing step 149 of the second processing cycle (e.g., about 50 W to about 100 W) is substantially the same as the source power of processing step 145 performed in processing step 145 of the second processing cycle (e.g., about 50 W to about 100 W). In some embodiments, processing step 149 in the second processing cycle can be performed in the same processing chamber as the passivation step of the second processing cycle. The processing chamber can operate at pressures in the range of about 50 mTorr to about 100 mTorr.

[0098] Figure 13 The etching step 151 of the third processing cycle in the cyclic process is shown. Etching step 151 is performed to remove the softened passivation layer 143b. Figure 12 The first semiconductor layer 106 and the second semiconductor layer 108 form a third portion of the trench 1802. The third portion of the trench 1802 is formed to have a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the trench 1802 in the depth direction of the trench 1802. The etching step 151 can be performed using an etching chemical similar to or the same as that used in etching step 147. Except for using a higher bias power, etching step 151 is substantially the same as etching step 147. In some embodiments, the bias power used in etching step 151 of the third processing cycle is greater than the bias power used in processing step 149 of the second processing cycle.

[0099] In one embodiment, the source power used during etching step 151 (e.g., about 100 W to about 300 W) is substantially the same as the source power used during etching step 147 performed in the second processing cycle (e.g., about 100 W to about 300 W), and the bias power used during etching step 151 (e.g., about 300 W to about 600 W) is greater than the bias power used during etching step 147 performed in the second processing cycle (e.g., about 200 W to about 500 W). Alternatively, the source power used during etching step 151 is greater than the source power used during etching step 147. The processing chamber pressure used during etching step 151 and etching step 147 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In one exemplary embodiment, etching step 151 uses a plasma formed from a gas mixture comprising, for example, CH4, Cl2, HBr, and CHF3.

[0100] Etching step 151 extends the depth of trench 1802. In the case where the fin structure 112 includes three second semiconductor layers 108, etching step 147 is performed until the third highest second semiconductor layer 108 of the semiconductor layer stack 104 is completely etched. After etching step 151, trench 1802 may have a depth D3, defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs3 of trench 1802. In other words, the depth of trench 1802 extends from depth D2 to depth D3. In some embodiments, the bottom surface 1802bs3 of trench 1802 is located at or near the interface defined by the third highest second semiconductor layer 108 of semiconductor layer stack 104 and the first semiconductor layer 106 immediately below it.

[0101] Figure 14 The passivation step of the third processing cycle in the cyclic process is illustrated. The passivation step is performed to form a passivation layer 143c on the exposed surfaces of trench 1802, such as the sidewalls 1802s and bottom surface 1802bs3 of trench 1802. Passivation layer 143c may be formed of the same material as passivation layer 143a. Similarly, passivation layer 143c protects the exposed surfaces of trench 1802 from over-etching in the lateral direction during subsequent etching steps. A bias power is also applied to the substrate support during the passivation step to direct most of the etching chemicals to the bottom of trench 1802. Passivation layer 143c reduces the effect of the etchant on the sidewalls 1802s of trench 1802. Therefore, trench 1802 can extend vertically with a straight and symmetrical sidewall profile during subsequent etching steps. In some embodiments, passivation layer 143c may have a thickness between about 1 nm and about 3 nm.

[0102] Except for using a higher bias power, the passivation step in the third processing cycle is substantially the same as the passivation step in the second processing cycle. In some embodiments, the bias power used during the passivation step in the third processing cycle (e.g., about 50 W to about 100 W) is greater than the bias power used during the passivation step performed in the second processing cycle (e.g., 20 W to about 80 W), and the source power used during the passivation step in the third processing cycle (e.g., about 200 W to about 500 W) is substantially the same as the source power used during the passivation step performed in the second processing cycle (e.g., about 200 W to about 500 W). In some embodiments, the passivation step in the third processing cycle may be performed in the same processing chamber as the etching step 151 of the second processing cycle. The processing chamber may be operated at a pressure in the range of about 5 mTorr to about 20 mTorr. In one exemplary embodiment, the passivation step in the third processing cycle uses, for example, a plasma formed from a gas mixture comprising N2 and / or O2.

[0103] Figure 15 A processing step 153 of the third processing cycle in a cyclic process is shown. Processing step 153 is performed to bombard and soften the passivation layer 143c, thereby allowing easy removal of the softened passivation layer 143c during a subsequent etching step in the next processing cycle. Processing step 153 of the third processing cycle is substantially the same as processing step 149 of the second processing cycle, except that a greater bias power is used. In some embodiments, the bias power used during processing step 153 of the third processing cycle (e.g., about 500 W to about 1000 W) is greater than the bias power used in processing step 149 of the second processing cycle (e.g., 300 W to about 500 W), and the source power used during processing step 153 of the third processing cycle (e.g., about 50 W to about 100 W) is substantially the same as the source power used in processing step 149 of the second processing cycle (e.g., about 50 W to about 100 W). In some embodiments, processing step 153 in the third processing cycle can be performed in the same processing chamber as the passivation step of the third processing cycle. The processing chamber can operate at pressures in the range of about 50 mTorr to about 100 mTorr.

[0104] Figure 16 The semiconductor device structure 100 after etching step 155 is shown. Etching step 155 is performed to remove the softened passivation layer 143c. Figure 15 The fourth portion of the trench 1802 is formed by combining the substrate 101 with a portion of the substrate 101. The fourth portion of the trench 1802 is formed to have a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the trench 1802 in the depth direction of the trench 1802. In some embodiments, the fourth portion of the trench 1802 has a tapered profile at the bottom.

[0105] Etching step 155 can be performed using similar or the same etching chemicals as etching step 151. Except for using a higher bias power, etching step 155 is substantially the same as etching step 151. In some embodiments, the bias power used in etching step 155 is greater than the bias power used in processing step 153 in the third processing cycle.

[0106] In one embodiment, the source power used during etching step 155 (e.g., about 100 W to about 300 W) is substantially the same as the source power used during etching step 151 performed in the third step (e.g., about 100 W to about 300 W), and the bias power used during etching step 155 (e.g., about 400 W to about 700 W) is greater than the bias power used during etching step 151 performed in the third process cycle (e.g., about 300 W to about 600 W). The processing chamber pressure used during etching step 155 and etching step 151 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In one exemplary embodiment, etching step 155 uses a plasma formed from a gas mixture comprising, for example, CH4, Cl2, HBr, and CHF3.

[0107] Etching step 155 further extends the depth of trench 1802. Etching step 155 may be performed until trench 1802 reaches a predetermined depth below the interface defined by the bottom second semiconductor layer 108 and substrate 101. After etching step 155, trench 1802 may have a depth D4 defined by the distance between the top first semiconductor layer 106 and the bottom surface 1802bs4 of trench 1802. In other words, the depth of trench 1802 extends from depth D3 to depth D4. In some embodiments, the bottom surface 1802bs4 of trench 1802 is approximately 5 nm to approximately 10 nm below the interface defined by the bottom second semiconductor layer 108 and substrate 101.

[0108] Figures 7 to 16The described process can be repeated two or more times until the desired depth of trench 1802 is reached. In some embodiments, the total number of processing cycles may correspond to the number of second semiconductor layers 108 in fin structure 112. In any case, the formed trench 1802 has a straight vertical sidewall profile and a substantially uniform critical dimension (CD) from top to bottom. In some embodiments, a first portion of trench 1802 at or near the topmost first semiconductor layer 106 has a first critical dimension CD1, a second portion of trench 1802 at or near the second highest first semiconductor layer 106 of semiconductor layer stack 104 has a second critical dimension CD2, and a third portion of trench 1802 at or near the third highest first semiconductor layer 106 of semiconductor layer stack 104 has a third critical dimension CD3. In some embodiments, the first critical dimension CD1, the second critical dimension CD2, and the third critical dimension CD3 are substantially the same. Each of the first semiconductor layers 106 in fin structure 112 may have a substantially identical width W1. In some embodiments with a gate pitch of about 40 nm to about 50 nm, the third critical dimension CD3 may be about 0 nm to about 1 nm wider than the width W1.

[0109] In some embodiments, the first critical dimension CD1 and the second critical dimension CD2 are substantially the same, and the third critical dimension CD3 is slightly smaller than the first critical dimension CD1 and the second critical dimension CD2, such as... Figure 16-1 The embodiment shown. In this case, the difference between the first critical size CD1 (or the second critical size CD2) and the third critical size CD3 is less than 2 nm, for example, about 0 nm to about 1 nm, for example, about 0.5 nm. The size of the first semiconductor layer 106 gradually increases along the direction away from the sacrificial gate dielectric layer 132.

[0110] exist Figure 17In the process, edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. Removing the edge portions of the second semiconductor layers 108 forms a recess. Next, a dielectric layer is formed on the exposed surfaces of the sacrificial gate structure 130 and the first semiconductor layer 106 and the second semiconductor layer 108. The dielectric layer fills the recess formed by removing the edge portions of the second semiconductor layers 108. Suitable materials for the dielectric layer may include, but are not limited to, SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN, and / or other suitable materials. The dielectric layer can be formed by a conformal deposition process (e.g., ALD). Next, a removal process, such as an anisotropic etching process, is performed such that only a portion of the dielectric layer remains in the recess to form internal spacers 144. The remaining second semiconductor layers 108 along the X direction are located between the internal spacers 144.

[0111] exist Figure 18 In this process, epitaxial S / D features 146 are formed in the source / drain (S / D) region. Epitaxial S / D features 146 can be grown vertically and horizontally to form facets that correspond to crystal planes of the material used for the first semiconductor layer 106. In some cases, epitaxial S / D features 146 of fin structures can be grown and merged with epitaxial S / D features 146 of adjacent fin structures. In any case, the epitaxial S / D features 146 are formed to have a substantially uniform critical dimension from top to bottom. For example, the dimensions of the epitaxial S / D features 146 can correspond to... Figure 16 The first critical dimension CD1, the second critical dimension CD2, and the third critical dimension CD3 are shown. One or more layers of the epitaxial S / D feature 146 may include Si, SiP, SiC, and SiCP for n-type FETs or Si, SiGe, and Ge for p-type FETs. The epitaxial S / D feature 146 can be formed using epitaxial growth methods such as selective epitaxial growth (SEG), CVD, ALD, or MBE. The epitaxial S / D feature 146 is in contact with the first semiconductor layer 106 and the internal spacer 144. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial S / D feature 146 by the internal spacer 144.

[0112] The epitaxial S / D feature 146 can be an S / D region. For example, one of a pair of epitaxial S / D features 146 located on one side of the sacrificial gate structure 130 can be a source region, and the other of a pair of epitaxial S / D features 146 located on the other side of the sacrificial gate structure 130 can be a drain region. A pair of epitaxial S / D features 146 includes a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). Depending on the context, the source / drain region can refer to the source or drain individually or jointly. In this disclosure, the source and drain are used interchangeably and have substantially the same structure.

[0113] In some embodiments, after the internal spacer 144 is formed, a faceted structure 148 is formed on the exposed surfaces of the first semiconductor layer 106 and the substrate 101 (e.g., well 116) to facilitate subsequent epitaxial growth of the epitaxial S / D feature 146. In some embodiments, a portion of the faceted structure 148 may further contact the internal spacer 144. The faceted structure 148 may be grown vertically and horizontally to form facets that may correspond to the crystal planes of the material of the first semiconductor layer 106 and the exposed surfaces of the substrate 101. Facets can be formed due to the different growth rates on different surface planes. For example, during the growth of the faceted structure 148, the first semiconductor layer 106 (e.g., silicon) undergoes a process where the growth rate of the material changes. <111> The growth rate on a planar surface can be lower than that on other planar surfaces (e.g., the first semiconductor layer 106). <110> plane and <100> The growth rate on the plane. Therefore, facets are formed due to the different growth rates on different planes. In one embodiment, the faceted structure 148 has a rhomboid shape. Compared to the exposed surface of the first semiconductor layer 106, the facets of the faceted structure 148 provide an increased surface area to facilitate the epitaxial growth of the S / D feature 146. Once the faceted structure 148 is formed, the S / D feature 146 can be grown on the faceted structure 148 and cover the exposed surface of the faceted structure 148.

[0114] In some embodiments, the faceted structure 148 comprises silicon. In some embodiments, the faceted structure 148 comprises silicon and an n-type or p-type dopant, depending on the conductivity type of the S / D feature 146 to be grown thereon. For example, the faceted structure 148 at an n-type device region may be silicon doped with an n-type dopant (e.g., phosphorus or arsenic), and the faceted structure 148 at a p-type device region may be silicon doped with a p-type dopant. Selective epitaxial growth (SEG), ALD, MBE, or any suitable growth process can be used to form the faceted structure 148. Process conditions of the growth process are configured according to the crystal planes of the first semiconductor layer 106 and the substrate 101 to facilitate faceting formation of the faceted structure 148. Once a predetermined volume of the faceted structure 148 is reached, the flow of the n-type or p-type doped precursor can be terminated, and a group IV or V precursor is introduced into the processing chamber along with the silicon-containing precursor to form the S / D feature 146. Thus, the faceted structure 148 is formed from a material with chemical properties different from those of the S / D feature 146. Dopant can be added during the formation of S / D feature 146, or by implantation process after the formation of S / D feature 146.

[0115] exist Figure 19 In this process, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D feature 146, and the semiconductor layer stack 104. CESL 162 may comprise an oxygen-containing or nitrogen-containing material and can be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of the first ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials, such as polymers, may also be used for the first ILD layer 164.

[0116] exist Figure 20 In the process, after the formation of the first ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. The sacrificial gate electrode layer 134, the gate spacer 138, the CESL 162, and the top surface of the first ILD layer 164 are substantially coplanar after CMP.

[0117] exist Figure 21In this process, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed. The sacrificial gate structure 130 and the second semiconductor layer 108 are removed to form an opening 166 between the first semiconductor layer 106. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the second semiconductor layer 108, the sacrificial gate electrode layer 134, and the sacrificial gate dielectric layer 132, but without removing the gate spacer 138, the first ILD layer 164, and the CESL 162. After the sacrificial gate structure 130 is removed, the first semiconductor layer 106 and the internal spacer 144 are exposed to the opening 166.

[0118] exist Figure 22 In this process, an alternative gate structure 190 is formed. The alternative gate structure 190 may each include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178 may also be formed on an exposed surface of the substrate 101. The IL 178 may include or be made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride, silicon oxynitride, oxide oxynitride, etc.), and / or dielectric layers (e.g., hafnium silicate) formed by thermal or chemical oxidation of the first semiconductor layer 106. Next, the gate dielectric layer 180 is formed on the exposed surfaces of the semiconductor device structure 100 (e.g., on the IL (if present), the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, and the CESL 162). The gate dielectric layer 180 may be formed of a material with chemical properties different from that of the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer produced by processes such as ALD, PECVD, molecular beam deposition (MBD), or combinations thereof.

[0119] After forming IL 178 and gate dielectric layer 180, gate electrode layer 182 is formed on gate dielectric layer 180. Gate electrode layer 182 fills opening 166 ( Figure 21The gate electrode layer 182 surrounds a portion of each of the first semiconductor layers 106. The gate electrode layer 182 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) may be conformally deposited (and if more than one, sequentially) between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers may include one or more barrier layers and / or capping layers, and one or more work function adjustment layers. One or more barrier layers and / or capping layers may include tantalum and / or titanium nitrides, silicon nitrides, carbon nitrides and / or aluminum nitrides; tungsten nitrides, carbon nitrides and / or carbides; the like; or combinations thereof. One or more work function regulating layers may include titanium and / or tantalum nitrides, silicon nitrides, carbon nitrides, aluminum nitrides, aluminum oxides and / or aluminum carbides; tungsten nitrides, tungsten nitrides and / or tungsten carbides; cobalt; platinum; the like; or combinations thereof.

[0120] Above the top surfaces of the first ILD layer 164, CESL 162, and gate spacer 138, a portion of the gate electrode layer 182, one or more optionally conformal layers, and the gate dielectric layer 180 can be removed by a planarization process, such as a CMP process. After the CMP process, the top surfaces of the first ILD layer 164, CESL 162, gate spacer 138, gate dielectric layer 180, and gate electrode layer 182 are substantially coplanar.

[0121] exist Figure 23In the process, a contact opening is formed through the first ILD layer 164 and CESL 162 to expose the epitaxial S / D feature 146. Next, a silicide layer 184 is formed on the epitaxial S / D feature 146, and a source / drain (S / D) contact 186 is formed in the contact opening on the silicide layer 184. The S / D contact 186 may include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact opening prior to the formation of the S / D contact 186. The silicide layer 184 electrically couples the epitaxial S / D feature 146 to the subsequent S / D contact 186 formed in the contact opening. The silicide layer 184 may include a metal or metal alloy silicide, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. Next, a planarization process, such as CMP, is performed to remove excess deposited contact material and expose the top surface of the gate electrode layer 182.

[0122] It should be understood that the semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end-of-line (BEOL) processes to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure 100 may also include back-side contacts (not shown) on the back side of the substrate 101, such that the source or drain of the epitaxial S / D feature 146 is connected to a back-side power rail (e.g., a positive voltage VDD or a negative voltage VSS) via the back-side contacts.

[0123] The embodiments disclosed herein provide improved etch profile control for forming source / drain trenches. Etch profile control is achieved through a cyclic process including etching, passivation, and processing steps, which allows for the formation of source / drain trenches with straight, vertical sidewall profiles without any bends. Compared to conventional nanosheet channel layers with tapered profiles, the channel resistance between the source and drain features is reduced, resulting in increased DC current. Consequently, device performance is improved.

[0124] This disclosure discloses a method for forming a semiconductor device structure. The method includes the following steps: Removing a portion of a fin structure at a source / drain region using a first etchant to form a trench with a first depth; Passivating the exposed surface of the trench to adjust the etch selectivity of the exposed surface to a second etchant, and forming a passivated surface; Performing a processing step on the passivated surface; Removing the passivated surface and a portion of the fin structure using a second etchant to form a trench with a second depth greater than the first depth.

[0125] According to some embodiments, the etching selectivity of the exposed surface is adjusted by forming a passivation layer on the exposed surface of the first portion of the trench. According to some embodiments, the passivation layer is formed by exposing the exposed surface of the first portion of the trench to a gas mixture comprising an oxygen-containing precursor or a nitrogen-containing precursor. According to some embodiments, the passivation layer has a thickness of about 1 nanometer to 3 nanometers. According to some embodiments, the passivation layer is bombarded with a neutral free radical material formed from a nitrogen-containing precursor and / or a hydrogen-containing precursor. According to some embodiments, the trench forms a straight, vertical sidewall profile. According to some embodiments, the first etchant and the second etchant are substantially the same. According to some embodiments, the first etchant and the second etchant comprise hydrocarbon-based etching chemicals, bromine-based etching chemicals, chlorine-based etching chemicals, and / or fluorine-based etching chemicals.

[0126] Another embodiment of this disclosure is a method for forming a semiconductor device structure. The method includes the following steps: (1) forming a fin structure, the fin structure including a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers. (2) performing a first etching process to form a trench having a first depth at the source / drain region of the fin structure, the first etching process using a first bias power. (3) passivating the exposed surface of the trench using a second bias power less than the first bias power. (4) processing the passivated exposed surface using a third bias power greater than the second bias power to form a passivated exposed surface. (5) performing a second etching process using a fourth bias power to extend the trench from the first depth to the second depth, wherein the fourth bias power is greater than the third bias power.

[0127] According to some embodiments, the method further includes repeating steps (2) to (5) as a cycle process after step (5) until the trench reaches a predetermined depth. According to some embodiments, the first bias power in the second processing cycle of the cycle process is greater than the first bias power in the first processing cycle. According to some embodiments, the second bias power in the second processing cycle of the cycle process is greater than the second bias power in the first processing cycle. According to some embodiments, the third bias power in the second processing cycle of the cycle process is greater than the third bias power in the first processing cycle. According to some embodiments, processing the passivated exposed surface includes bombarding the passivated exposed surface with a neutral free radical material formed by a nitrogen-containing gas and / or a hydrogen-containing gas. According to some embodiments, steps (2) to (5) are performed in the same processing chamber. According to some embodiments, the method further includes forming a faceted structure on the exposed surface of the first semiconductor layer and forming epitaxial source / drain features on the faceted structure within the trench after the trench reaches the predetermined depth, wherein the epitaxial source / drain features have substantially uniform critical dimensions along the thickness of the epitaxial source / drain features.

[0128] Another embodiment of this disclosure is a method for forming a semiconductor device structure. The method includes the following steps: A fin structure is provided comprising a plurality of alternately stacked channel layers and a plurality of sacrificial layers. A sacrificial gate structure and gate spacers are formed over a portion of the fin structure. A first etching process is performed to remove a first portion of the fin structure not covered by the sacrificial gate structure. The first portion is removed to form a trench extending through a first interface defined by a top sacrificial layer and a channel layer disposed directly beneath the top sacrificial layer. The method further includes forming a first passivation layer on the exposed surface of the trench. The first passivation layer is treated with plasma. A second etching process is performed to remove the first passivation layer and a second portion of the fin structure, such that the trench extends through a second interface defined by a second highest sacrificial layer in the fin structure and a channel layer disposed directly beneath the second highest sacrificial layer.

[0129] According to some embodiments, the source power used in the second etching process is greater than the source power of the first etching process, and the bias power used in the second etching process is greater than the bias power of the first etching process. According to some embodiments, the method further includes, after the second etching process, forming a second passivation layer on the exposed surface of the trench, treating the second passivation layer with plasma, and performing a third etching process to remove the second passivation layer and a third portion of the fin structure, such that the trench extends through a third interface defined by a third highest sacrificial layer in the fin structure and a channel layer disposed directly beneath the third highest sacrificial layer. According to some embodiments, the trench forms a straight, vertical sidewall profile.

[0130] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, a gate structure, and a source / drain structure. The fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate and has a first width. The second semiconductor layer is located on the first semiconductor layer, perpendicularly separated from the first semiconductor layer, and has a second width. The third semiconductor layer is located above the second semiconductor layer, perpendicularly separated from the second semiconductor layer, such that the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and has a third width, wherein the first width, the second width, and the third width are equal. The gate structure surrounds the fin structure and is located above the fin structure. The source / drain structure is located on the substrate, adjacent to the fin structure.

[0131] In some embodiments, the gate structure includes a gate electrode and a gate dielectric layer, the gate dielectric layer being located between the gate electrode and the fin structure. In some embodiments, the semiconductor device further includes a faceted structure located between the source / drain structure and the fin structure, and between the source / drain structure and the substrate. In some embodiments, the semiconductor device further includes a source / drain contact located on the source / drain structure.

[0132] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a first fin structure, a second fin structure, a gate structure, and a source / drain structure. The first fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate and has a first sidewall. The second semiconductor layer is located above the first semiconductor layer and has a second sidewall. The third semiconductor layer is located above the second semiconductor layer, such that the second semiconductor layer is located between the first and third semiconductor layers, and has a third sidewall. The second fin structure includes a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer. The fourth semiconductor layer is located on the substrate and has a fourth sidewall, wherein a first critical dimension is present between the fourth sidewall and the first sidewall. The fifth semiconductor layer is located above the first semiconductor layer and has a fifth sidewall, wherein a second critical dimension is present between the fifth sidewall and the second sidewall. The sixth semiconductor layer is located above the fifth semiconductor layer, such that the fifth semiconductor layer is located between the fourth and sixth semiconductor layers, and has a sixth sidewall, wherein a third critical dimension is present between the sixth sidewall and the third sidewall, and the first critical dimension, the second critical dimension, and the third critical dimension are equal. The gate structure surrounds the first fin structure and the second fin structure. The source / drain structure is located on the substrate, between the first fin structure and the second fin structure.

[0133] In some embodiments, the gate structure includes a gate electrode and a gate dielectric layer, the gate dielectric layer being located between the gate electrode and the first fin structure, and between the gate electrode and the second fin structure. In some embodiments, the semiconductor device further includes a source / drain contact located on the source / drain structure.

[0134] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, a gate structure, and a source / drain structure. The fin structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is located on the substrate. A second semiconductor layer is located above the first semiconductor layer and perpendicularly separated from it. A third semiconductor layer is located above the second semiconductor layer and perpendicularly separated from it, such that the second semiconductor layer is located between the first and third semiconductor layers. The gate structure surrounds the fin structure and is located on the fin structure. The source / drain structure is located on the substrate, adjacent to the fin structure, wherein the source / drain structure has a uniform critical dimension along the thickness direction.

[0135] In some embodiments, the semiconductor device further includes a faceted structure located between the source / drain structure and the fin structure, and between the source / drain structure and the substrate. In some embodiments, the semiconductor device further includes a source / drain contact located on the source / drain structure.

[0136] This document outlines the features of several embodiments of this disclosure to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; a fin structure comprising: a first semiconductor layer on the substrate having a first width; a second semiconductor layer on the first semiconductor layer vertically separated from the first semiconductor layer having a second width; and a third semiconductor layer on the second semiconductor layer vertically separated from the second semiconductor layer such that the second semiconductor layer is between the first semiconductor layer and the third semiconductor layer having a third width, wherein the first width, the second width, and the third width are equal; a gate structure surrounding the fin structure and on the fin structure; and 2. The semiconductor device according to claim 1, wherein a source / drain structure on the substrate adjacent to the fin structure. The gate structure comprises: a gate electrode; and 3. The semiconductor device according to claim 1, wherein a gate dielectric layer between the gate electrode and the fin structure. Further comprising:

4. The semiconductor device according to claim 1, wherein a facet structure between the source / drain structure and the fin structure and between the source / drain structure and the substrate. Further comprising:

5. A semiconductor device, characterized by comprising: a source / drain contact on the source / drain structure. Comprising: a substrate; a first fin structure comprising: a first semiconductor layer on the substrate having a first sidewall; a second semiconductor layer on the first semiconductor layer above having a second sidewall; and a third semiconductor layer on the second semiconductor layer above such that the second semiconductor layer is between the first semiconductor layer and the third semiconductor layer having a third sidewall; a second fin structure comprising: a fourth semiconductor layer on the substrate having a fourth sidewall, wherein the fourth sidewall has a first critical dimension to the first sidewall; a fifth semiconductor layer on the fourth semiconductor layer above having a fifth sidewall, wherein the fifth sidewall has a second critical dimension to the second sidewall; and a sixth semiconductor layer on the fifth semiconductor layer above such that the fifth semiconductor layer is between the fourth semiconductor layer and the sixth semiconductor layer having a sixth sidewall, wherein the sixth sidewall has a third critical dimension to the third sidewall, and the first critical dimension, the second critical dimension, and the third critical dimension are equal; a gate structure surrounding the first fin structure and the second fin structure; and 6. The semiconductor device according to claim 5, wherein a source / drain structure on the substrate between the first fin structure and the second fin structure. The gate structure comprises: a gate electrode; and 7. The semiconductor device according to claim 5, wherein a gate dielectric layer between the gate electrode and the first fin structure and between the gate electrode and the second fin structure. Further comprising:

8. A semiconductor device, characterized by comprising: a source / drain contact on the source / drain structure. Comprising: a substrate; a fin structure comprising: a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer above vertically separated from the first semiconductor layer; and a third semiconductor layer on the second semiconductor layer above vertically separated from the second semiconductor layer such that the second semiconductor layer is between the first semiconductor layer and the third semiconductor layer; a gate structure surrounding the fin structure and on the fin structure; and A source / drain structure is located on the substrate adjacent to the fin structure, wherein the source / drain structure has a uniform critical dimension in a thickness direction.

9. The semiconductor device according to claim 8, wherein Further comprising: A facet structure is located between the source / drain structure and the fin structure and between the source / drain structure and the substrate.

10. The semiconductor device according to claim 8, wherein Further comprising: A source / drain contact is located on the source / drain structure.

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